[mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/builtins-mips-msa.c b/test/CodeGen/builtins-mips-msa.c
index 2ff161a..51508ee 100644
--- a/test/CodeGen/builtins-mips-msa.c
+++ b/test/CodeGen/builtins-mips-msa.c
@@ -688,10 +688,10 @@
v8i16_r = __builtin_msa_shf_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.shf.h(
v4i32_r = __builtin_msa_shf_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.shf.w(
- v16i8_r = __builtin_msa_sld_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.sld.b(
- v8i16_r = __builtin_msa_sld_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.sld.h(
- v4i32_r = __builtin_msa_sld_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.sld.w(
- v2i64_r = __builtin_msa_sld_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.sld.d(
+ v16i8_r = __builtin_msa_sld_b(v16i8_a, 10); // CHECK: call <16 x i8> @llvm.mips.sld.b(
+ v8i16_r = __builtin_msa_sld_h(v8i16_a, 10); // CHECK: call <8 x i16> @llvm.mips.sld.h(
+ v4i32_r = __builtin_msa_sld_w(v4i32_a, 10); // CHECK: call <4 x i32> @llvm.mips.sld.w(
+ v2i64_r = __builtin_msa_sld_d(v2i64_a, 10); // CHECK: call <2 x i64> @llvm.mips.sld.d(
v16i8_r = __builtin_msa_sldi_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.sldi.b(
v8i16_r = __builtin_msa_sldi_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.sldi.h(