Update Clang for 3.5 rebase (r209713).
Change-Id: I8c9133b0f8f776dc915f270b60f94962e771bc83
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index fd59c00..9343542 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -384,6 +384,17 @@
Builder.defineMacro("__ELF__");
if (Opts.POSIXThreads)
Builder.defineMacro("_POSIX_THREADS");
+
+ switch (Triple.getArch()) {
+ default:
+ break;
+ case llvm::Triple::arm:
+ case llvm::Triple::armeb:
+ case llvm::Triple::thumb:
+ case llvm::Triple::thumbeb:
+ Builder.defineMacro("__ARM_DWARF_EH__");
+ break;
+ }
}
public:
NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
@@ -445,7 +456,6 @@
public:
BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
this->UserLabelPrefix = "";
- this->TLSSupported = false;
this->MCountName = "__mcount";
}
};
@@ -1346,7 +1356,7 @@
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
// No aliases.
- Aliases = 0;
+ Aliases = nullptr;
NumAliases = 0;
}
bool validateAsmConstraint(const char *&Name,
@@ -1439,7 +1449,7 @@
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
static const char *DescriptionStringSI =
- "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64"
+ "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
@@ -1473,13 +1483,13 @@
void getGCCRegNames(const char * const *&Names,
unsigned &numNames) const override {
- Names = NULL;
+ Names = nullptr;
numNames = 0;
}
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
- Aliases = NULL;
+ Aliases = nullptr;
NumAliases = 0;
}
@@ -1490,7 +1500,7 @@
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
- Records = NULL;
+ Records = nullptr;
NumRecords = 0;
}
@@ -1769,6 +1779,7 @@
CK_BDVER1,
CK_BDVER2,
CK_BDVER3,
+ CK_BDVER4,
//@}
/// This specification is deprecated and will be removed in the future.
@@ -1818,7 +1829,7 @@
}
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
- Aliases = 0;
+ Aliases = nullptr;
NumAliases = 0;
}
void getGCCAddlRegNames(const AddlRegName *&Names,
@@ -1912,6 +1923,7 @@
.Case("bdver1", CK_BDVER1)
.Case("bdver2", CK_BDVER2)
.Case("bdver3", CK_BDVER3)
+ .Case("bdver4", CK_BDVER4)
.Case("x86-64", CK_x86_64)
.Case("geode", CK_Geode)
.Default(CK_Generic);
@@ -1981,6 +1993,7 @@
case CK_BDVER1:
case CK_BDVER2:
case CK_BDVER3:
+ case CK_BDVER4:
case CK_x86_64:
return true;
}
@@ -2183,6 +2196,10 @@
setFeatureEnabledImpl(Features, "prfchw", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
+ case CK_BDVER4:
+ setFeatureEnabledImpl(Features, "avx2", true);
+ setFeatureEnabledImpl(Features, "bmi2", true);
+ // FALLTHROUGH
case CK_BDVER2:
case CK_BDVER3:
setFeatureEnabledImpl(Features, "xop", true);
@@ -2686,6 +2703,9 @@
case CK_BDVER3:
defineCPUMacros(Builder, "bdver3");
break;
+ case CK_BDVER4:
+ defineCPUMacros(Builder, "bdver4");
+ break;
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
@@ -3051,7 +3071,6 @@
public:
WindowsX86_32TargetInfo(const llvm::Triple &Triple)
: WindowsTargetInfo<X86_32TargetInfo>(Triple) {
- TLSSupported = false;
WCharType = UnsignedShort;
DoubleAlign = LongLongAlign = 64;
DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
@@ -3066,9 +3085,9 @@
namespace {
// x86-32 Windows Visual Studio target
-class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
+class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
public:
- VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
+ MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
: WindowsX86_32TargetInfo(Triple) {
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
@@ -3085,6 +3104,33 @@
};
} // end anonymous namespace
+static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
+ Builder.defineMacro("__MSVCRT__");
+ Builder.defineMacro("__MINGW32__");
+
+ // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
+ // __declspec natively under -fms-extensions, but we define a no-op __declspec
+ // macro anyway for pre-processor compatibility.
+ if (Opts.MicrosoftExt)
+ Builder.defineMacro("__declspec", "__declspec");
+ else
+ Builder.defineMacro("__declspec(a)", "__attribute__((a))");
+
+ if (!Opts.MicrosoftExt) {
+ // Provide macros for all the calling convention keywords. Provide both
+ // single and double underscore prefixed variants. These are available on
+ // x64 as well as x86, even though they have no effect.
+ const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
+ for (const char *CC : CCs) {
+ std::string GCCSpelling = "__attribute__((__";
+ GCCSpelling += CC;
+ GCCSpelling += "__))";
+ Builder.defineMacro(Twine("_") + CC, GCCSpelling);
+ Builder.defineMacro(Twine("__") + CC, GCCSpelling);
+ }
+ }
+}
+
namespace {
// x86-32 MinGW target
class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
@@ -3097,17 +3143,7 @@
DefineStd(Builder, "WIN32", Opts);
DefineStd(Builder, "WINNT", Opts);
Builder.defineMacro("_X86_");
- Builder.defineMacro("__MSVCRT__");
- Builder.defineMacro("__MINGW32__");
-
- // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
- // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
- if (Opts.MicrosoftExt)
- // Provide "as-is" __declspec.
- Builder.defineMacro("__declspec", "__declspec");
- else
- // Provide alias of __attribute__ like mingw32-gcc.
- Builder.defineMacro("__declspec(a)", "__attribute__((a))");
+ addMinGWDefines(Opts, Builder);
}
};
} // end anonymous namespace
@@ -3270,7 +3306,6 @@
public:
WindowsX86_64TargetInfo(const llvm::Triple &Triple)
: WindowsTargetInfo<X86_64TargetInfo>(Triple) {
- TLSSupported = false;
WCharType = UnsignedShort;
LongWidth = LongAlign = 32;
DoubleAlign = LongLongAlign = 64;
@@ -3300,9 +3335,9 @@
namespace {
// x86-64 Windows Visual Studio target
-class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
+class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
public:
- VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
+ MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
: WindowsX86_64TargetInfo(Triple) {
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
@@ -3327,18 +3362,8 @@
MacroBuilder &Builder) const override {
WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "WIN64", Opts);
- Builder.defineMacro("__MSVCRT__");
- Builder.defineMacro("__MINGW32__");
Builder.defineMacro("__MINGW64__");
-
- // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
- // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
- if (Opts.MicrosoftExt)
- // Provide "as-is" __declspec.
- Builder.defineMacro("__declspec", "__declspec");
- else
- // Provide alias of __attribute__ like mingw32-gcc.
- Builder.defineMacro("__declspec(a)", "__attribute__((a))");
+ addMinGWDefines(Opts, Builder);
}
};
} // end anonymous namespace
@@ -3383,282 +3408,6 @@
};
}
-namespace {
-class AArch64TargetInfo : public TargetInfo {
- virtual void setDescriptionString() = 0;
- static const char * const GCCRegNames[];
- static const TargetInfo::GCCRegAlias GCCRegAliases[];
-
- enum FPUModeEnum {
- FPUMode,
- NeonMode
- };
-
- unsigned FPU;
- unsigned Crypto;
- static const Builtin::Info BuiltinInfo[];
-
-public:
- AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
- LongWidth = LongAlign = 64;
- LongDoubleWidth = LongDoubleAlign = 128;
- PointerWidth = PointerAlign = 64;
- SuitableAlign = 128;
-
- WCharType = UnsignedInt;
- if (getTriple().getOS() == llvm::Triple::NetBSD) {
- WCharType = SignedInt;
- Int64Type = SignedLongLong;
- IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
- } else {
- WCharType = UnsignedInt;
- Int64Type = SignedLong;
- IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
- }
- LongDoubleFormat = &llvm::APFloat::IEEEquad;
-
- // AArch64 backend supports 64-bit operations at the moment. In principle
- // 128-bit is possible if register-pairs are used.
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
-
- TheCXXABI.set(TargetCXXABI::GenericAArch64);
- }
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
- // GCC defines theses currently
- Builder.defineMacro("__aarch64__");
-
- // ACLE predefines. Many can only have one possible value on v8 AArch64.
- Builder.defineMacro("__ARM_ACLE", "200");
- Builder.defineMacro("__ARM_ARCH", "8");
- Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
-
- Builder.defineMacro("__ARM_64BIT_STATE");
- Builder.defineMacro("__ARM_PCS_AAPCS64");
- Builder.defineMacro("__ARM_ARCH_ISA_A64");
-
- Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
- Builder.defineMacro("__ARM_FEATURE_CLZ");
- Builder.defineMacro("__ARM_FEATURE_FMA");
- Builder.defineMacro("__ARM_FEATURE_DIV");
-
- Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
-
- // 0xe implies support for half, single and double precision operations.
- Builder.defineMacro("__ARM_FP", "0xe");
-
- // PCS specifies this for SysV variants, which is all we support. Other ABIs
- // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
- Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
-
- if (Opts.FastMath || Opts.FiniteMathOnly)
- Builder.defineMacro("__ARM_FP_FAST");
-
- if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
- Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
-
- Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
- Opts.ShortWChar ? "2" : "4");
-
- Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
- Opts.ShortEnums ? "1" : "4");
-
- if (FPU == NeonMode) {
- Builder.defineMacro("__ARM_NEON");
- // 64-bit NEON supports half, single and double precision operations.
- Builder.defineMacro("__ARM_NEON_FP", "7");
- }
-
- if (Crypto) {
- Builder.defineMacro("__ARM_FEATURE_CRYPTO");
- }
- }
- void getTargetBuiltins(const Builtin::Info *&Records,
- unsigned &NumRecords) const override {
- Records = BuiltinInfo;
- NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
- }
- bool hasFeature(StringRef Feature) const override {
- return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
- }
-
- bool setCPU(const std::string &Name) override {
- return llvm::StringSwitch<bool>(Name)
- .Case("generic", true)
- .Cases("cortex-a53", "cortex-a57", true)
- .Default(false);
- }
-
- bool handleTargetFeatures(std::vector<std::string> &Features,
- DiagnosticsEngine &Diags) override {
- FPU = FPUMode;
- Crypto = 0;
- for (unsigned i = 0, e = Features.size(); i != e; ++i) {
- if (Features[i] == "+neon")
- FPU = NeonMode;
- if (Features[i] == "+crypto")
- Crypto = 1;
- }
-
- setDescriptionString();
-
- return true;
- }
-
- void getGCCRegNames(const char *const *&Names,
- unsigned &NumNames) const override;
- void getGCCRegAliases(const GCCRegAlias *&Aliases,
- unsigned &NumAliases) const override;
-
- bool isCLZForZeroUndef() const override { return false; }
-
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- switch (*Name) {
- default: return false;
- case 'w': // An FP/SIMD vector register
- Info.setAllowsRegister();
- return true;
- case 'I': // Constant that can be used with an ADD instruction
- case 'J': // Constant that can be used with a SUB instruction
- case 'K': // Constant that can be used with a 32-bit logical instruction
- case 'L': // Constant that can be used with a 64-bit logical instruction
- case 'M': // Constant that can be used as a 32-bit MOV immediate
- case 'N': // Constant that can be used as a 64-bit MOV immediate
- case 'Y': // Floating point constant zero
- case 'Z': // Integer constant zero
- return true;
- case 'Q': // A memory reference with base register and no offset
- Info.setAllowsMemory();
- return true;
- case 'S': // A symbolic address
- Info.setAllowsRegister();
- return true;
- case 'U':
- // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
- // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
- // Usa: An absolute symbolic address
- // Ush: The high part (bits 32:12) of a pc-relative symbolic address
- llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
- }
- }
-
- const char *getClobbers() const override {
- // There are no AArch64 clobbers shared by all asm statements.
- return "";
- }
-
- BuiltinVaListKind getBuiltinVaListKind() const override {
- return TargetInfo::AArch64ABIBuiltinVaList;
- }
-};
-
-const char * const AArch64TargetInfo::GCCRegNames[] = {
- "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
- "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
- "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
- "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
-
- "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
- "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
- "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
- "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
-
- "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
- "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
- "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
- "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
-
- "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
- "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
- "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
- "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
-
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
- "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
- "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
- "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
-
- "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
- "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
- "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
- "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
-
- "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
- "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
- "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
- "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
-};
-
-void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
- unsigned &NumNames) const {
- Names = GCCRegNames;
- NumNames = llvm::array_lengthof(GCCRegNames);
-}
-
-const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
- { { "x16" }, "ip0"},
- { { "x17" }, "ip1"},
- { { "x29" }, "fp" },
- { { "x30" }, "lr" }
-};
-
-void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
- unsigned &NumAliases) const {
- Aliases = GCCRegAliases;
- NumAliases = llvm::array_lengthof(GCCRegAliases);
-
-}
-
-const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
-#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
-#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
- ALL_LANGUAGES },
-#include "clang/Basic/BuiltinsNEON.def"
-
-#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
-#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
- ALL_LANGUAGES },
-#include "clang/Basic/BuiltinsAArch64.def"
-};
-
-class AArch64leTargetInfo : public AArch64TargetInfo {
- void setDescriptionString() override {
- DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
- }
-
-public:
- AArch64leTargetInfo(const llvm::Triple &Triple)
- : AArch64TargetInfo(Triple) {
- BigEndian = false;
- }
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
- Builder.defineMacro("__AARCH64EL__");
- AArch64TargetInfo::getTargetDefines(Opts, Builder);
- }
-};
-
-class AArch64beTargetInfo : public AArch64TargetInfo {
- void setDescriptionString() override {
- DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
- }
-
-public:
- AArch64beTargetInfo(const llvm::Triple &Triple)
- : AArch64TargetInfo(Triple) { }
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
- Builder.defineMacro("__AARCH64EB__");
- Builder.defineMacro("__AARCH_BIG_ENDIAN");
- Builder.defineMacro("__ARM_BIG_ENDIAN");
- AArch64TargetInfo::getTargetDefines(Opts, Builder);
- }
-};
-
-} // end anonymous namespace
namespace {
class ARMTargetInfo : public TargetInfo {
@@ -3708,6 +3457,9 @@
static const Builtin::Info BuiltinInfo[];
static bool shouldUseInlineAtomic(const llvm::Triple &T) {
+ if (T.isOSWindows())
+ return true;
+
// On linux, binaries targeting old cpus call functions in libgcc to
// perform atomic operations. The implementation in libgcc then calls into
// the kernel which on armv6 and newer uses ldrex and strex. The net result
@@ -3760,11 +3512,18 @@
else
SizeType = UnsignedInt;
- if (T.getOS() == llvm::Triple::NetBSD) {
+ switch (T.getOS()) {
+ case llvm::Triple::NetBSD:
WCharType = SignedInt;
- } else {
+ break;
+ case llvm::Triple::Win32:
+ WCharType = UnsignedShort;
+ break;
+ case llvm::Triple::Linux:
+ default:
// AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
WCharType = UnsignedInt;
+ break;
}
UseBitFieldTypeAlignment = true;
@@ -3774,19 +3533,30 @@
if (IsThumb) {
// Thumb1 add sp, #imm requires the immediate value be multiple of 4,
// so set preferred for small types to 32.
- if (T.isOSBinFormatMachO())
+ if (T.isOSBinFormatMachO()) {
DescriptionString = BigEndian ?
"E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
"v128:64:128-a:0:32-n32-S64" :
"e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
"v128:64:128-a:0:32-n32-S64";
- else
+ } else if (T.isOSWindows()) {
+ // FIXME: this is invalid for WindowsCE
+ assert(!BigEndian && "Windows on ARM does not support big endian");
+ DescriptionString = "e"
+ "-m:e"
+ "-p:32:32"
+ "-i1:8:32-i8:8:32-i16:16:32-i64:64"
+ "-v128:64:128"
+ "-a:0:32"
+ "-n32"
+ "-S64";
+ } else {
DescriptionString = BigEndian ?
"E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
"v128:64:128-a:0:32-n32-S64" :
"e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
"v128:64:128-a:0:32-n32-S64";
-
+ }
} else {
if (T.isOSBinFormatMachO())
DescriptionString = BigEndian ?
@@ -4052,7 +3822,7 @@
.Cases("cortex-m3", "cortex-m4", "7M")
.Case("cortex-m0", "6M")
.Cases("cortex-a53", "cortex-a57", "8A")
- .Default(0);
+ .Default(nullptr);
}
static const char *getCPUProfile(StringRef Name) {
return llvm::StringSwitch<const char*>(Name)
@@ -4095,12 +3865,14 @@
// FIXME: It's more complicated than this and we don't really support
// interworking.
- if (5 <= CPUArchVer && CPUArchVer <= 8)
+ // Windows on ARM does not "support" interworking
+ if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
Builder.defineMacro("__THUMB_INTERWORK__");
if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
// Embedded targets on Darwin follow AAPCS, but not EABI.
- if (!getTriple().isOSDarwin())
+ // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
+ if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
Builder.defineMacro("__ARM_EABI__");
Builder.defineMacro("__ARM_PCS", "1");
@@ -4373,6 +4145,72 @@
} // end anonymous namespace.
namespace {
+class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
+ const llvm::Triple Triple;
+public:
+ WindowsARMTargetInfo(const llvm::Triple &Triple)
+ : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
+ TLSSupported = false;
+ WCharType = UnsignedShort;
+ SizeType = UnsignedInt;
+ UserLabelPrefix = "";
+ }
+ void getVisualStudioDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const {
+ WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
+
+ // FIXME: this is invalid for WindowsCE
+ Builder.defineMacro("_M_ARM_NT", "1");
+ Builder.defineMacro("_M_ARMT", "_M_ARM");
+ Builder.defineMacro("_M_THUMB", "_M_ARM");
+
+ assert((Triple.getArch() == llvm::Triple::arm ||
+ Triple.getArch() == llvm::Triple::thumb) &&
+ "invalid architecture for Windows ARM target info");
+ unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
+ Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
+
+ // TODO map the complete set of values
+ // 31: VFPv3 40: VFPv4
+ Builder.defineMacro("_M_ARM_FP", "31");
+ }
+};
+
+// Windows ARM + Itanium C++ ABI Target
+class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
+public:
+ ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
+ : WindowsARMTargetInfo(Triple) {
+ TheCXXABI.set(TargetCXXABI::GenericARM);
+ }
+
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
+
+ if (Opts.MSVCCompat)
+ WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
+ }
+};
+
+// Windows ARM, MS (C++) ABI
+class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
+public:
+ MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
+ : WindowsARMTargetInfo(Triple) {
+ TheCXXABI.set(TargetCXXABI::Microsoft);
+ }
+
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
+ WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
+ }
+};
+}
+
+
+namespace {
class DarwinARMTargetInfo :
public DarwinTargetInfo<ARMleTargetInfo> {
protected:
@@ -4397,23 +4235,44 @@
namespace {
-class ARM64TargetInfo : public TargetInfo {
+class AArch64TargetInfo : public TargetInfo {
+ virtual void setDescriptionString() = 0;
static const TargetInfo::GCCRegAlias GCCRegAliases[];
static const char *const GCCRegNames[];
+ enum FPUModeEnum {
+ FPUMode,
+ NeonMode
+ };
+
+ unsigned FPU;
+ unsigned CRC;
+ unsigned Crypto;
+
static const Builtin::Info BuiltinInfo[];
std::string ABI;
public:
- ARM64TargetInfo(const llvm::Triple &Triple)
+ AArch64TargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), ABI("aapcs") {
- BigEndian = false;
+
+ if (getTriple().getOS() == llvm::Triple::NetBSD) {
+ WCharType = SignedInt;
+
+ // NetBSD apparently prefers consistency across ARM targets to consistency
+ // across 64-bit targets.
+ Int64Type = SignedLongLong;
+ IntMaxType = SignedLongLong;
+ UIntMaxType = UnsignedLongLong;
+ } else {
+ WCharType = UnsignedInt;
+ Int64Type = SignedLong;
+ IntMaxType = SignedLong;
+ UIntMaxType = UnsignedLong;
+ }
+
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
- IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
- Int64Type = SignedLong;
- WCharType = UnsignedInt;
MaxVectorAlign = 128;
RegParmMax = 8;
MaxAtomicInlineWidth = 128;
@@ -4422,16 +4281,11 @@
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad;
- if (Triple.isOSBinFormatMachO())
- DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
- else
- DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
-
// {} in inline assembly are neon specifiers, not assembly variant
// specifiers.
NoAsmVariants = true;
- // ARM64 targets default to using the ARM C++ ABI.
+ // AArch64 targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
@@ -4446,7 +4300,8 @@
virtual bool setCPU(const std::string &Name) {
bool CPUKnown = llvm::StringSwitch<bool>(Name)
- .Case("arm64-generic", true)
+ .Case("generic", true)
+ .Cases("cortex-a53", "cortex-a57", true)
.Case("cyclone", true)
.Default(false);
return CPUKnown;
@@ -4455,23 +4310,11 @@
virtual void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
- Builder.defineMacro("__arm64");
- Builder.defineMacro("__arm64__");
Builder.defineMacro("__aarch64__");
- Builder.defineMacro("__ARM64_ARCH_8__");
- Builder.defineMacro("__AARCH64_SIMD__");
- Builder.defineMacro("__ARM_NEON__");
// Target properties.
Builder.defineMacro("_LP64");
Builder.defineMacro("__LP64__");
- Builder.defineMacro("__LITTLE_ENDIAN__");
-
- // Subtarget options.
- Builder.defineMacro("__REGISTER_PREFIX__", "");
-
- Builder.defineMacro("__aarch64__");
- Builder.defineMacro("__AARCH64EL__");
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
@@ -4507,31 +4350,48 @@
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
Opts.ShortEnums ? "1" : "4");
- if (BigEndian)
- Builder.defineMacro("__ARM_BIG_ENDIAN");
+ if (FPU == NeonMode) {
+ Builder.defineMacro("__ARM_NEON");
+ // 64-bit NEON supports half, single and double precision operations.
+ Builder.defineMacro("__ARM_NEON_FP", "0xe");
+ }
- // FIXME: the target should support NEON as an optional extension, like
- // the OSS AArch64.
- Builder.defineMacro("__ARM_NEON");
- // 64-bit NEON supports half, single and double precision operations.
- Builder.defineMacro("__ARM_NEON_FP", "7");
+ if (CRC)
+ Builder.defineMacro("__ARM_FEATURE_CRC32");
- // FIXME: the target should support crypto as an optional extension, like
- // the OSS AArch64
- Builder.defineMacro("__ARM_FEATURE_CRYPTO");
+ if (Crypto)
+ Builder.defineMacro("__ARM_FEATURE_CRYPTO");
}
virtual void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const {
Records = BuiltinInfo;
- NumRecords = clang::ARM64::LastTSBuiltin - Builtin::FirstTSBuiltin;
+ NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
}
virtual bool hasFeature(StringRef Feature) const {
- return llvm::StringSwitch<bool>(Feature)
- .Case("arm64", true)
- .Case("neon", true)
- .Default(false);
+ return Feature == "aarch64" ||
+ Feature == "arm64" ||
+ (Feature == "neon" && FPU == NeonMode);
+ }
+
+ bool handleTargetFeatures(std::vector<std::string> &Features,
+ DiagnosticsEngine &Diags) override {
+ FPU = FPUMode;
+ CRC = 0;
+ Crypto = 0;
+ for (unsigned i = 0, e = Features.size(); i != e; ++i) {
+ if (Features[i] == "+neon")
+ FPU = NeonMode;
+ if (Features[i] == "+crc")
+ CRC = 1;
+ if (Features[i] == "+crypto")
+ Crypto = 1;
+ }
+
+ setDescriptionString();
+
+ return true;
}
virtual bool isCLZForZeroUndef() const { return false; }
@@ -4553,46 +4413,37 @@
case 'w': // Floating point and SIMD registers (V0-V31)
Info.setAllowsRegister();
return true;
+ case 'I': // Constant that can be used with an ADD instruction
+ case 'J': // Constant that can be used with a SUB instruction
+ case 'K': // Constant that can be used with a 32-bit logical instruction
+ case 'L': // Constant that can be used with a 64-bit logical instruction
+ case 'M': // Constant that can be used as a 32-bit MOV immediate
+ case 'N': // Constant that can be used as a 64-bit MOV immediate
+ case 'Y': // Floating point constant zero
+ case 'Z': // Integer constant zero
+ return true;
+ case 'Q': // A memory reference with base register and no offset
+ Info.setAllowsMemory();
+ return true;
+ case 'S': // A symbolic address
+ Info.setAllowsRegister();
+ return true;
+ case 'U':
+ // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
+ // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
+ // Usa: An absolute symbolic address
+ // Ush: The high part (bits 32:12) of a pc-relative symbolic address
+ llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
case 'z': // Zero register, wzr or xzr
Info.setAllowsRegister();
return true;
case 'x': // Floating point and SIMD registers (V0-V15)
Info.setAllowsRegister();
return true;
- case 'Q': // A memory address that is a single base register.
- Info.setAllowsMemory();
- return true;
}
return false;
}
- virtual bool validateConstraintModifier(StringRef Constraint,
- const char Modifier,
- unsigned Size) const {
- // Strip off constraint modifiers.
- while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
- Constraint = Constraint.substr(1);
-
- switch (Constraint[0]) {
- default:
- return true;
- case 'z':
- case 'r': {
- switch (Modifier) {
- case 'x':
- case 'w':
- // For now assume that the person knows what they're
- // doing with the modifier.
- return true;
- default:
- // By default an 'r' constraint will be in the 'x'
- // registers.
- return (Size == 64);
- }
- }
- }
- }
-
virtual const char *getClobbers() const { return ""; }
int getEHDataRegisterNumber(unsigned RegNo) const {
@@ -4604,7 +4455,7 @@
}
};
-const char *const ARM64TargetInfo::GCCRegNames[] = {
+const char *const AArch64TargetInfo::GCCRegNames[] = {
// 32-bit Integer registers
"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
"w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
@@ -4631,13 +4482,13 @@
"v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
};
-void ARM64TargetInfo::getGCCRegNames(const char *const *&Names,
+void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
unsigned &NumNames) const {
Names = GCCRegNames;
NumNames = llvm::array_lengthof(GCCRegNames);
}
-const TargetInfo::GCCRegAlias ARM64TargetInfo::GCCRegAliases[] = {
+const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
{ { "w31" }, "wsp" },
{ { "x29" }, "fp" },
{ { "x30" }, "lr" },
@@ -4646,28 +4497,80 @@
// don't want to substitute one of these for a different-sized one.
};
-void ARM64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
+void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const {
Aliases = GCCRegAliases;
NumAliases = llvm::array_lengthof(GCCRegAliases);
}
-const Builtin::Info ARM64TargetInfo::BuiltinInfo[] = {
+const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
#define BUILTIN(ID, TYPE, ATTRS) \
{ #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#include "clang/Basic/BuiltinsNEON.def"
#define BUILTIN(ID, TYPE, ATTRS) \
{ #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
-#include "clang/Basic/BuiltinsARM64.def"
+#include "clang/Basic/BuiltinsAArch64.def"
+};
+
+class AArch64leTargetInfo : public AArch64TargetInfo {
+ void setDescriptionString() override {
+ if (getTriple().isOSBinFormatMachO())
+ DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
+ else
+ DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
+ }
+
+public:
+ AArch64leTargetInfo(const llvm::Triple &Triple)
+ : AArch64TargetInfo(Triple) {
+ BigEndian = false;
+ }
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__AARCH64EL__");
+ AArch64TargetInfo::getTargetDefines(Opts, Builder);
+ }
+};
+
+class AArch64beTargetInfo : public AArch64TargetInfo {
+ void setDescriptionString() override {
+ assert(!getTriple().isOSBinFormatMachO());
+ DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
+ }
+
+public:
+ AArch64beTargetInfo(const llvm::Triple &Triple)
+ : AArch64TargetInfo(Triple) { }
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__AARCH64EB__");
+ Builder.defineMacro("__AARCH_BIG_ENDIAN");
+ Builder.defineMacro("__ARM_BIG_ENDIAN");
+ AArch64TargetInfo::getTargetDefines(Opts, Builder);
+ }
};
} // end anonymous namespace.
namespace {
-class DarwinARM64TargetInfo : public DarwinTargetInfo<ARM64TargetInfo> {
+class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
+protected:
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__AARCH64_SIMD__");
+ Builder.defineMacro("__ARM64_ARCH_8__");
+ Builder.defineMacro("__ARM_NEON__");
+ Builder.defineMacro("__LITTLE_ENDIAN__");
+ Builder.defineMacro("__REGISTER_PREFIX__", "");
+ Builder.defineMacro("__arm64", "1");
+ Builder.defineMacro("__arm64__", "1");
+
+ getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
+ }
+
public:
- DarwinARM64TargetInfo(const llvm::Triple &Triple)
- : DarwinTargetInfo<ARM64TargetInfo>(Triple) {
+ DarwinAArch64TargetInfo(const llvm::Triple &Triple)
+ : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
Int64Type = SignedLongLong;
WCharType = SignedInt;
UseSignedCharForObjCBool = false;
@@ -4734,7 +4637,7 @@
return llvm::StringSwitch<const char*>(Name)
.Case("hexagonv4", "4")
.Case("hexagonv5", "5")
- .Default(0);
+ .Default(nullptr);
}
bool setCPU(const std::string &Name) override {
@@ -5040,107 +4943,107 @@
} // end anonymous namespace.
namespace {
- class SystemZTargetInfo : public TargetInfo {
- static const char *const GCCRegNames[];
+class SystemZTargetInfo : public TargetInfo {
+ static const char *const GCCRegNames[];
- public:
- SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
- TLSSupported = true;
- IntWidth = IntAlign = 32;
- LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
- PointerWidth = PointerAlign = 64;
- LongDoubleWidth = 128;
- LongDoubleAlign = 64;
- LongDoubleFormat = &llvm::APFloat::IEEEquad;
- MinGlobalAlign = 16;
- DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
- }
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
- Builder.defineMacro("__s390__");
- Builder.defineMacro("__s390x__");
- Builder.defineMacro("__zarch__");
- Builder.defineMacro("__LONG_DOUBLE_128__");
- }
- void getTargetBuiltins(const Builtin::Info *&Records,
- unsigned &NumRecords) const override {
- // FIXME: Implement.
- Records = 0;
- NumRecords = 0;
- }
-
- void getGCCRegNames(const char *const *&Names,
- unsigned &NumNames) const override;
- void getGCCRegAliases(const GCCRegAlias *&Aliases,
- unsigned &NumAliases) const override {
- // No aliases.
- Aliases = 0;
- NumAliases = 0;
- }
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const override;
- const char *getClobbers() const override {
- // FIXME: Is this really right?
- return "";
- }
- BuiltinVaListKind getBuiltinVaListKind() const override {
- return TargetInfo::SystemZBuiltinVaList;
- }
- bool setCPU(const std::string &Name) override {
- bool CPUKnown = llvm::StringSwitch<bool>(Name)
- .Case("z10", true)
- .Case("z196", true)
- .Case("zEC12", true)
- .Default(false);
-
- // No need to store the CPU yet. There aren't any CPU-specific
- // macros to define.
- return CPUKnown;
- }
- };
-
- const char *const SystemZTargetInfo::GCCRegNames[] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
- "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
- };
-
- void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
- unsigned &NumNames) const {
- Names = GCCRegNames;
- NumNames = llvm::array_lengthof(GCCRegNames);
+public:
+ SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
+ TLSSupported = true;
+ IntWidth = IntAlign = 32;
+ LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
+ PointerWidth = PointerAlign = 64;
+ LongDoubleWidth = 128;
+ LongDoubleAlign = 64;
+ LongDoubleFormat = &llvm::APFloat::IEEEquad;
+ MinGlobalAlign = 16;
+ DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
+ MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+ }
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__s390__");
+ Builder.defineMacro("__s390x__");
+ Builder.defineMacro("__zarch__");
+ Builder.defineMacro("__LONG_DOUBLE_128__");
+ }
+ void getTargetBuiltins(const Builtin::Info *&Records,
+ unsigned &NumRecords) const override {
+ // FIXME: Implement.
+ Records = nullptr;
+ NumRecords = 0;
}
- bool SystemZTargetInfo::
- validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const {
- switch (*Name) {
- default:
- return false;
-
- case 'a': // Address register
- case 'd': // Data register (equivalent to 'r')
- case 'f': // Floating-point register
- Info.setAllowsRegister();
- return true;
-
- case 'I': // Unsigned 8-bit constant
- case 'J': // Unsigned 12-bit constant
- case 'K': // Signed 16-bit constant
- case 'L': // Signed 20-bit displacement (on all targets we support)
- case 'M': // 0x7fffffff
- return true;
-
- case 'Q': // Memory with base and unsigned 12-bit displacement
- case 'R': // Likewise, plus an index
- case 'S': // Memory with base and signed 20-bit displacement
- case 'T': // Likewise, plus an index
- Info.setAllowsMemory();
- return true;
- }
+ void getGCCRegNames(const char *const *&Names,
+ unsigned &NumNames) const override;
+ void getGCCRegAliases(const GCCRegAlias *&Aliases,
+ unsigned &NumAliases) const override {
+ // No aliases.
+ Aliases = nullptr;
+ NumAliases = 0;
}
+ bool validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &info) const override;
+ const char *getClobbers() const override {
+ // FIXME: Is this really right?
+ return "";
+ }
+ BuiltinVaListKind getBuiltinVaListKind() const override {
+ return TargetInfo::SystemZBuiltinVaList;
+ }
+ bool setCPU(const std::string &Name) override {
+ bool CPUKnown = llvm::StringSwitch<bool>(Name)
+ .Case("z10", true)
+ .Case("z196", true)
+ .Case("zEC12", true)
+ .Default(false);
+
+ // No need to store the CPU yet. There aren't any CPU-specific
+ // macros to define.
+ return CPUKnown;
+ }
+};
+
+const char *const SystemZTargetInfo::GCCRegNames[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
+ "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
+};
+
+void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
+ unsigned &NumNames) const {
+ Names = GCCRegNames;
+ NumNames = llvm::array_lengthof(GCCRegNames);
+}
+
+bool SystemZTargetInfo::
+validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &Info) const {
+ switch (*Name) {
+ default:
+ return false;
+
+ case 'a': // Address register
+ case 'd': // Data register (equivalent to 'r')
+ case 'f': // Floating-point register
+ Info.setAllowsRegister();
+ return true;
+
+ case 'I': // Unsigned 8-bit constant
+ case 'J': // Unsigned 12-bit constant
+ case 'K': // Signed 16-bit constant
+ case 'L': // Signed 20-bit displacement (on all targets we support)
+ case 'M': // 0x7fffffff
+ return true;
+
+ case 'Q': // Memory with base and unsigned 12-bit displacement
+ case 'R': // Likewise, plus an index
+ case 'S': // Memory with base and signed 20-bit displacement
+ case 'T': // Likewise, plus an index
+ Info.setAllowsMemory();
+ return true;
+ }
+}
}
namespace {
@@ -5172,7 +5075,7 @@
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
// FIXME: Implement.
- Records = 0;
+ Records = nullptr;
NumRecords = 0;
}
bool hasFeature(StringRef Feature) const override {
@@ -5183,7 +5086,7 @@
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
// No aliases.
- Aliases = 0;
+ Aliases = nullptr;
NumAliases = 0;
}
bool validateAsmConstraint(const char *&Name,
@@ -5508,9 +5411,6 @@
std::find(Features.begin(), Features.end(), "+soft-float");
if (it != Features.end())
Features.erase(it);
- it = std::find(Features.begin(), Features.end(), "+nan2008");
- if (it != Features.end())
- Features.erase(it);
setDescriptionString();
@@ -5644,32 +5544,44 @@
public:
Mips64TargetInfoBase(const llvm::Triple &Triple)
: MipsTargetInfoBase(Triple, "n64", "mips64r2") {
- LongWidth = LongAlign = 64;
- PointerWidth = PointerAlign = 64;
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad;
if (getTriple().getOS() == llvm::Triple::FreeBSD) {
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
}
+ setN64ABITypes();
SuitableAlign = 128;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
}
+
+ void setN64ABITypes() {
+ LongWidth = LongAlign = 64;
+ PointerWidth = PointerAlign = 64;
+ SizeType = UnsignedLong;
+ PtrDiffType = SignedLong;
+ }
+
+ void setN32ABITypes() {
+ LongWidth = LongAlign = 32;
+ PointerWidth = PointerAlign = 32;
+ SizeType = UnsignedInt;
+ PtrDiffType = SignedInt;
+ }
+
bool setABI(const std::string &Name) override {
if (Name == "n32") {
- LongWidth = LongAlign = 32;
- PointerWidth = PointerAlign = 32;
+ setN32ABITypes();
ABI = Name;
return true;
- } else if (Name == "n64") {
- ABI = Name;
- return true;
- } else if (Name == "64") {
+ } else if (Name == "n64" || Name == "64") {
+ setN64ABITypes();
ABI = "n64";
return true;
- } else
- return false;
+ }
+ return false;
}
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
MipsTargetInfoBase::getTargetDefines(Opts, Builder);
@@ -5729,6 +5641,8 @@
Aliases = GCCRegAliases;
NumAliases = llvm::array_lengthof(GCCRegAliases);
}
+
+ bool hasInt128Type() const override { return true; }
};
class Mips64EBTargetInfo : public Mips64TargetInfoBase {
@@ -5830,13 +5744,13 @@
void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
unsigned &NumNames) const {
- Names = NULL;
+ Names = nullptr;
NumNames = 0;
}
void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const {
- Aliases = NULL;
+ Aliases = nullptr;
NumAliases = 0;
}
} // end anonymous namespace.
@@ -5970,7 +5884,7 @@
}
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
- Aliases = NULL;
+ Aliases = nullptr;
NumAliases = 0;
}
bool validateAsmConstraint(const char *&Name,
@@ -6001,17 +5915,29 @@
switch (Triple.getArch()) {
default:
- return NULL;
+ return nullptr;
case llvm::Triple::arm64:
if (Triple.isOSDarwin())
- return new DarwinARM64TargetInfo(Triple);
+ return new DarwinAArch64TargetInfo(Triple);
switch (os) {
case llvm::Triple::Linux:
- return new LinuxTargetInfo<ARM64TargetInfo>(Triple);
+ return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
+ case llvm::Triple::NetBSD:
+ return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
default:
- return new ARM64TargetInfo(Triple);
+ return new AArch64leTargetInfo(Triple);
+ }
+
+ case llvm::Triple::arm64_be:
+ switch (os) {
+ case llvm::Triple::Linux:
+ return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
+ case llvm::Triple::NetBSD:
+ return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
+ default:
+ return new AArch64beTargetInfo(Triple);
}
case llvm::Triple::xcore:
@@ -6060,6 +5986,15 @@
return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
case llvm::Triple::NaCl:
return new NaClTargetInfo<ARMleTargetInfo>(Triple);
+ case llvm::Triple::Win32:
+ switch (Triple.getEnvironment()) {
+ default:
+ return new ARMleTargetInfo(Triple);
+ case llvm::Triple::Itanium:
+ return new ItaniumWindowsARMleTargetInfo(Triple);
+ case llvm::Triple::MSVC:
+ return new MicrosoftARMleTargetInfo(Triple);
+ }
default:
return new ARMleTargetInfo(Triple);
}
@@ -6158,7 +6093,7 @@
case llvm::Triple::NaCl:
return new NaClTargetInfo<PNaClTargetInfo>(Triple);
default:
- return NULL;
+ return nullptr;
}
case llvm::Triple::ppc:
@@ -6292,7 +6227,7 @@
case llvm::Triple::GNU:
return new MinGWX86_32TargetInfo(Triple);
case llvm::Triple::MSVC:
- return new VisualStudioWindowsX86_32TargetInfo(Triple);
+ return new MicrosoftX86_32TargetInfo(Triple);
}
}
case llvm::Triple::Haiku:
@@ -6335,7 +6270,7 @@
case llvm::Triple::GNU:
return new MinGWX86_64TargetInfo(Triple);
case llvm::Triple::MSVC:
- return new VisualStudioWindowsX86_64TargetInfo(Triple);
+ return new MicrosoftX86_64TargetInfo(Triple);
}
}
case llvm::Triple::NaCl:
@@ -6347,13 +6282,13 @@
case llvm::Triple::spir: {
if (Triple.getOS() != llvm::Triple::UnknownOS ||
Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
- return NULL;
+ return nullptr;
return new SPIR32TargetInfo(Triple);
}
case llvm::Triple::spir64: {
if (Triple.getOS() != llvm::Triple::UnknownOS ||
Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
- return NULL;
+ return nullptr;
return new SPIR64TargetInfo(Triple);
}
}
@@ -6369,26 +6304,26 @@
std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
if (!Target) {
Diags.Report(diag::err_target_unknown_triple) << Triple.str();
- return 0;
+ return nullptr;
}
Target->setTargetOpts(Opts);
// Set the target CPU if specified.
if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
- return 0;
+ return nullptr;
}
// Set the target ABI if specified.
if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
- return 0;
+ return nullptr;
}
// Set the fp math unit.
if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
- return 0;
+ return nullptr;
}
// Compute the default target features, we need the target to handle this
@@ -6414,7 +6349,7 @@
ie = Features.end(); it != ie; ++it)
Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
if (!Target->handleTargetFeatures(Opts->Features, Diags))
- return 0;
+ return nullptr;
return Target.release();
}