commit b83f5a77335ca8a5b41ba4e17aa8d4bb6248c1e4
author Ben Langmuir <ben.langmuir@intel.com> Thu Sep 19 13:22:04 2013 +0000
committer Ben Langmuir <ben.langmuir@intel.com> Thu Sep 19 13:22:04 2013 +0000
tree 701348e4e3a8017efbed2dfe03d30733462610f6
parent d2cf0842a4690fe716762525496c864ae25c4bf2

Add C intrinsics for Intel SHA Extensions

Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@190999 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Basic/Targets.cpp

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 3e54c12..2f4aeb9 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1589,6 +1589,7 @@
   bool HasFMA;
   bool HasF16C;
   bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
+  bool HasSHA;
 
   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
   ///
@@ -1749,7 +1750,7 @@
         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasFMA(false),
         HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
-        HasAVX512PF(false), CPU(CK_Generic), FPMath(FP_Default) {
+        HasAVX512PF(false), HasSHA(false), CPU(CK_Generic), FPMath(FP_Default) {
     BigEndian = false;
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
   }
@@ -2166,7 +2167,8 @@
   case SSE1:
     Features["sse"] = false;
   case SSE2:
-    Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
+    Features["sse2"] = Features["pclmul"] = Features["aes"] =
+      Features["sha"] = false;
   case SSE3:
     Features["sse3"] = false;
     setXOPLevel(Features, NoXOP, false);
@@ -2297,6 +2299,9 @@
   } else if (Name == "f16c") {
     if (Enabled)
       setSSELevel(Features, AVX, Enabled);
+  } else if (Name == "sha") {
+    if (Enabled)
+      setSSELevel(Features, SSE2, Enabled);
   }
 }
 
@@ -2387,6 +2392,11 @@
       continue;
     }
 
+    if (Feature == "sha") {
+      HasSHA = true;
+      continue;
+    }
+
     assert(Features[i][0] == '+' && "Invalid target feature!");
     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
       .Case("avx512f", AVX512F)
@@ -2656,6 +2666,9 @@
   if (HasAVX512PF)
     Builder.defineMacro("__AVX512PF__");
 
+  if (HasSHA)
+    Builder.defineMacro("__SHA__");
+
   // Each case falls through to the previous one here.
   switch (SSELevel) {
   case AVX512F:
@@ -2746,6 +2759,7 @@
       .Case("rtm", HasRTM)
       .Case("prfchw", HasPRFCHW)
       .Case("rdseed", HasRDSEED)
+      .Case("sha", HasSHA)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)