change TargetInfo::ConstraintInfo to be a struct that contains
the enum along with some other data.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@70114 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Basic/TargetInfo.cpp b/lib/Basic/TargetInfo.cpp
index b66e26f..cee13ea 100644
--- a/lib/Basic/TargetInfo.cpp
+++ b/lib/Basic/TargetInfo.cpp
@@ -164,24 +164,19 @@
}
bool TargetInfo::validateOutputConstraint(const char *Name,
- ConstraintInfo &info) const
-{
- info = CI_None;
-
+ ConstraintInfo &Info) const {
// An output constraint must start with '=' or '+'
if (*Name != '=' && *Name != '+')
return false;
if (*Name == '+')
- info = CI_ReadWrite;
- else
- info = CI_None;
+ Info.setIsReadWrite();
Name++;
while (*Name) {
switch (*Name) {
default:
- if (!validateAsmConstraint(Name, info)) {
+ if (!validateAsmConstraint(Name, Info)) {
// FIXME: We temporarily return false
// so we can add more constraints as we hit it.
// Eventually, an unknown constraint should just be treated as 'g'.
@@ -190,14 +185,15 @@
case '&': // early clobber.
break;
case 'r': // general register.
- info = (ConstraintInfo)(info|CI_AllowsRegister);
+ Info.setAllowsRegister();
break;
case 'm': // memory operand.
- info = (ConstraintInfo)(info|CI_AllowsMemory);
+ Info.setAllowsMemory();
break;
case 'g': // general register, memory operand or immediate integer.
case 'X': // any operand.
- info = (ConstraintInfo)(info|CI_AllowsMemory|CI_AllowsRegister);
+ Info.setAllowsRegister();
+ Info.setAllowsMemory();
break;
}
@@ -210,10 +206,8 @@
bool TargetInfo::resolveSymbolicName(const char *&Name,
const std::string *OutputNamesBegin,
const std::string *OutputNamesEnd,
- unsigned &Index) const
-{
+ unsigned &Index) const {
assert(*Name == '[' && "Symbolic name did not start with '['");
-
Name++;
const char *Start = Name;
while (*Name && *Name != ']')
@@ -240,10 +234,8 @@
bool TargetInfo::validateInputConstraint(const char *Name,
const std::string *OutputNamesBegin,
const std::string *OutputNamesEnd,
- ConstraintInfo* OutputConstraints,
- ConstraintInfo &info) const {
- info = CI_None;
-
+ ConstraintInfo *OutputConstraints,
+ ConstraintInfo &Info) const {
while (*Name) {
switch (*Name) {
default:
@@ -258,8 +250,9 @@
// The constraint should have the same info as the respective
// output constraint.
- info = (ConstraintInfo)(info|OutputConstraints[i]);
- } else if (!validateAsmConstraint(Name, info)) {
+ Info = OutputConstraints[i];
+ Info.setTiedOperand(i);
+ } else if (!validateAsmConstraint(Name, Info)) {
// FIXME: This error return is in place temporarily so we can
// add more constraints as we hit it. Eventually, an unknown
// constraint should just be treated as 'g'.
@@ -281,14 +274,15 @@
case 'n': // immediate integer with a known value.
break;
case 'r': // general register.
- info = (ConstraintInfo)(info|CI_AllowsRegister);
+ Info.setAllowsRegister();
break;
case 'm': // memory operand.
- info = (ConstraintInfo)(info|CI_AllowsMemory);
+ Info.setAllowsMemory();
break;
case 'g': // general register, memory operand or immediate integer.
case 'X': // any operand.
- info = (ConstraintInfo)(info|CI_AllowsMemory|CI_AllowsRegister);
+ Info.setAllowsRegister();
+ Info.setAllowsMemory();
break;
}
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index cb74001..98f6dc1 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -280,14 +280,14 @@
virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const;
virtual bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const {
+ TargetInfo::ConstraintInfo &Info) const {
switch (*Name) {
default: return false;
case 'O': // Zero
return true;
case 'b': // Base register
case 'f': // Floating point register
- info = (TargetInfo::ConstraintInfo)(info|TargetInfo::CI_AllowsRegister);
+ Info.setAllowsRegister();
return true;
}
}
@@ -638,7 +638,7 @@
bool
X86TargetInfo::validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const {
+ TargetInfo::ConstraintInfo &Info) const {
switch (*Name) {
default: return false;
case 'a': // eax.
@@ -660,7 +660,7 @@
// x86_64 instructions.
case 'N': // unsigned 8-bit integer constant for use with in and out
// instructions.
- info = (TargetInfo::ConstraintInfo)(info|TargetInfo::CI_AllowsRegister);
+ Info.setAllowsRegister();
return true;
}
}
@@ -997,7 +997,7 @@
NumAliases = 0;
}
virtual bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const {
+ TargetInfo::ConstraintInfo &Info) const {
// FIXME: Check if this is complete
switch (*Name) {
default:
@@ -1005,7 +1005,7 @@
case 'h': // r8-r15
case 'w': // VFP Floating point register single precision
case 'P': // VFP Floating point register double precision
- info = (TargetInfo::ConstraintInfo)(info|TargetInfo::CI_AllowsRegister);
+ Info.setAllowsRegister();
return true;
}
return false;