Update Clang for rebase to r212749.
This also fixes a small issue with arm_neon.h not being generated always.
Includes a cherry-pick of:
r213450 - fixes mac-specific header issue
r213126 - removes a default -Bsymbolic on Android
Change-Id: I2a790a0f5d3b2aab11de596fc3a74e7cbc99081d
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 9343542..c88fed1 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -572,7 +572,7 @@
void getVisualStudioDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
if (Opts.CPlusPlus) {
- if (Opts.RTTI)
+ if (Opts.RTTIData)
Builder.defineMacro("_CPPRTTI");
if (Opts.Exceptions)
@@ -587,8 +587,12 @@
if (Opts.POSIXThreads)
Builder.defineMacro("_MT");
- if (Opts.MSCVersion != 0)
- Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
+ if (Opts.MSCVersion != 0) {
+ Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion / 100000));
+ Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCVersion));
+ // FIXME We cannot encode the revision information into 32-bits
+ Builder.defineMacro("_MSC_BUILD", Twine(1));
+ }
if (Opts.MicrosoftExt) {
Builder.defineMacro("_MSC_EXTENSIONS");
@@ -702,8 +706,9 @@
ArchDefinePwr6 = 1 << 9,
ArchDefinePwr6x = 1 << 10,
ArchDefinePwr7 = 1 << 11,
- ArchDefineA2 = 1 << 12,
- ArchDefineA2q = 1 << 13
+ ArchDefinePwr8 = 1 << 12,
+ ArchDefineA2 = 1 << 13,
+ ArchDefineA2q = 1 << 14
} ArchDefineTypes;
// Note: GCC recognizes the following additional cpus:
@@ -750,6 +755,8 @@
.Case("pwr6x", true)
.Case("power7", true)
.Case("pwr7", true)
+ .Case("power8", true)
+ .Case("pwr8", true)
.Case("powerpc", true)
.Case("ppc", true)
.Case("powerpc64", true)
@@ -1012,7 +1019,10 @@
| ArchDefinePpcsq)
.Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
| ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
- | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
+ | ArchDefinePpcgr | ArchDefinePpcsq)
+ .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
+ | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
+ | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
.Case("power3", ArchDefinePpcgr)
.Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
.Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
@@ -1026,7 +1036,10 @@
| ArchDefinePpcsq)
.Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
| ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
- | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
+ | ArchDefinePpcgr | ArchDefinePpcsq)
+ .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
+ | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
+ | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
.Default(ArchDefineNone);
if (defs & ArchDefineName)
@@ -1053,6 +1066,8 @@
Builder.defineMacro("_ARCH_PWR6X");
if (defs & ArchDefinePwr7)
Builder.defineMacro("_ARCH_PWR7");
+ if (defs & ArchDefinePwr8)
+ Builder.defineMacro("_ARCH_PWR8");
if (defs & ArchDefineA2)
Builder.defineMacro("_ARCH_A2");
if (defs & ArchDefineA2q) {
@@ -1101,6 +1116,7 @@
.Case("g5", true)
.Case("pwr6", true)
.Case("pwr7", true)
+ .Case("pwr8", true)
.Case("ppc64", true)
.Case("ppc64le", true)
.Default(false);
@@ -1454,6 +1470,8 @@
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
class R600TargetInfo : public TargetInfo {
+ static const Builtin::Info BuiltinInfo[];
+
/// \brief The GPU profiles supported by the R600 target.
enum GPUKind {
GK_NONE,
@@ -1500,11 +1518,10 @@
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
- Records = nullptr;
- NumRecords = 0;
+ Records = BuiltinInfo;
+ NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
}
-
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__R600__");
@@ -1580,6 +1597,12 @@
}
};
+const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS) \
+ { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
+#include "clang/Basic/BuiltinsR600.def"
+};
+
} // end anonymous namespace
namespace {
@@ -1863,7 +1886,7 @@
bool hasFeature(StringRef Feature) const override;
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override;
- const char* getABI() const override {
+ StringRef getABI() const override {
if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
return "avx";
else if (getTriple().getArch() == llvm::Triple::x86 &&
@@ -3080,9 +3103,6 @@
WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
}
};
-} // end anonymous namespace
-
-namespace {
// x86-32 Windows Visual Studio target
class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
@@ -3252,18 +3272,24 @@
class X86_64TargetInfo : public X86TargetInfo {
public:
X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
- LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
+ const bool IsX32{getTriple().getEnvironment() == llvm::Triple::GNUX32};
+ LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
LongDoubleWidth = 128;
LongDoubleAlign = 128;
LargeArrayMinWidth = 128;
LargeArrayAlign = 128;
SuitableAlign = 128;
- IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
- Int64Type = SignedLong;
+ SizeType = IsX32 ? UnsignedInt : UnsignedLong;
+ PtrDiffType = IsX32 ? SignedInt : SignedLong;
+ IntPtrType = IsX32 ? SignedInt : SignedLong;
+ IntMaxType = IsX32 ? SignedLongLong : SignedLong;
+ UIntMaxType = IsX32 ? UnsignedLongLong : UnsignedLong;
+ Int64Type = IsX32 ? SignedLongLong : SignedLong;
RegParmMax = 6;
- DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
+ DescriptionString = (IsX32)
+ ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
+ : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128";
// Use fpret only for long double.
RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
@@ -3272,10 +3298,8 @@
ComplexLongDoubleUsesFP2Ret = true;
// x86-64 has atomics up to 16 bytes.
- // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
- // on CPUs with cmpxchg16b
MaxAtomicPromoteWidth = 128;
- MaxAtomicInlineWidth = 64;
+ MaxAtomicInlineWidth = 128;
}
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::X86_64ABIBuiltinVaList;
@@ -3457,27 +3481,14 @@
static const Builtin::Info BuiltinInfo[];
static bool shouldUseInlineAtomic(const llvm::Triple &T) {
- if (T.isOSWindows())
- return true;
-
- // On linux, binaries targeting old cpus call functions in libgcc to
- // perform atomic operations. The implementation in libgcc then calls into
- // the kernel which on armv6 and newer uses ldrex and strex. The net result
- // is that if we assume the kernel is at least as recent as the hardware,
- // it is safe to use atomic instructions on armv6 and newer.
- if (!T.isOSLinux() &&
- T.getOS() != llvm::Triple::FreeBSD &&
- T.getOS() != llvm::Triple::NetBSD &&
- T.getOS() != llvm::Triple::Bitrig)
- return false;
StringRef ArchName = T.getArchName();
if (T.getArch() == llvm::Triple::arm ||
T.getArch() == llvm::Triple::armeb) {
StringRef VersionStr;
if (ArchName.startswith("armv"))
- VersionStr = ArchName.substr(4);
+ VersionStr = ArchName.substr(4, 1);
else if (ArchName.startswith("armebv"))
- VersionStr = ArchName.substr(6);
+ VersionStr = ArchName.substr(6, 1);
else
return false;
unsigned Version;
@@ -3489,9 +3500,9 @@
T.getArch() == llvm::Triple::thumbeb);
StringRef VersionStr;
if (ArchName.startswith("thumbv"))
- VersionStr = ArchName.substr(6);
+ VersionStr = ArchName.substr(6, 1);
else if (ArchName.startswith("thumbebv"))
- VersionStr = ArchName.substr(8);
+ VersionStr = ArchName.substr(8, 1);
else
return false;
unsigned Version;
@@ -3663,7 +3674,7 @@
// zero length bitfield.
UseZeroLengthBitfieldAlignment = true;
}
- const char *getABI() const override { return ABI.c_str(); }
+ StringRef getABI() const override { return ABI; }
bool setABI(const std::string &Name) override {
ABI = Name;
@@ -3819,7 +3830,8 @@
.Cases("cortex-r4", "cortex-r5", "7R")
.Case("swift", "7S")
.Case("cyclone", "8A")
- .Cases("cortex-m3", "cortex-m4", "7M")
+ .Case("cortex-m3", "7M")
+ .Case("cortex-m4", "7EM")
.Case("cortex-m0", "6M")
.Cases("cortex-a53", "cortex-a57", "8A")
.Default(nullptr);
@@ -3837,10 +3849,29 @@
if (!getCPUDefineSuffix(Name))
return false;
+ // Cortex M does not support 8 byte atomics, while general Thumb2 does.
+ StringRef Profile = getCPUProfile(Name);
+ if (Profile == "M" && MaxAtomicInlineWidth) {
+ MaxAtomicPromoteWidth = 32;
+ MaxAtomicInlineWidth = 32;
+ }
+
CPU = Name;
return true;
}
bool setFPMath(StringRef Name) override;
+ bool supportsThumb(StringRef ArchName, StringRef CPUArch,
+ unsigned CPUArchVer) const {
+ return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
+ (CPUArch.find('M') != StringRef::npos);
+ }
+ bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
+ unsigned CPUArchVer) const {
+ // We check both CPUArchVer and ArchName because when only triple is
+ // specified, the default CPU is arm1136j-s.
+ return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
+ ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
+ }
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
// Target identification.
@@ -3856,10 +3887,40 @@
llvm_unreachable("Invalid char for architecture version number");
}
Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
- Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+ // ACLE 6.4.1 ARM/Thumb instruction set architecture
StringRef CPUProfile = getCPUProfile(CPU);
+ StringRef ArchName = getTriple().getArchName();
+
+ // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
+ Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+ // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
+ // is not defined for the M-profile.
+ // NOTE that the deffault profile is assumed to be 'A'
+ if (CPUProfile.empty() || CPUProfile != "M")
+ Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
+
+ // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
+ // Thumb ISA (including v6-M). It is set to 2 if the core supports the
+ // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
+ if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
+ Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
+ else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
+ Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
+
+ // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
+ // instruction set such as ARM or Thumb.
+ Builder.defineMacro("__ARM_32BIT_STATE", "1");
+
+ // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
+
+ // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
if (!CPUProfile.empty())
- Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
+ Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
+
+ // ACLE predefines.
+ Builder.defineMacro("__ARM_ACLE", "200");
// Subtarget options.
@@ -3889,11 +3950,7 @@
if (IsThumb) {
Builder.defineMacro("__THUMBEL__");
Builder.defineMacro("__thumb__");
- // We check both CPUArchVer and ArchName because when only triple is
- // specified, the default CPU is arm1136j-s.
- StringRef ArchName = getTriple().getArchName();
- if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") ||
- ArchName.endswith("v7") || ArchName.endswith("v8"))
+ if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
Builder.defineMacro("__thumb2__");
}
if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
@@ -4115,6 +4172,7 @@
#include "clang/Basic/BuiltinsNEON.def"
#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
+#define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
ALL_LANGUAGES },
#include "clang/Basic/BuiltinsARM.def"
@@ -4174,6 +4232,9 @@
// 31: VFPv3 40: VFPv4
Builder.defineMacro("_M_ARM_FP", "31");
}
+ BuiltinVaListKind getBuiltinVaListKind() const override {
+ return TargetInfo::CharPtrBuiltinVaList;
+ }
};
// Windows ARM + Itanium C++ ABI Target
@@ -4245,6 +4306,7 @@
NeonMode
};
+ std::string CPU;
unsigned FPU;
unsigned CRC;
unsigned Crypto;
@@ -4289,7 +4351,7 @@
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
- virtual const char *getABI() const { return ABI.c_str(); }
+ StringRef getABI() const override { return ABI; }
virtual bool setABI(const std::string &Name) {
if (Name != "aapcs" && Name != "darwinpcs")
return false;
@@ -4304,6 +4366,8 @@
.Cases("cortex-a53", "cortex-a57", true)
.Case("cyclone", true)
.Default(false);
+ if (CPUKnown)
+ CPU = Name;
return CPUKnown;
}
@@ -4375,6 +4439,23 @@
(Feature == "neon" && FPU == NeonMode);
}
+ void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
+
+ if (CPU == "cyclone") {
+ Features["fp-armv8"] = true;
+ Features["neon"] = true;
+ Features["crypto"] = true;
+ Features["crc"] = true;
+ Features["zcm"] = true;
+ Features["zcz"] = true;
+ } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
+ Features["fp-armv8"] = true;
+ Features["neon"] = true;
+ Features["crypto"] = true;
+ Features["crc"] = true;
+ }
+}
+
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
FPU = FPUMode;
@@ -5224,12 +5305,35 @@
IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
- const char *getABI() const override { return ABI.c_str(); }
- bool setABI(const std::string &Name) override = 0;
- bool setCPU(const std::string &Name) override {
- CPU = Name;
- return true;
+ bool isNaN2008Default() const {
+ return CPU == "mips32r6" || CPU == "mips64r6";
}
+
+ bool isFP64Default() const {
+ return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
+ }
+
+ StringRef getABI() const override { return ABI; }
+ bool setCPU(const std::string &Name) override {
+ bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
+ getTriple().getArch() == llvm::Triple::mipsel;
+ CPU = Name;
+ return llvm::StringSwitch<bool>(Name)
+ .Case("mips1", IsMips32)
+ .Case("mips2", IsMips32)
+ .Case("mips3", true)
+ .Case("mips4", true)
+ .Case("mips5", true)
+ .Case("mips32", IsMips32)
+ .Case("mips32r2", IsMips32)
+ .Case("mips32r6", IsMips32)
+ .Case("mips64", true)
+ .Case("mips64r2", true)
+ .Case("mips64r6", true)
+ .Case("octeon", true)
+ .Default(false);
+ }
+ const std::string& getCPU() const { return CPU; }
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
// The backend enables certain ABI's by default according to the
// architecture.
@@ -5239,7 +5343,10 @@
Features["n64"] = false;
Features[ABI] = true;
- Features[CPU] = true;
+ if (CPU == "octeon")
+ Features["mips64r2"] = Features["cnmips"] = true;
+ else
+ Features[CPU] = true;
}
void getTargetDefines(const LangOptions &Opts,
@@ -5376,11 +5483,11 @@
DiagnosticsEngine &Diags) override {
IsMips16 = false;
IsMicromips = false;
- IsNan2008 = false;
+ IsNan2008 = isNaN2008Default();
IsSingleFloat = false;
FloatABI = HardFloat;
DspRev = NoDSP;
- HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64";
+ HasFP64 = isFP64Default();
for (std::vector<std::string>::iterator it = Features.begin(),
ie = Features.end(); it != ie; ++it) {
@@ -5404,6 +5511,8 @@
HasFP64 = false;
else if (*it == "+nan2008")
IsNan2008 = true;
+ else if (*it == "-nan2008")
+ IsNan2008 = false;
}
// Remove front-end specific options.
@@ -5422,6 +5531,8 @@
if (RegNo == 1) return 5;
return -1;
}
+
+ bool isCLZForZeroUndef() const override { return false; }
};
const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
@@ -5440,20 +5551,24 @@
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
}
bool setABI(const std::string &Name) override {
- if ((Name == "o32") || (Name == "eabi")) {
+ if (Name == "o32" || Name == "eabi") {
ABI = Name;
return true;
- } else if (Name == "32") {
- ABI = "o32";
- return true;
- } else
- return false;
+ }
+ return false;
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
MipsTargetInfoBase::getTargetDefines(Opts, Builder);
Builder.defineMacro("__mips", "32");
+ Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
+
+ const std::string& CPUStr = getCPU();
+ if (CPUStr == "mips32")
+ Builder.defineMacro("__mips_isa_rev", "1");
+ else if (CPUStr == "mips32r2")
+ Builder.defineMacro("__mips_isa_rev", "2");
if (ABI == "o32") {
Builder.defineMacro("__mips_o32");
@@ -5574,9 +5689,10 @@
setN32ABITypes();
ABI = Name;
return true;
- } else if (Name == "n64" || Name == "64") {
+ }
+ if (Name == "n64") {
setN64ABITypes();
- ABI = "n64";
+ ABI = Name;
return true;
}
return false;
@@ -5589,6 +5705,13 @@
Builder.defineMacro("__mips", "64");
Builder.defineMacro("__mips64");
Builder.defineMacro("__mips64__");
+ Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
+
+ const std::string& CPUStr = getCPU();
+ if (CPUStr == "mips64")
+ Builder.defineMacro("__mips_isa_rev", "1");
+ else if (CPUStr == "mips64r2")
+ Builder.defineMacro("__mips_isa_rev", "2");
if (ABI == "n32") {
Builder.defineMacro("__mips_n32");
@@ -5917,6 +6040,13 @@
default:
return nullptr;
+ case llvm::Triple::xcore:
+ return new XCoreTargetInfo(Triple);
+
+ case llvm::Triple::hexagon:
+ return new HexagonTargetInfo(Triple);
+
+ case llvm::Triple::aarch64:
case llvm::Triple::arm64:
if (Triple.isOSDarwin())
return new DarwinAArch64TargetInfo(Triple);
@@ -5930,33 +6060,8 @@
return new AArch64leTargetInfo(Triple);
}
- case llvm::Triple::arm64_be:
- switch (os) {
- case llvm::Triple::Linux:
- return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
- case llvm::Triple::NetBSD:
- return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
- default:
- return new AArch64beTargetInfo(Triple);
- }
-
- case llvm::Triple::xcore:
- return new XCoreTargetInfo(Triple);
-
- case llvm::Triple::hexagon:
- return new HexagonTargetInfo(Triple);
-
- case llvm::Triple::aarch64:
- switch (os) {
- case llvm::Triple::Linux:
- return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
- case llvm::Triple::NetBSD:
- return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
- default:
- return new AArch64leTargetInfo(Triple);
- }
-
case llvm::Triple::aarch64_be:
+ case llvm::Triple::arm64_be:
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
@@ -6226,6 +6331,7 @@
return new CygwinX86_32TargetInfo(Triple);
case llvm::Triple::GNU:
return new MinGWX86_32TargetInfo(Triple);
+ case llvm::Triple::Itanium:
case llvm::Triple::MSVC:
return new MicrosoftX86_32TargetInfo(Triple);
}
@@ -6296,8 +6402,9 @@
/// CreateTargetInfo - Return the target info object for the specified target
/// triple.
-TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
- TargetOptions *Opts) {
+TargetInfo *
+TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
+ const std::shared_ptr<TargetOptions> &Opts) {
llvm::Triple Triple(Opts->Triple);
// Construct the target
@@ -6306,7 +6413,7 @@
Diags.Report(diag::err_target_unknown_triple) << Triple.str();
return nullptr;
}
- Target->setTargetOpts(Opts);
+ Target->TargetOpts = Opts;
// Set the target CPU if specified.
if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {