make: Add CheckCommandLineOverrides to my little Makefile library, a routine for
validating the variables set on the make command line.
git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@116517 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/make/util.mk b/make/util.mk
index 57ff4da..0687755 100644
--- a/make/util.mk
+++ b/make/util.mk
@@ -88,6 +88,17 @@
$(if $(call streq,$($(1)),$(2)),,\
$(error Assertion failed: $(1): $(value $(1)) - $($(1)) != $(2)))
+# Function: CheckCommandLineOverrides list
+#
+# Check that all command line variables are in the given list. This routine is
+# useful for validating that users aren't trying to override something which
+# will not work.
+CheckCommandLineOverrides = \
+ $(foreach arg,$(MAKEOVERRIDES),\
+ $(call Set,varname,$(firstword $(subst =, ,$(arg)))) \
+ $(if $(call contains,$(1),$(varname)),,\
+ $(error "Invalid command line override: $(1) $(varname) (not supported)")))
+
###
# Clean up make behavior