Guillaume Chatelet | 3cc8f31 | 2020-10-12 08:55:20 +0000 | [diff] [blame] | 1 | // Copyright 2017 Google LLC |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
Guillaume Chatelet | 8e58ef0 | 2018-02-01 10:38:48 +0100 | [diff] [blame] | 15 | #ifndef CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ |
| 16 | #define CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 17 | |
Guillaume Chatelet | 918553a | 2019-01-17 15:28:04 +0100 | [diff] [blame] | 18 | #include <stdint.h> // uint32_t |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 19 | |
Artem Alekseev | 653d581 | 2019-07-02 17:52:25 +0300 | [diff] [blame] | 20 | #include "cpu_features_cache_info.h" |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 21 | #include "cpu_features_macros.h" |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 22 | |
Guillaume Chatelet | e419573 | 2018-02-12 16:15:15 +0100 | [diff] [blame] | 23 | CPU_FEATURES_START_CPP_NAMESPACE |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 24 | |
| 25 | typedef struct { |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 26 | int swp : 1; // SWP instruction (atomic read-modify-write) |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 27 | int half : 1; // Half-word loads and stores |
| 28 | int thumb : 1; // Thumb (16-bit instruction set) |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 29 | int _26bit : 1; // "26 Bit" Model (Processor status register folded into |
| 30 | // program counter) |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 31 | int fastmult : 1; // 32x32->64-bit multiplication |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 32 | int fpa : 1; // Floating point accelerator |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 33 | int vfp : 1; // Vector Floating Point. |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 34 | int edsp : 1; // DSP extensions (the 'e' variant of the ARM9 CPUs, and all |
| 35 | // others above) |
| 36 | int java : 1; // Jazelle (Java bytecode accelerator) |
| 37 | int iwmmxt : 1; // Intel Wireless MMX Technology. |
| 38 | int crunch : 1; // MaverickCrunch coprocessor |
| 39 | int thumbee : 1; // ThumbEE |
| 40 | int neon : 1; // Advanced SIMD. |
| 41 | int vfpv3 : 1; // VFP version 3 |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 42 | int vfpv3d16 : 1; // VFP version 3 with 16 D-registers |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 43 | int tls : 1; // TLS register |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 44 | int vfpv4 : 1; // VFP version 4 with fast context switching |
| 45 | int idiva : 1; // SDIV and UDIV hardware division in ARM mode. |
| 46 | int idivt : 1; // SDIV and UDIV hardware division in Thumb mode. |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 47 | int vfpd32 : 1; // VFP with 32 D-registers |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 48 | int lpae : 1; // Large Physical Address Extension (>4GB physical memory on |
| 49 | // 32-bit architecture) |
| 50 | int evtstrm : 1; // kernel event stream using generic architected timer |
| 51 | int aes : 1; // Hardware-accelerated Advanced Encryption Standard. |
| 52 | int pmull : 1; // Polynomial multiply long. |
| 53 | int sha1 : 1; // Hardware-accelerated SHA1. |
| 54 | int sha2 : 1; // Hardware-accelerated SHA2-256. |
| 55 | int crc32 : 1; // Hardware-accelerated CRC-32. |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 56 | |
| 57 | // Make sure to update ArmFeaturesEnum below if you add a field here. |
| 58 | } ArmFeatures; |
| 59 | |
| 60 | typedef struct { |
| 61 | ArmFeatures features; |
| 62 | int implementer; |
| 63 | int architecture; |
| 64 | int variant; |
| 65 | int part; |
| 66 | int revision; |
| 67 | } ArmInfo; |
| 68 | |
| 69 | // TODO(user): Add macros to know which features are present at compile |
| 70 | // time. |
| 71 | |
| 72 | ArmInfo GetArmInfo(void); |
| 73 | |
Guillaume Chatelet | 918553a | 2019-01-17 15:28:04 +0100 | [diff] [blame] | 74 | // Compute CpuId from ArmInfo. |
| 75 | uint32_t GetArmCpuId(const ArmInfo* const info); |
| 76 | |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 77 | //////////////////////////////////////////////////////////////////////////////// |
| 78 | // Introspection functions |
| 79 | |
| 80 | typedef enum { |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 81 | ARM_SWP, |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 82 | ARM_HALF, |
| 83 | ARM_THUMB, |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 84 | ARM_26BIT, |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 85 | ARM_FASTMULT, |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 86 | ARM_FPA, |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 87 | ARM_VFP, |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 88 | ARM_EDSP, |
| 89 | ARM_JAVA, |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 90 | ARM_IWMMXT, |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 91 | ARM_CRUNCH, |
| 92 | ARM_THUMBEE, |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 93 | ARM_NEON, |
| 94 | ARM_VFPV3, |
| 95 | ARM_VFPV3D16, |
Dr.-Ing. Patrick Siegl | 6482bad | 2019-06-18 12:53:08 +0200 | [diff] [blame] | 96 | ARM_TLS, |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 97 | ARM_VFPV4, |
| 98 | ARM_IDIVA, |
| 99 | ARM_IDIVT, |
Dr.-Ing. Patrick Siegl | bfd109b | 2019-06-26 12:56:52 +0200 | [diff] [blame] | 100 | ARM_VFPD32, |
| 101 | ARM_LPAE, |
| 102 | ARM_EVTSTRM, |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 103 | ARM_AES, |
| 104 | ARM_PMULL, |
| 105 | ARM_SHA1, |
| 106 | ARM_SHA2, |
| 107 | ARM_CRC32, |
| 108 | ARM_LAST_, |
| 109 | } ArmFeaturesEnum; |
| 110 | |
| 111 | int GetArmFeaturesEnumValue(const ArmFeatures* features, ArmFeaturesEnum value); |
| 112 | |
| 113 | const char* GetArmFeaturesEnumName(ArmFeaturesEnum); |
| 114 | |
Guillaume Chatelet | e419573 | 2018-02-12 16:15:15 +0100 | [diff] [blame] | 115 | CPU_FEATURES_END_CPP_NAMESPACE |
Guillaume Chatelet | 439d371 | 2018-02-01 10:03:09 +0100 | [diff] [blame] | 116 | |
Guillaume Chatelet | 4155ee7 | 2019-01-18 13:38:22 +0100 | [diff] [blame] | 117 | #if !defined(CPU_FEATURES_ARCH_ARM) |
| 118 | #error "Including cpuinfo_arm.h from a non-arm target." |
| 119 | #endif |
| 120 | |
Guillaume Chatelet | 8e58ef0 | 2018-02-01 10:38:48 +0100 | [diff] [blame] | 121 | #endif // CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ |