diff --git a/jni/Android.mk b/jni/Android.mk
index 938ebe2..4374039 100644
--- a/jni/Android.mk
+++ b/jni/Android.mk
@@ -160,6 +160,13 @@
 include $(BUILD_EXECUTABLE)
 
 include $(CLEAR_VARS)
+LOCAL_MODULE := nexus6-test
+LOCAL_SRC_FILES := $(LOCAL_PATH)/test/nexus6.cc
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/test
+LOCAL_STATIC_LIBRARIES := cpuinfo_mock gtest
+include $(BUILD_EXECUTABLE)
+
+include $(CLEAR_VARS)
 LOCAL_MODULE := nexus9-test
 LOCAL_SRC_FILES := $(LOCAL_PATH)/test/nexus9.cc
 LOCAL_C_INCLUDES := $(LOCAL_PATH)/test
diff --git a/test/cpuinfo/nexus6.log b/test/cpuinfo/nexus6.log
new file mode 100644
index 0000000..4356050
--- /dev/null
+++ b/test/cpuinfo/nexus6.log
@@ -0,0 +1,46 @@
+processor	: 0
+model name	: ARMv7 Processor rev 1 (v7l)
+BogoMIPS	: 38.40
+Features	: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt 
+CPU implementer	: 0x51
+CPU architecture: 7
+CPU variant	: 0x3
+CPU part	: 0x06f
+CPU revision	: 1
+
+processor	: 1
+model name	: ARMv7 Processor rev 1 (v7l)
+BogoMIPS	: 38.40
+Features	: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt 
+CPU implementer	: 0x51
+CPU architecture: 7
+CPU variant	: 0x3
+CPU part	: 0x06f
+CPU revision	: 1
+
+processor	: 2
+model name	: ARMv7 Processor rev 1 (v7l)
+BogoMIPS	: 38.40
+Features	: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt 
+CPU implementer	: 0x51
+CPU architecture: 7
+CPU variant	: 0x3
+CPU part	: 0x06f
+CPU revision	: 1
+
+processor	: 3
+model name	: ARMv7 Processor rev 1 (v7l)
+BogoMIPS	: 38.40
+Features	: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt 
+CPU implementer	: 0x51
+CPU architecture: 7
+CPU variant	: 0x3
+CPU part	: 0x06f
+CPU revision	: 1
+
+Hardware	: Qualcomm APQ 8084 (Flattened Device Tree)
+Revision	: 83a0
+Serial		: 68123d0111000000
+Device		: shamu
+Radio		: 6
+MSM Hardware	: APQ8084 ES1.1
diff --git a/test/nexus6.cc b/test/nexus6.cc
new file mode 100644
index 0000000..692672a
--- /dev/null
+++ b/test/nexus6.cc
@@ -0,0 +1,318 @@
+#include <gtest/gtest.h>
+
+#include <cpuinfo.h>
+#include <cpuinfo-mock.h>
+
+
+TEST(PROCESSORS, count) {
+	ASSERT_EQ(4, cpuinfo_processors_count);
+}
+
+TEST(PROCESSORS, non_null) {
+	ASSERT_TRUE(cpuinfo_processors);
+}
+
+TEST(PROCESSORS, vendor_qualcomm) {
+	for (uint32_t i = 0; i < cpuinfo_processors_count; i++) {
+		ASSERT_EQ(cpuinfo_vendor_qualcomm, cpuinfo_processors[i].vendor);
+	}
+}
+
+TEST(PROCESSORS, uarch_krait) {
+	for (uint32_t i = 0; i < cpuinfo_processors_count; i++) {
+		ASSERT_EQ(cpuinfo_uarch_krait, cpuinfo_processors[i].uarch);
+	}
+}
+
+TEST(ISA, thumb) {
+	ASSERT_TRUE(cpuinfo_isa.thumb);
+}
+
+TEST(ISA, thumb2) {
+	ASSERT_TRUE(cpuinfo_isa.thumb2);
+}
+
+TEST(ISA, thumbee) {
+	ASSERT_FALSE(cpuinfo_isa.thumbee);
+}
+
+TEST(ISA, jazelle) {
+	ASSERT_FALSE(cpuinfo_isa.jazelle);
+}
+
+TEST(ISA, armv5e) {
+	ASSERT_TRUE(cpuinfo_isa.armv5e);
+}
+
+TEST(ISA, armv6) {
+	ASSERT_TRUE(cpuinfo_isa.armv6);
+}
+
+TEST(ISA, armv6k) {
+	ASSERT_TRUE(cpuinfo_isa.armv6k);
+}
+
+TEST(ISA, armv7) {
+	ASSERT_TRUE(cpuinfo_isa.armv7);
+}
+
+TEST(ISA, armv7mp) {
+	ASSERT_TRUE(cpuinfo_isa.armv7mp);
+}
+
+TEST(ISA, idiv) {
+	ASSERT_TRUE(cpuinfo_isa.idiv);
+}
+
+TEST(ISA, vfpv2) {
+	ASSERT_FALSE(cpuinfo_isa.vfpv2);
+}
+
+TEST(ISA, vfpv3) {
+	ASSERT_TRUE(cpuinfo_isa.vfpv3);
+}
+
+TEST(ISA, d32) {
+	ASSERT_TRUE(cpuinfo_isa.d32);
+}
+
+TEST(ISA, fp16) {
+	ASSERT_TRUE(cpuinfo_isa.fp16);
+}
+
+TEST(ISA, fma) {
+	ASSERT_TRUE(cpuinfo_isa.fma);
+}
+
+TEST(ISA, wmmx) {
+	ASSERT_FALSE(cpuinfo_isa.wmmx);
+}
+
+TEST(ISA, wmmx2) {
+	ASSERT_FALSE(cpuinfo_isa.wmmx2);
+}
+
+TEST(ISA, neon) {
+	ASSERT_TRUE(cpuinfo_isa.neon);
+}
+
+TEST(ISA, aes) {
+	ASSERT_FALSE(cpuinfo_isa.aes);
+}
+
+TEST(ISA, sha1) {
+	ASSERT_FALSE(cpuinfo_isa.sha1);
+}
+
+TEST(ISA, sha2) {
+	ASSERT_FALSE(cpuinfo_isa.sha2);
+}
+
+TEST(ISA, pmull) {
+	ASSERT_FALSE(cpuinfo_isa.pmull);
+}
+
+TEST(ISA, crc32) {
+	ASSERT_FALSE(cpuinfo_isa.crc32);
+}
+
+TEST(L1I, count) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	ASSERT_EQ(4, l1i.count);
+}
+
+TEST(L1I, non_null) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	ASSERT_TRUE(l1i.instances);
+}
+
+TEST(L1I, size) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(16 * 1024, l1i.instances[k].size);
+	}
+}
+
+TEST(L1I, associativity) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(4, l1i.instances[k].associativity);
+	}
+}
+
+TEST(L1I, sets) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(64, l1i.instances[k].sets);
+	}
+}
+
+TEST(L1I, partitions) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(1, l1i.instances[k].partitions);
+	}
+}
+
+TEST(L1I, line_size) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(64, l1i.instances[k].line_size);
+	}
+}
+
+TEST(L1I, flags) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(0, l1i.instances[k].flags);
+	}
+}
+
+TEST(L1I, processors) {
+	cpuinfo_caches l1i = cpuinfo_get_l1i_cache();
+	for (uint32_t k = 0; k < l1i.count; k++) {
+		ASSERT_EQ(k, l1i.instances[k].thread_start);
+		ASSERT_EQ(1, l1i.instances[k].thread_count);
+	}
+}
+
+TEST(L1D, count) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	ASSERT_EQ(4, l1d.count);
+}
+
+TEST(L1D, non_null) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	ASSERT_TRUE(l1d.instances);
+}
+
+TEST(L1D, size) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(16 * 1024, l1d.instances[k].size);
+	}
+}
+
+TEST(L1D, associativity) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(4, l1d.instances[k].associativity);
+	}
+}
+
+TEST(L1D, sets) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(64, l1d.instances[k].sets);
+	}
+}
+
+TEST(L1D, partitions) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(1, l1d.instances[k].partitions);
+	}
+}
+
+TEST(L1D, line_size) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(64, l1d.instances[k].line_size);
+	}
+}
+
+TEST(L1D, flags) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(0, l1d.instances[k].flags);
+	}
+}
+
+TEST(L1D, processors) {
+	cpuinfo_caches l1d = cpuinfo_get_l1d_cache();
+	for (uint32_t k = 0; k < l1d.count; k++) {
+		ASSERT_EQ(k, l1d.instances[k].thread_start);
+		ASSERT_EQ(1, l1d.instances[k].thread_count);
+	}
+}
+
+TEST(L2, count) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	ASSERT_EQ(1, l2.count);
+}
+
+TEST(L2, non_null) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	ASSERT_TRUE(l2.instances);
+}
+
+TEST(L2, size) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(2 * 1024 * 1024, l2.instances[k].size);
+	}
+}
+
+TEST(L2, associativity) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(8, l2.instances[k].associativity);
+	}
+}
+
+TEST(L2, sets) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(2048, l2.instances[k].sets);
+	}
+}
+
+TEST(L2, partitions) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(1, l2.instances[k].partitions);
+	}
+}
+
+TEST(L2, line_size) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(128, l2.instances[k].line_size);
+	}
+}
+
+TEST(L2, flags) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(0, l2.instances[k].flags);
+	}
+}
+
+TEST(L2, processors) {
+	cpuinfo_caches l2 = cpuinfo_get_l2_cache();
+	for (uint32_t k = 0; k < l2.count; k++) {
+		ASSERT_EQ(0, l2.instances[k].thread_start);
+		ASSERT_EQ(4, l2.instances[k].thread_count);
+	}
+}
+
+TEST(L3, none) {
+	cpuinfo_caches l3 = cpuinfo_get_l3_cache();
+	ASSERT_EQ(0, l3.count);
+	ASSERT_FALSE(l3.instances);
+}
+
+TEST(L4, none) {
+	cpuinfo_caches l4 = cpuinfo_get_l4_cache();
+	ASSERT_EQ(0, l4.count);
+	ASSERT_FALSE(l4.instances);
+}
+
+#include <nexus6.h>
+
+int main(int argc, char* argv[]) {
+	cpuinfo_mock_filesystem(filesystem);
+	cpuinfo_initialize();
+	::testing::InitGoogleTest(&argc, argv);
+	return RUN_ALL_TESTS();
+}
diff --git a/test/nexus6.h b/test/nexus6.h
new file mode 100644
index 0000000..c6acfe5
--- /dev/null
+++ b/test/nexus6.h
@@ -0,0 +1,340 @@
+struct cpuinfo_mock_file filesystem[] = {
+	{
+		.path = "/proc/cpuinfo",
+		.size = 1136,
+		.content =
+			"processor\t: 0\n"
+			"model name\t: ARMv7 Processor rev 1 (v7l)\n"
+			"BogoMIPS\t: 38.40\n"
+			"Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n"
+			"CPU implementer\t: 0x51\n"
+			"CPU architecture: 7\n"
+			"CPU variant\t: 0x3\n"
+			"CPU part\t: 0x06f\n"
+			"CPU revision\t: 1\n"
+			"\n"
+			"processor\t: 1\n"
+			"model name\t: ARMv7 Processor rev 1 (v7l)\n"
+			"BogoMIPS\t: 38.40\n"
+			"Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n"
+			"CPU implementer\t: 0x51\n"
+			"CPU architecture: 7\n"
+			"CPU variant\t: 0x3\n"
+			"CPU part\t: 0x06f\n"
+			"CPU revision\t: 1\n"
+			"\n"
+			"processor\t: 2\n"
+			"model name\t: ARMv7 Processor rev 1 (v7l)\n"
+			"BogoMIPS\t: 38.40\n"
+			"Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n"
+			"CPU implementer\t: 0x51\n"
+			"CPU architecture: 7\n"
+			"CPU variant\t: 0x3\n"
+			"CPU part\t: 0x06f\n"
+			"CPU revision\t: 1\n"
+			"\n"
+			"processor\t: 3\n"
+			"model name\t: ARMv7 Processor rev 1 (v7l)\n"
+			"BogoMIPS\t: 38.40\n"
+			"Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n"
+			"CPU implementer\t: 0x51\n"
+			"CPU architecture: 7\n"
+			"CPU variant\t: 0x3\n"
+			"CPU part\t: 0x06f\n"
+			"CPU revision\t: 1\n"
+			"\n"
+			"Hardware\t: Qualcomm APQ 8084 (Flattened Device Tree)\n"
+			"Revision\t: 83a0\n"
+			"Serial\t\t: 68123d0111000000\n"
+			"Device\t\t: shamu\n"
+			"Radio\t\t: 6\n"
+			"MSM Hardware\t: APQ8084 ES1.1\n",
+	},
+	{
+		.path = "/system/build.prop",
+		.size = 4715,
+		.content =
+			"\n"
+			"#\n"
+			"# PRODUCT_OEM_PROPERTIES\n"
+			"#\n"
+			"import /oem/oem.prop ro.config.ringtone\n"
+			"import /oem/oem.prop ro.config.notification_sound\n"
+			"import /oem/oem.prop ro.config.alarm_alert\n"
+			"import /oem/oem.prop ro.config.wallpaper\n"
+			"import /oem/oem.prop ro.config.wallpaper_component\n"
+			"import /oem/oem.prop ro.oem.*\n"
+			"import /oem/oem.prop oem.*\n"
+			"# begin build properties\n"
+			"# autogenerated by buildinfo.sh\n"
+			"ro.build.id=MPA44I\n"
+			"ro.build.display.id=MPA44I\n"
+			"ro.build.version.incremental=2172151\n"
+			"ro.build.version.sdk=23\n"
+			"ro.build.version.preview_sdk=0\n"
+			"ro.build.version.codename=REL\n"
+			"ro.build.version.all_codenames=REL\n"
+			"ro.build.version.release=6.0\n"
+			"ro.build.version.security_patch=\n"
+			"ro.build.version.base_os=\n"
+			"ro.build.date=Mon Aug 17 16:07:31 UTC 2015\n"
+			"ro.build.date.utc=1439827651\n"
+			"ro.build.type=user\n"
+			"ro.build.user=android-build\n"
+			"ro.build.host=wpee25.hot.corp.google.com\n"
+			"ro.build.tags=release-keys\n"
+			"ro.build.flavor=shamu-user\n"
+			"ro.product.model=Nexus 6\n"
+			"ro.product.brand=google\n"
+			"ro.product.name=shamu\n"
+			"ro.product.device=shamu\n"
+			"ro.product.board=shamu\n"
+			"# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n"
+			"# use ro.product.cpu.abilist instead.\n"
+			"ro.product.cpu.abi=armeabi-v7a\n"
+			"ro.product.cpu.abi2=armeabi\n"
+			"ro.product.cpu.abilist=armeabi-v7a,armeabi\n"
+			"ro.product.cpu.abilist32=armeabi-v7a,armeabi\n"
+			"ro.product.cpu.abilist64=\n"
+			"ro.product.manufacturer=motorola\n"
+			"ro.product.locale=en-US\n"
+			"ro.wifi.channels=\n"
+			"ro.board.platform=msm8084\n"
+			"# ro.build.product is obsolete; use ro.product.device\n"
+			"ro.build.product=shamu\n"
+			"# Do not try to parse description, fingerprint, or thumbprint\n"
+			"ro.build.description=shamu-user 6.0 MPA44I 2172151 release-keys\n"
+			"ro.build.fingerprint=google/shamu/shamu:6.0/MPA44I/2172151:user/release-keys\n"
+			"ro.build.characteristics=nosdcard\n"
+			"# end build properties\n"
+			"\n"
+			"#\n"
+			"# ADDITIONAL_BUILD_PROPERTIES\n"
+			"#\n"
+			"ro.config.ringtone=Titania.ogg\n"
+			"ro.config.notification_sound=Tethys.ogg\n"
+			"ro.config.alarm_alert=Oxygen.ogg\n"
+			"ro.com.android.dataroaming=false\n"
+			"ro.url.legal=http://www.google.com/intl/%s/mobile/android/basic/phone-legal.html\n"
+			"ro.url.legal.android_privacy=http://www.google.com/intl/%s/mobile/android/basic/privacy.html\n"
+			"ro.com.google.clientidbase=android-google\n"
+			"ro.carrier=unknown\n"
+			"ro.com.android.wifi-watchlist=GoogleGuest\n"
+			"ro.error.receiver.system.apps=com.google.android.gms\n"
+			"ro.setupwizard.enterprise_mode=1\n"
+			"fmas.spkr_6ch=35,20,110\n"
+			"fmas.spkr_2ch=35,25\n"
+			"fmas.spkr_angles=10\n"
+			"fmas.spkr_sgain=0\n"
+			"media.aac_51_output_enabled=true\n"
+			"ro.audio.monitorRotation=true\n"
+			"ro.opengles.version=196609\n"
+			"ro.sf.lcd_density=560\n"
+			"persist.hwc.mdpcomp.enable=true\n"
+			"rild.libpath=/system/vendor/lib/libril-qc-qmi-1.so\n"
+			"persist.radio.apm_sim_not_pwdn=1\n"
+			"persist.radio.no_wait_for_card=1\n"
+			"persist.ims.disableDebugLogs=1\n"
+			"persist.ims.disableADBLogs=2\n"
+			"persist.ims.disableQXDMLogs=0\n"
+			"persist.ims.disableIMSLogs=1\n"
+			"persist.camera.hal.debug.mask=7\n"
+			"persist.camera.ISP.debug.mask=0\n"
+			"persist.camera.pproc.debug.mask=7\n"
+			"persist.camera.stats.debug.mask=0\n"
+			"persit.camera.imglib.logs=1\n"
+			"persist.camera.mct.debug.mask=1\n"
+			"persist.camera.sensor.debug=0\n"
+			"vidc.debug.level=1\n"
+			"persist.radio.oem_socket=false\n"
+			"persist.qcril_uim_vcc_feature=1\n"
+			"ro.telephony.default_cdma_sub=0\n"
+			"ro.telephony.default_network=10\n"
+			"telephony.lteOnCdmaDevice=1\n"
+			"persist.radio.fsg_reload_on=1\n"
+			"persist.radio.mcfg_enabled=1\n"
+			"ro.hwui.texture_cache_size=72\n"
+			"ro.hwui.layer_cache_size=48\n"
+			"ro.hwui.r_buffer_cache_size=8\n"
+			"ro.hwui.path_cache_size=32\n"
+			"ro.hwui.gradient_cache_size=1\n"
+			"ro.hwui.drop_shadow_cache_size=6\n"
+			"ro.hwui.texture_cache_flushrate=0.4\n"
+			"ro.hwui.text_small_cache_width=1024\n"
+			"ro.hwui.text_small_cache_height=1024\n"
+			"ro.hwui.text_large_cache_width=2048\n"
+			"ro.hwui.text_large_cache_height=1024\n"
+			"dalvik.vm.heapgrowthlimit=256m\n"
+			"dalvik.vm.heapstartsize=8m\n"
+			"dalvik.vm.heapsize=512m\n"
+			"dalvik.vm.heaptargetutilization=0.75\n"
+			"dalvik.vm.heapminfree=512k\n"
+			"dalvik.vm.heapmaxfree=8m\n"
+			"ro.frp.pst=/dev/block/platform/msm_sdcc.1/by-name/frp\n"
+			"af.fast_track_multiplier=1\n"
+			"audio_hal.period_size=192\n"
+			"persist.rcs.supported=0\n"
+			"persist.audio.dualmic.config=endfire\n"
+			"persist.audio.fluence.voicecall=true\n"
+			"persist.audio.fluence.voicerec=false\n"
+			"persist.audio.fluence.speaker=false\n"
+			"persist.radio.sib16_support=1\n"
+			"persist.data.qmi.adb_logmask=0\n"
+			"persist.data.iwlan.enable=true\n"
+			"persist.radio.ignore_ims_wlan=1\n"
+			"persist.radio.data_con_rprt=1\n"
+			"keyguard.no_require_sim=true\n"
+			"drm.service.enabled=true\n"
+			"ro.facelock.black_timeout=400\n"
+			"ro.facelock.det_timeout=1500\n"
+			"ro.facelock.rec_timeout=2500\n"
+			"ro.facelock.lively_timeout=2500\n"
+			"ro.facelock.est_max_time=600\n"
+			"ro.facelock.use_intro_anim=false\n"
+			"persist.sys.dalvik.vm.lib.2=libart\n"
+			"dalvik.vm.isa.arm.variant=krait\n"
+			"dalvik.vm.isa.arm.features=default\n"
+			"net.bt.name=Android\n"
+			"dalvik.vm.stack-trace-file=/data/anr/traces.txt\n"
+			"ro.build.expect.bootloader=moto-apq8084-71.15\n"
+			"ro.build.expect.baseband=D4.01-9625-05.24+FSG-9625-02.101\n"
+			"ro.expect.recovery_id=0xc7e3a51dcb8bb9aac02a77707b095512cd8b751a000000000000000000000000\n"
+			"\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/kernel_max",
+		.size = 2,
+		.content = "3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/possible",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/present",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq",
+		.size = 8,
+		.content = "2649600\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq",
+		.size = 7,
+		.content = "300000\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/topology/core_siblings_list",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/topology/core_id",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings_list",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_max_freq",
+		.size = 8,
+		.content = "2649600\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_min_freq",
+		.size = 7,
+		.content = "300000\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/topology/physical_package_id",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/topology/core_siblings_list",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/topology/core_id",
+		.size = 2,
+		.content = "1\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu1/topology/thread_siblings_list",
+		.size = 2,
+		.content = "1\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_max_freq",
+		.size = 8,
+		.content = "2649600\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_min_freq",
+		.size = 7,
+		.content = "300000\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/topology/physical_package_id",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/topology/core_siblings_list",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/topology/core_id",
+		.size = 2,
+		.content = "2\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings_list",
+		.size = 2,
+		.content = "2\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_max_freq",
+		.size = 8,
+		.content = "2649600\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_min_freq",
+		.size = 7,
+		.content = "300000\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id",
+		.size = 2,
+		.content = "0\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/topology/core_siblings_list",
+		.size = 4,
+		.content = "0-3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/topology/core_id",
+		.size = 2,
+		.content = "3\n",
+	},
+	{
+		.path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings_list",
+		.size = 2,
+		.content = "3\n",
+	},
+	{ NULL },
+};