Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1 | #include <gtest/gtest.h> |
| 2 | |
| 3 | #include <cpuinfo.h> |
| 4 | |
| 5 | |
| 6 | TEST(PROCESSORS_COUNT, non_zero) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 7 | EXPECT_NE(0, cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 8 | } |
| 9 | |
| 10 | TEST(PROCESSORS, non_null) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 11 | EXPECT_TRUE(cpuinfo_get_processors()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 12 | } |
| 13 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 14 | TEST(PROCESSOR, non_null) { |
| 15 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 16 | EXPECT_TRUE(cpuinfo_get_processor(i)); |
| 17 | } |
| 18 | } |
| 19 | |
| 20 | TEST(PROCESSOR, valid_smt_id) { |
| 21 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 22 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 23 | ASSERT_TRUE(processor); |
| 24 | const cpuinfo_core* core = processor->core; |
| 25 | ASSERT_TRUE(core); |
| 26 | |
| 27 | EXPECT_LT(processor->smt_id, core->processor_count); |
| 28 | } |
| 29 | } |
| 30 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 31 | TEST(PROCESSOR, valid_core) { |
| 32 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 33 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 34 | ASSERT_TRUE(processor); |
| 35 | |
| 36 | EXPECT_TRUE(processor->core); |
| 37 | } |
| 38 | } |
| 39 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 40 | TEST(PROCESSOR, consistent_core) { |
| 41 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 42 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 43 | ASSERT_TRUE(processor); |
| 44 | const cpuinfo_core* core = processor->core; |
| 45 | ASSERT_TRUE(core); |
| 46 | |
| 47 | EXPECT_GE(i, core->processor_start); |
| 48 | EXPECT_LT(i, core->processor_start + core->processor_count); |
| 49 | } |
| 50 | } |
| 51 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 52 | TEST(PROCESSOR, valid_cluster) { |
| 53 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 54 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 55 | ASSERT_TRUE(processor); |
| 56 | |
| 57 | EXPECT_TRUE(processor->cluster); |
| 58 | } |
| 59 | } |
| 60 | |
| 61 | TEST(PROCESSOR, consistent_cluster) { |
| 62 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 63 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 64 | ASSERT_TRUE(processor); |
| 65 | const cpuinfo_cluster* cluster = processor->cluster; |
| 66 | ASSERT_TRUE(cluster); |
| 67 | |
| 68 | EXPECT_GE(i, cluster->processor_start); |
| 69 | EXPECT_LT(i, cluster->processor_start + cluster->processor_count); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | TEST(PROCESSOR, valid_package) { |
| 74 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 75 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 76 | ASSERT_TRUE(processor); |
| 77 | |
| 78 | EXPECT_TRUE(processor->package); |
| 79 | } |
| 80 | } |
| 81 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 82 | TEST(PROCESSOR, consistent_package) { |
| 83 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 84 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 85 | ASSERT_TRUE(processor); |
| 86 | const cpuinfo_package* package = processor->package; |
| 87 | ASSERT_TRUE(package); |
| 88 | |
| 89 | EXPECT_GE(i, package->processor_start); |
| 90 | EXPECT_LT(i, package->processor_start + package->processor_count); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | TEST(PROCESSOR, consistent_l1i) { |
| 95 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 96 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 97 | ASSERT_TRUE(processor); |
| 98 | const cpuinfo_cache* l1i = processor->cache.l1i; |
| 99 | if (l1i != nullptr) { |
| 100 | EXPECT_GE(i, l1i->processor_start); |
| 101 | EXPECT_LT(i, l1i->processor_start + l1i->processor_count); |
| 102 | } |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | TEST(PROCESSOR, consistent_l1d) { |
| 107 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 108 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 109 | ASSERT_TRUE(processor); |
| 110 | const cpuinfo_cache* l1d = processor->cache.l1d; |
| 111 | if (l1d != nullptr) { |
| 112 | EXPECT_GE(i, l1d->processor_start); |
| 113 | EXPECT_LT(i, l1d->processor_start + l1d->processor_count); |
| 114 | } |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | TEST(PROCESSOR, consistent_l2) { |
| 119 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 120 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 121 | ASSERT_TRUE(processor); |
| 122 | const cpuinfo_cache* l2 = processor->cache.l2; |
| 123 | if (l2 != nullptr) { |
| 124 | EXPECT_GE(i, l2->processor_start); |
| 125 | EXPECT_LT(i, l2->processor_start + l2->processor_count); |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | TEST(PROCESSOR, consistent_l3) { |
| 131 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 132 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 133 | ASSERT_TRUE(processor); |
| 134 | const cpuinfo_cache* l3 = processor->cache.l3; |
| 135 | if (l3 != nullptr) { |
| 136 | EXPECT_GE(i, l3->processor_start); |
| 137 | EXPECT_LT(i, l3->processor_start + l3->processor_count); |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | TEST(PROCESSOR, consistent_l4) { |
| 143 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 144 | const cpuinfo_processor* processor = cpuinfo_get_processor(i); |
| 145 | ASSERT_TRUE(processor); |
| 146 | const cpuinfo_cache* l4 = processor->cache.l4; |
| 147 | if (l4 != nullptr) { |
| 148 | EXPECT_GE(i, l4->processor_start); |
| 149 | EXPECT_LT(i, l4->processor_start + l4->processor_count); |
| 150 | } |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | TEST(CORES_COUNT, within_bounds) { |
| 155 | EXPECT_NE(0, cpuinfo_get_cores_count()); |
| 156 | EXPECT_LE(cpuinfo_get_cores_count(), cpuinfo_get_processors_count()); |
| 157 | EXPECT_GE(cpuinfo_get_cores_count(), cpuinfo_get_packages_count()); |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | TEST(CORES, non_null) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 161 | EXPECT_TRUE(cpuinfo_get_cores()); |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 164 | TEST(CORE, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 165 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 166 | EXPECT_TRUE(cpuinfo_get_core(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 167 | } |
| 168 | } |
| 169 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 170 | TEST(CORE, non_zero_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 171 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 172 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 173 | ASSERT_TRUE(core); |
| 174 | |
| 175 | EXPECT_NE(0, core->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 179 | TEST(CORE, consistent_processors) { |
| 180 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 181 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 182 | ASSERT_TRUE(core); |
| 183 | |
| 184 | for (uint32_t i = 0; i < core->processor_count; i++) { |
| 185 | const cpuinfo_processor* processor = cpuinfo_get_processor(core->processor_start + i); |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 186 | ASSERT_TRUE(processor); |
| 187 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 188 | EXPECT_EQ(core, processor->core); |
| 189 | } |
| 190 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 193 | TEST(CORE, valid_core_id) { |
| 194 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 195 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 196 | ASSERT_TRUE(core); |
| 197 | const cpuinfo_package* package = core->package; |
| 198 | ASSERT_TRUE(package); |
| 199 | |
| 200 | EXPECT_LT(core->core_id, package->core_count); |
| 201 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 204 | TEST(CORE, valid_cluster) { |
| 205 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 206 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 207 | ASSERT_TRUE(core); |
| 208 | |
| 209 | EXPECT_TRUE(core->cluster); |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | TEST(CORE, consistent_cluster) { |
| 214 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 215 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 216 | ASSERT_TRUE(core); |
| 217 | const cpuinfo_cluster* cluster = core->cluster; |
| 218 | ASSERT_TRUE(cluster); |
| 219 | |
| 220 | EXPECT_GE(i, cluster->core_start); |
| 221 | EXPECT_LT(i, cluster->core_start + cluster->core_count); |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | TEST(CORE, valid_package) { |
| 226 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 227 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 228 | ASSERT_TRUE(core); |
| 229 | |
| 230 | EXPECT_TRUE(core->package); |
| 231 | } |
| 232 | } |
| 233 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 234 | TEST(CORE, consistent_package) { |
| 235 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 236 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 237 | ASSERT_TRUE(core); |
| 238 | const cpuinfo_package* package = core->package; |
| 239 | ASSERT_TRUE(package); |
| 240 | |
| 241 | EXPECT_GE(i, package->core_start); |
| 242 | EXPECT_LT(i, package->core_start + package->core_count); |
| 243 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 244 | } |
| 245 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 246 | TEST(CORE, known_vendor) { |
| 247 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 248 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 249 | ASSERT_TRUE(core); |
| 250 | |
| 251 | EXPECT_NE(cpuinfo_vendor_unknown, core->vendor); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | TEST(CORE, known_uarch) { |
| 256 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 257 | const cpuinfo_core* core = cpuinfo_get_core(i); |
| 258 | ASSERT_TRUE(core); |
| 259 | |
| 260 | EXPECT_NE(cpuinfo_uarch_unknown, core->uarch); |
| 261 | } |
| 262 | } |
| 263 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 264 | TEST(CLUSTERS_COUNT, within_bounds) { |
| 265 | EXPECT_NE(0, cpuinfo_get_clusters_count()); |
| 266 | EXPECT_LE(cpuinfo_get_clusters_count(), cpuinfo_get_cores_count()); |
| 267 | EXPECT_LE(cpuinfo_get_clusters_count(), cpuinfo_get_processors_count()); |
| 268 | EXPECT_GE(cpuinfo_get_clusters_count(), cpuinfo_get_packages_count()); |
| 269 | } |
| 270 | |
| 271 | TEST(CLUSTERS, non_null) { |
| 272 | EXPECT_TRUE(cpuinfo_get_clusters()); |
| 273 | } |
| 274 | |
| 275 | TEST(CLUSTER, non_null) { |
| 276 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 277 | EXPECT_TRUE(cpuinfo_get_cluster(i)); |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | TEST(CLUSTER, non_zero_processors) { |
| 282 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 283 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 284 | ASSERT_TRUE(cluster); |
| 285 | |
| 286 | EXPECT_NE(0, cluster->processor_count); |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | TEST(CLUSTER, valid_processors) { |
| 291 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 292 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 293 | ASSERT_TRUE(cluster); |
| 294 | |
| 295 | EXPECT_LT(cluster->processor_start, cpuinfo_get_processors_count()); |
| 296 | EXPECT_LE(cluster->processor_start + cluster->processor_count, cpuinfo_get_processors_count()); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | TEST(CLUSTER, consistent_processors) { |
| 301 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 302 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 303 | ASSERT_TRUE(cluster); |
| 304 | |
| 305 | for (uint32_t j = 0; j < cluster->processor_count; j++) { |
| 306 | const cpuinfo_processor* processor = cpuinfo_get_processor(cluster->processor_start + j); |
| 307 | EXPECT_EQ(cluster, processor->cluster); |
| 308 | } |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | TEST(CLUSTER, non_zero_cores) { |
| 313 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 314 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 315 | ASSERT_TRUE(cluster); |
| 316 | |
| 317 | EXPECT_NE(0, cluster->core_count); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | TEST(CLUSTER, valid_cores) { |
| 322 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 323 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 324 | ASSERT_TRUE(cluster); |
| 325 | |
| 326 | EXPECT_LT(cluster->core_start, cpuinfo_get_cores_count()); |
| 327 | EXPECT_LE(cluster->core_start + cluster->core_count, cpuinfo_get_cores_count()); |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | TEST(CLUSTER, consistent_cores) { |
| 332 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 333 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 334 | ASSERT_TRUE(cluster); |
| 335 | |
| 336 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 337 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 338 | ASSERT_TRUE(core); |
| 339 | |
| 340 | EXPECT_EQ(cluster, core->cluster); |
| 341 | } |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | TEST(CLUSTER, valid_cluster_id) { |
| 346 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 347 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 348 | ASSERT_TRUE(cluster); |
| 349 | |
| 350 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 351 | const cpuinfo_package* package = cluster->package; |
| 352 | ASSERT_TRUE(package); |
| 353 | |
| 354 | EXPECT_LT(cluster->cluster_id, package->cluster_count); |
| 355 | } |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | TEST(CLUSTER, valid_package) { |
| 360 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 361 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 362 | ASSERT_TRUE(cluster); |
| 363 | |
| 364 | EXPECT_TRUE(cluster->package); |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | TEST(CLUSTER, consistent_package) { |
| 369 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 370 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 371 | ASSERT_TRUE(cluster); |
| 372 | const cpuinfo_package* package = cluster->package; |
| 373 | ASSERT_TRUE(package); |
| 374 | |
| 375 | EXPECT_GE(i, package->cluster_start); |
| 376 | EXPECT_LT(i, package->cluster_start + package->cluster_count); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | TEST(CLUSTER, consistent_vendor) { |
| 381 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 382 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 383 | ASSERT_TRUE(cluster); |
| 384 | |
| 385 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 386 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 387 | ASSERT_TRUE(core); |
| 388 | |
| 389 | EXPECT_EQ(cluster->vendor, core->vendor); |
| 390 | } |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | TEST(CLUSTER, consistent_uarch) { |
| 395 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 396 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 397 | ASSERT_TRUE(cluster); |
| 398 | |
| 399 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 400 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 401 | ASSERT_TRUE(core); |
| 402 | |
| 403 | EXPECT_EQ(cluster->uarch, core->uarch); |
| 404 | } |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 409 | TEST(CLUSTER, consistent_cpuid) { |
| 410 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 411 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 412 | ASSERT_TRUE(cluster); |
| 413 | |
| 414 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 415 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 416 | ASSERT_TRUE(core); |
| 417 | |
| 418 | EXPECT_EQ(cluster->cpuid, core->cpuid); |
| 419 | } |
| 420 | } |
| 421 | } |
| 422 | #endif /* CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 */ |
| 423 | |
| 424 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 425 | TEST(CLUSTER, consistent_midr) { |
| 426 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 427 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 428 | ASSERT_TRUE(cluster); |
| 429 | |
| 430 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 431 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 432 | ASSERT_TRUE(core); |
| 433 | |
| 434 | EXPECT_EQ(cluster->midr, core->midr); |
| 435 | } |
| 436 | } |
| 437 | } |
| 438 | #endif /* CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 */ |
| 439 | |
| 440 | TEST(CLUSTER, consistent_frequency) { |
| 441 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 442 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i); |
| 443 | ASSERT_TRUE(cluster); |
| 444 | |
| 445 | for (uint32_t j = 0; j < cluster->core_count; j++) { |
| 446 | const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j); |
| 447 | ASSERT_TRUE(core); |
| 448 | |
| 449 | EXPECT_EQ(cluster->frequency, core->frequency); |
| 450 | } |
| 451 | } |
| 452 | } |
| 453 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 454 | TEST(PACKAGES_COUNT, within_bounds) { |
| 455 | EXPECT_NE(0, cpuinfo_get_packages_count()); |
| 456 | EXPECT_LE(cpuinfo_get_packages_count(), cpuinfo_get_cores_count()); |
| 457 | EXPECT_LE(cpuinfo_get_packages_count(), cpuinfo_get_processors_count()); |
| 458 | } |
| 459 | |
| 460 | TEST(PACKAGES, non_null) { |
| 461 | EXPECT_TRUE(cpuinfo_get_packages()); |
| 462 | } |
| 463 | |
| 464 | TEST(PACKAGE, non_null) { |
| 465 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 466 | EXPECT_TRUE(cpuinfo_get_package(i)); |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | TEST(PACKAGE, non_zero_processors) { |
| 471 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 472 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 473 | ASSERT_TRUE(package); |
| 474 | |
| 475 | EXPECT_NE(0, package->processor_count); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | TEST(PACKAGE, valid_processors) { |
| 480 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 481 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 482 | ASSERT_TRUE(package); |
| 483 | |
| 484 | EXPECT_LT(package->processor_start, cpuinfo_get_processors_count()); |
| 485 | EXPECT_LE(package->processor_start + package->processor_count, cpuinfo_get_processors_count()); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | TEST(PACKAGE, consistent_processors) { |
| 490 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 491 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 492 | ASSERT_TRUE(package); |
| 493 | |
| 494 | for (uint32_t j = 0; j < package->processor_count; j++) { |
| 495 | const cpuinfo_processor* processor = cpuinfo_get_processor(package->processor_start + j); |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 496 | ASSERT_TRUE(processor); |
| 497 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 498 | EXPECT_EQ(package, processor->package); |
| 499 | } |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | TEST(PACKAGE, non_zero_cores) { |
| 504 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 505 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 506 | ASSERT_TRUE(package); |
| 507 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 508 | EXPECT_NE(0, package->core_count); |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 509 | } |
| 510 | } |
| 511 | |
| 512 | TEST(PACKAGE, valid_cores) { |
| 513 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 514 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 515 | ASSERT_TRUE(package); |
| 516 | |
| 517 | EXPECT_LT(package->core_start, cpuinfo_get_cores_count()); |
| 518 | EXPECT_LE(package->core_start + package->core_count, cpuinfo_get_cores_count()); |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | TEST(PACKAGE, consistent_cores) { |
| 523 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 524 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 525 | ASSERT_TRUE(package); |
| 526 | |
| 527 | for (uint32_t j = 0; j < package->core_count; j++) { |
| 528 | const cpuinfo_core* core = cpuinfo_get_core(package->core_start + j); |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 529 | ASSERT_TRUE(core); |
| 530 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 531 | EXPECT_EQ(package, core->package); |
| 532 | } |
| 533 | } |
| 534 | } |
| 535 | |
Marat Dukhan | 4d376c3 | 2018-03-18 11:36:39 -0700 | [diff] [blame] | 536 | TEST(PACKAGE, non_zero_clusters) { |
| 537 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 538 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 539 | ASSERT_TRUE(package); |
| 540 | |
| 541 | EXPECT_NE(0, package->cluster_count); |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | TEST(PACKAGE, valid_clusters) { |
| 546 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 547 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 548 | ASSERT_TRUE(package); |
| 549 | |
| 550 | EXPECT_LT(package->cluster_start, cpuinfo_get_clusters_count()); |
| 551 | EXPECT_LE(package->cluster_start + package->cluster_count, cpuinfo_get_clusters_count()); |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | TEST(PACKAGE, consistent_cluster) { |
| 556 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 557 | const cpuinfo_package* package = cpuinfo_get_package(i); |
| 558 | ASSERT_TRUE(package); |
| 559 | |
| 560 | for (uint32_t j = 0; j < package->cluster_count; j++) { |
| 561 | const cpuinfo_cluster* cluster = cpuinfo_get_cluster(package->cluster_start + j); |
| 562 | ASSERT_TRUE(cluster); |
| 563 | |
| 564 | EXPECT_EQ(package, cluster->package); |
| 565 | } |
| 566 | } |
| 567 | } |
| 568 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 569 | TEST(L1I_CACHES_COUNT, within_bounds) { |
| 570 | EXPECT_NE(0, cpuinfo_get_l1i_caches_count()); |
| 571 | EXPECT_LE(cpuinfo_get_l1i_caches_count(), cpuinfo_get_processors_count()); |
| 572 | } |
| 573 | |
| 574 | TEST(L1I_CACHES, non_null) { |
| 575 | EXPECT_TRUE(cpuinfo_get_l1i_caches()); |
| 576 | } |
| 577 | |
| 578 | TEST(L1I_CACHE, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 579 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 580 | EXPECT_TRUE(cpuinfo_get_l1i_cache(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 581 | } |
| 582 | } |
| 583 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 584 | TEST(L1I_CACHE, non_zero_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 585 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 586 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 587 | ASSERT_TRUE(cache); |
| 588 | |
| 589 | EXPECT_NE(0, cache->size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 590 | } |
| 591 | } |
| 592 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 593 | TEST(L1I_CACHE, valid_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 594 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 595 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 596 | ASSERT_TRUE(cache); |
| 597 | |
| 598 | EXPECT_EQ(cache->size, |
| 599 | cache->associativity * cache->sets * cache->partitions * cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 600 | } |
| 601 | } |
| 602 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 603 | TEST(L1I_CACHE, non_zero_associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 604 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 605 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 606 | ASSERT_TRUE(cache); |
| 607 | |
| 608 | EXPECT_NE(0, cache->associativity); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 609 | } |
| 610 | } |
| 611 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 612 | TEST(L1I_CACHE, non_zero_partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 613 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 614 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 615 | ASSERT_TRUE(cache); |
| 616 | |
| 617 | EXPECT_NE(0, cache->partitions); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 618 | } |
| 619 | } |
| 620 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 621 | TEST(L1I_CACHE, non_zero_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 622 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 623 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 624 | ASSERT_TRUE(cache); |
| 625 | |
| 626 | EXPECT_NE(0, cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 627 | } |
| 628 | } |
| 629 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 630 | TEST(L1I_CACHE, power_of_2_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 631 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 632 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 633 | ASSERT_TRUE(cache); |
| 634 | |
| 635 | const uint32_t line_size = cache->line_size; |
| 636 | EXPECT_NE(0, line_size); |
| 637 | EXPECT_EQ(0, line_size & (line_size - 1)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 638 | } |
| 639 | } |
| 640 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 641 | TEST(L1I_CACHE, reasonable_line_size) { |
| 642 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 643 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 644 | ASSERT_TRUE(cache); |
| 645 | |
| 646 | EXPECT_GE(cache->line_size, 16); |
| 647 | EXPECT_LE(cache->line_size, 128); |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | TEST(L1I_CACHE, valid_flags) { |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 652 | const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING; |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 653 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 654 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 655 | ASSERT_TRUE(cache); |
| 656 | |
| 657 | EXPECT_EQ(0, cache->flags & ~valid_flags); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 658 | } |
| 659 | } |
| 660 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 661 | TEST(L1I_CACHE, non_inclusive) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 662 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 663 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 664 | ASSERT_TRUE(cache); |
| 665 | |
| 666 | EXPECT_NE(CPUINFO_CACHE_INCLUSIVE, cache->flags & CPUINFO_CACHE_INCLUSIVE); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 667 | } |
| 668 | } |
| 669 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 670 | TEST(L1I_CACHE, non_zero_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 671 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 672 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 673 | ASSERT_TRUE(cache); |
| 674 | |
| 675 | EXPECT_NE(0, cache->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 676 | } |
| 677 | } |
| 678 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 679 | TEST(L1I_CACHE, valid_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 680 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 681 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 682 | ASSERT_TRUE(cache); |
| 683 | |
| 684 | EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count()); |
| 685 | EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 686 | } |
| 687 | } |
| 688 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 689 | TEST(L1I_CACHE, consistent_processors) { |
| 690 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 691 | const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); |
| 692 | ASSERT_TRUE(cache); |
| 693 | |
| 694 | for (uint32_t j = 0; j < cache->processor_count; j++) { |
| 695 | const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j); |
| 696 | ASSERT_TRUE(processor); |
| 697 | |
| 698 | EXPECT_EQ(cache, processor->cache.l1i); |
| 699 | } |
| 700 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 701 | } |
| 702 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 703 | TEST(L1D_CACHES_COUNT, within_bounds) { |
| 704 | EXPECT_NE(0, cpuinfo_get_l1d_caches_count()); |
| 705 | EXPECT_LE(cpuinfo_get_l1d_caches_count(), cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 706 | } |
| 707 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 708 | TEST(L1D_CACHES, non_null) { |
| 709 | EXPECT_TRUE(cpuinfo_get_l1d_caches()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 710 | } |
| 711 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 712 | TEST(L1D_CACHE, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 713 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 714 | EXPECT_TRUE(cpuinfo_get_l1d_cache(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 715 | } |
| 716 | } |
| 717 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 718 | TEST(L1D_CACHE, non_zero_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 719 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 720 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 721 | ASSERT_TRUE(cache); |
| 722 | |
| 723 | EXPECT_NE(0, cache->size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 724 | } |
| 725 | } |
| 726 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 727 | TEST(L1D_CACHE, valid_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 728 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 729 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 730 | ASSERT_TRUE(cache); |
| 731 | |
| 732 | EXPECT_EQ(cache->size, |
| 733 | cache->associativity * cache->sets * cache->partitions * cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 737 | TEST(L1D_CACHE, non_zero_associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 738 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 739 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 740 | ASSERT_TRUE(cache); |
| 741 | |
| 742 | EXPECT_NE(0, cache->associativity); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 743 | } |
| 744 | } |
| 745 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 746 | TEST(L1D_CACHE, non_zero_partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 747 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 748 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 749 | ASSERT_TRUE(cache); |
| 750 | |
| 751 | EXPECT_NE(0, cache->partitions); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 752 | } |
| 753 | } |
| 754 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 755 | TEST(L1D_CACHE, non_zero_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 756 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 757 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 758 | ASSERT_TRUE(cache); |
| 759 | |
| 760 | EXPECT_NE(0, cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 761 | } |
| 762 | } |
| 763 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 764 | TEST(L1D_CACHE, power_of_2_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 765 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 766 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 767 | ASSERT_TRUE(cache); |
| 768 | |
| 769 | const uint32_t line_size = cache->line_size; |
| 770 | EXPECT_NE(0, line_size); |
| 771 | EXPECT_EQ(0, line_size & (line_size - 1)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 772 | } |
| 773 | } |
| 774 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 775 | TEST(L1D_CACHE, reasonable_line_size) { |
| 776 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 777 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 778 | ASSERT_TRUE(cache); |
| 779 | |
| 780 | EXPECT_GE(cache->line_size, 16); |
| 781 | EXPECT_LE(cache->line_size, 128); |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | TEST(L1D_CACHE, valid_flags) { |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 786 | const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING; |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 787 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 788 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 789 | ASSERT_TRUE(cache); |
| 790 | |
| 791 | EXPECT_EQ(0, cache->flags & ~valid_flags); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 792 | } |
| 793 | } |
| 794 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 795 | TEST(L1D_CACHE, non_inclusive) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 796 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 797 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 798 | ASSERT_TRUE(cache); |
| 799 | |
| 800 | EXPECT_NE(CPUINFO_CACHE_INCLUSIVE, cache->flags & CPUINFO_CACHE_INCLUSIVE); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 801 | } |
| 802 | } |
| 803 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 804 | TEST(L1D_CACHE, non_zero_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 805 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 806 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 807 | ASSERT_TRUE(cache); |
| 808 | |
| 809 | EXPECT_NE(0, cache->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 810 | } |
| 811 | } |
| 812 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 813 | TEST(L1D_CACHE, valid_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 814 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 815 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 816 | ASSERT_TRUE(cache); |
| 817 | |
| 818 | EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count()); |
| 819 | EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 820 | } |
| 821 | } |
| 822 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 823 | TEST(L1D_CACHE, consistent_processors) { |
| 824 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 825 | const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); |
| 826 | ASSERT_TRUE(cache); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 827 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 828 | for (uint32_t j = 0; j < cache->processor_count; j++) { |
| 829 | const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j); |
| 830 | ASSERT_TRUE(processor); |
| 831 | |
| 832 | EXPECT_EQ(cache, processor->cache.l1d); |
| 833 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 834 | } |
| 835 | } |
| 836 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 837 | TEST(L2_CACHES_COUNT, within_bounds) { |
| 838 | EXPECT_NE(0, cpuinfo_get_l2_caches_count()); |
| 839 | EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_processors_count()); |
| 840 | EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_l1d_caches_count()); |
| 841 | EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_l1i_caches_count()); |
| 842 | } |
| 843 | |
| 844 | TEST(L2_CACHES, non_null) { |
| 845 | EXPECT_TRUE(cpuinfo_get_l2_caches()); |
| 846 | } |
| 847 | |
| 848 | TEST(L2_CACHE, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 849 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 850 | EXPECT_TRUE(cpuinfo_get_l2_cache(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 851 | } |
| 852 | } |
| 853 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 854 | TEST(L2_CACHE, non_zero_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 855 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 856 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 857 | ASSERT_TRUE(cache); |
| 858 | |
| 859 | EXPECT_NE(0, cache->size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 860 | } |
| 861 | } |
| 862 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 863 | TEST(L2_CACHE, valid_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 864 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 865 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 866 | ASSERT_TRUE(cache); |
| 867 | |
| 868 | EXPECT_EQ(cache->size, |
| 869 | cache->associativity * cache->sets * cache->partitions * cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 870 | } |
| 871 | } |
| 872 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 873 | TEST(L2_CACHE, non_zero_associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 874 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 875 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 876 | ASSERT_TRUE(cache); |
| 877 | |
| 878 | EXPECT_NE(0, cache->associativity); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 879 | } |
| 880 | } |
| 881 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 882 | TEST(L2_CACHE, non_zero_partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 883 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 884 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 885 | ASSERT_TRUE(cache); |
| 886 | |
| 887 | EXPECT_NE(0, cache->partitions); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 888 | } |
| 889 | } |
| 890 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 891 | TEST(L2_CACHE, non_zero_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 892 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 893 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 894 | ASSERT_TRUE(cache); |
| 895 | |
| 896 | EXPECT_NE(0, cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 897 | } |
| 898 | } |
| 899 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 900 | TEST(L2_CACHE, power_of_2_line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 901 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 902 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 903 | ASSERT_TRUE(cache); |
| 904 | |
| 905 | const uint32_t line_size = cache->line_size; |
| 906 | EXPECT_NE(0, line_size); |
| 907 | EXPECT_EQ(0, line_size & (line_size - 1)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 908 | } |
| 909 | } |
| 910 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 911 | TEST(L2_CACHE, reasonable_line_size) { |
| 912 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 913 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 914 | ASSERT_TRUE(cache); |
| 915 | |
| 916 | EXPECT_GE(cache->line_size, 16); |
| 917 | EXPECT_LE(cache->line_size, 128); |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | TEST(L2_CACHE, valid_flags) { |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 922 | const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING; |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 923 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 924 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 925 | ASSERT_TRUE(cache); |
| 926 | |
| 927 | EXPECT_EQ(0, cache->flags & ~valid_flags); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 928 | } |
| 929 | } |
| 930 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 931 | TEST(L2_CACHE, non_zero_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 932 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 933 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 934 | ASSERT_TRUE(cache); |
| 935 | |
| 936 | EXPECT_NE(0, cache->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 937 | } |
| 938 | } |
| 939 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 940 | TEST(L2_CACHE, valid_processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 941 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 942 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 943 | ASSERT_TRUE(cache); |
| 944 | |
| 945 | EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count()); |
| 946 | EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 947 | } |
| 948 | } |
| 949 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 950 | TEST(L2_CACHE, consistent_processors) { |
| 951 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 952 | const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); |
| 953 | ASSERT_TRUE(cache); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 954 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 955 | for (uint32_t j = 0; j < cache->processor_count; j++) { |
| 956 | const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j); |
| 957 | ASSERT_TRUE(processor); |
| 958 | |
| 959 | EXPECT_EQ(cache, processor->cache.l2); |
| 960 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 961 | } |
| 962 | } |
| 963 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 964 | TEST(L3_CACHES_COUNT, within_bounds) { |
| 965 | EXPECT_LE(cpuinfo_get_l3_caches_count(), cpuinfo_get_processors_count()); |
| 966 | EXPECT_LE(cpuinfo_get_l3_caches_count(), cpuinfo_get_l2_caches_count()); |
| 967 | } |
| 968 | |
| 969 | TEST(L3_CACHE, non_null) { |
| 970 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 971 | EXPECT_TRUE(cpuinfo_get_l3_cache(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 972 | } |
| 973 | } |
| 974 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 975 | TEST(L3_CACHE, non_zero_size) { |
| 976 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 977 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 978 | ASSERT_TRUE(cache); |
| 979 | |
| 980 | EXPECT_NE(0, cache->size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 981 | } |
| 982 | } |
| 983 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 984 | TEST(L3_CACHE, valid_size) { |
| 985 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 986 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 987 | ASSERT_TRUE(cache); |
| 988 | |
| 989 | EXPECT_EQ(cache->size, |
| 990 | cache->associativity * cache->sets * cache->partitions * cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 991 | } |
| 992 | } |
| 993 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 994 | TEST(L3_CACHE, non_zero_associativity) { |
| 995 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 996 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 997 | ASSERT_TRUE(cache); |
| 998 | |
| 999 | EXPECT_NE(0, cache->associativity); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1000 | } |
| 1001 | } |
| 1002 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1003 | TEST(L3_CACHE, non_zero_partitions) { |
| 1004 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1005 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1006 | ASSERT_TRUE(cache); |
| 1007 | |
| 1008 | EXPECT_NE(0, cache->partitions); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1009 | } |
| 1010 | } |
| 1011 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1012 | TEST(L3_CACHE, non_zero_line_size) { |
| 1013 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1014 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1015 | ASSERT_TRUE(cache); |
| 1016 | |
| 1017 | EXPECT_NE(0, cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1018 | } |
| 1019 | } |
| 1020 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1021 | TEST(L3_CACHE, power_of_2_line_size) { |
| 1022 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1023 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1024 | ASSERT_TRUE(cache); |
| 1025 | |
| 1026 | const uint32_t line_size = cache->line_size; |
| 1027 | EXPECT_NE(0, line_size); |
| 1028 | EXPECT_EQ(0, line_size & (line_size - 1)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1029 | } |
| 1030 | } |
| 1031 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1032 | TEST(L3_CACHE, reasonable_line_size) { |
| 1033 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1034 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1035 | ASSERT_TRUE(cache); |
| 1036 | |
| 1037 | EXPECT_GE(cache->line_size, 16); |
| 1038 | EXPECT_LE(cache->line_size, 128); |
| 1039 | } |
| 1040 | } |
| 1041 | |
| 1042 | TEST(L3_CACHE, valid_flags) { |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1043 | const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING; |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1044 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1045 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1046 | ASSERT_TRUE(cache); |
| 1047 | |
| 1048 | EXPECT_EQ(0, cache->flags & ~valid_flags); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1049 | } |
| 1050 | } |
| 1051 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1052 | TEST(L3_CACHE, non_zero_processors) { |
| 1053 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1054 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1055 | ASSERT_TRUE(cache); |
| 1056 | |
| 1057 | EXPECT_NE(0, cache->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1058 | } |
| 1059 | } |
| 1060 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1061 | TEST(L3_CACHE, valid_processors) { |
| 1062 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1063 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1064 | ASSERT_TRUE(cache); |
| 1065 | |
| 1066 | EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count()); |
| 1067 | EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count()); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1068 | } |
| 1069 | } |
| 1070 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1071 | TEST(L3_CACHE, consistent_processors) { |
| 1072 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 1073 | const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); |
| 1074 | ASSERT_TRUE(cache); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1075 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1076 | for (uint32_t j = 0; j < cache->processor_count; j++) { |
| 1077 | const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j); |
| 1078 | ASSERT_TRUE(processor); |
| 1079 | |
| 1080 | EXPECT_EQ(cache, processor->cache.l3); |
| 1081 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1082 | } |
| 1083 | } |
| 1084 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1085 | TEST(L4_CACHES_COUNT, within_bounds) { |
| 1086 | EXPECT_LE(cpuinfo_get_l4_caches_count(), cpuinfo_get_processors_count()); |
| 1087 | EXPECT_LE(cpuinfo_get_l4_caches_count(), cpuinfo_get_l3_caches_count()); |
| 1088 | } |
| 1089 | |
| 1090 | TEST(L4_CACHE, non_null) { |
| 1091 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1092 | EXPECT_TRUE(cpuinfo_get_l4_cache(i)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1093 | } |
| 1094 | } |
| 1095 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1096 | TEST(L4_CACHE, non_zero_size) { |
| 1097 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1098 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1099 | ASSERT_TRUE(cache); |
| 1100 | |
| 1101 | EXPECT_NE(0, cache->size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1102 | } |
| 1103 | } |
| 1104 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1105 | TEST(L4_CACHE, valid_size) { |
| 1106 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1107 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1108 | ASSERT_TRUE(cache); |
| 1109 | |
| 1110 | EXPECT_EQ(cache->size, |
| 1111 | cache->associativity * cache->sets * cache->partitions * cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1112 | } |
| 1113 | } |
| 1114 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1115 | TEST(L4_CACHE, non_zero_associativity) { |
| 1116 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1117 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1118 | ASSERT_TRUE(cache); |
| 1119 | |
| 1120 | EXPECT_NE(0, cache->associativity); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1121 | } |
| 1122 | } |
| 1123 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1124 | TEST(L4_CACHE, non_zero_partitions) { |
| 1125 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1126 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1127 | ASSERT_TRUE(cache); |
| 1128 | |
| 1129 | EXPECT_NE(0, cache->partitions); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1130 | } |
| 1131 | } |
| 1132 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1133 | TEST(L4_CACHE, non_zero_line_size) { |
| 1134 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1135 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1136 | ASSERT_TRUE(cache); |
| 1137 | |
| 1138 | EXPECT_NE(0, cache->line_size); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1142 | TEST(L4_CACHE, power_of_2_line_size) { |
| 1143 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1144 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1145 | ASSERT_TRUE(cache); |
| 1146 | |
| 1147 | const uint32_t line_size = cache->line_size; |
| 1148 | EXPECT_NE(0, line_size); |
| 1149 | EXPECT_EQ(0, line_size & (line_size - 1)); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1150 | } |
| 1151 | } |
| 1152 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1153 | TEST(L4_CACHE, reasonable_line_size) { |
| 1154 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1155 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1156 | ASSERT_TRUE(cache); |
| 1157 | |
| 1158 | EXPECT_GE(cache->line_size, 16); |
| 1159 | EXPECT_LE(cache->line_size, 128); |
| 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | TEST(L4_CACHE, valid_flags) { |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1164 | const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING; |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1165 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1166 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1167 | ASSERT_TRUE(cache); |
| 1168 | |
| 1169 | EXPECT_EQ(0, cache->flags & ~valid_flags); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1170 | } |
| 1171 | } |
| 1172 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1173 | TEST(L4_CACHE, non_zero_processors) { |
| 1174 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1175 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1176 | ASSERT_TRUE(cache); |
| 1177 | |
| 1178 | EXPECT_NE(0, cache->processor_count); |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1179 | } |
| 1180 | } |
| 1181 | |
Marat Dukhan | e846401 | 2018-03-18 00:30:45 -0700 | [diff] [blame] | 1182 | TEST(L4_CACHE, valid_processors) { |
| 1183 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1184 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1185 | ASSERT_TRUE(cache); |
| 1186 | |
| 1187 | EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count()); |
| 1188 | EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count()); |
| 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | TEST(L4_CACHE, consistent_processors) { |
| 1193 | for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) { |
| 1194 | const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); |
| 1195 | ASSERT_TRUE(cache); |
| 1196 | |
| 1197 | for (uint32_t j = 0; j < cache->processor_count; j++) { |
| 1198 | const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j); |
| 1199 | ASSERT_TRUE(processor); |
| 1200 | |
| 1201 | EXPECT_EQ(cache, processor->cache.l4); |
| 1202 | } |
Marat Dukhan | 4f63992 | 2017-05-08 07:24:37 +0000 | [diff] [blame] | 1203 | } |
| 1204 | } |
| 1205 | |
| 1206 | int main(int argc, char* argv[]) { |
| 1207 | cpuinfo_initialize(); |
| 1208 | ::testing::InitGoogleTest(&argc, argv); |
| 1209 | return RUN_ALL_TESTS(); |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1210 | } |