blob: 0ab01273095621d7c0368d27d3e3742dd7f9ce88 [file] [log] [blame]
Marat Dukhan4f639922017-05-08 07:24:37 +00001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4
5
6TEST(PROCESSORS_COUNT, non_zero) {
Marat Dukhane8464012018-03-18 00:30:45 -07007 EXPECT_NE(0, cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +00008}
9
10TEST(PROCESSORS, non_null) {
Marat Dukhane8464012018-03-18 00:30:45 -070011 EXPECT_TRUE(cpuinfo_get_processors());
Marat Dukhan4f639922017-05-08 07:24:37 +000012}
13
Marat Dukhane8464012018-03-18 00:30:45 -070014TEST(PROCESSOR, non_null) {
15 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
16 EXPECT_TRUE(cpuinfo_get_processor(i));
17 }
18}
19
20TEST(PROCESSOR, valid_smt_id) {
21 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
22 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
23 ASSERT_TRUE(processor);
24 const cpuinfo_core* core = processor->core;
25 ASSERT_TRUE(core);
26
27 EXPECT_LT(processor->smt_id, core->processor_count);
28 }
29}
30
Marat Dukhan4d376c32018-03-18 11:36:39 -070031TEST(PROCESSOR, valid_core) {
32 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
33 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
34 ASSERT_TRUE(processor);
35
36 EXPECT_TRUE(processor->core);
37 }
38}
39
Marat Dukhane8464012018-03-18 00:30:45 -070040TEST(PROCESSOR, consistent_core) {
41 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
42 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
43 ASSERT_TRUE(processor);
44 const cpuinfo_core* core = processor->core;
45 ASSERT_TRUE(core);
46
47 EXPECT_GE(i, core->processor_start);
48 EXPECT_LT(i, core->processor_start + core->processor_count);
49 }
50}
51
Marat Dukhan4d376c32018-03-18 11:36:39 -070052TEST(PROCESSOR, valid_cluster) {
53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
55 ASSERT_TRUE(processor);
56
57 EXPECT_TRUE(processor->cluster);
58 }
59}
60
61TEST(PROCESSOR, consistent_cluster) {
62 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
63 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
64 ASSERT_TRUE(processor);
65 const cpuinfo_cluster* cluster = processor->cluster;
66 ASSERT_TRUE(cluster);
67
68 EXPECT_GE(i, cluster->processor_start);
69 EXPECT_LT(i, cluster->processor_start + cluster->processor_count);
70 }
71}
72
73TEST(PROCESSOR, valid_package) {
74 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
75 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
76 ASSERT_TRUE(processor);
77
78 EXPECT_TRUE(processor->package);
79 }
80}
81
Marat Dukhane8464012018-03-18 00:30:45 -070082TEST(PROCESSOR, consistent_package) {
83 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
84 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
85 ASSERT_TRUE(processor);
86 const cpuinfo_package* package = processor->package;
87 ASSERT_TRUE(package);
88
89 EXPECT_GE(i, package->processor_start);
90 EXPECT_LT(i, package->processor_start + package->processor_count);
91 }
92}
93
94TEST(PROCESSOR, consistent_l1i) {
95 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
96 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
97 ASSERT_TRUE(processor);
98 const cpuinfo_cache* l1i = processor->cache.l1i;
99 if (l1i != nullptr) {
100 EXPECT_GE(i, l1i->processor_start);
101 EXPECT_LT(i, l1i->processor_start + l1i->processor_count);
102 }
103 }
104}
105
106TEST(PROCESSOR, consistent_l1d) {
107 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
108 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
109 ASSERT_TRUE(processor);
110 const cpuinfo_cache* l1d = processor->cache.l1d;
111 if (l1d != nullptr) {
112 EXPECT_GE(i, l1d->processor_start);
113 EXPECT_LT(i, l1d->processor_start + l1d->processor_count);
114 }
115 }
116}
117
118TEST(PROCESSOR, consistent_l2) {
119 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
120 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
121 ASSERT_TRUE(processor);
122 const cpuinfo_cache* l2 = processor->cache.l2;
123 if (l2 != nullptr) {
124 EXPECT_GE(i, l2->processor_start);
125 EXPECT_LT(i, l2->processor_start + l2->processor_count);
126 }
127 }
128}
129
130TEST(PROCESSOR, consistent_l3) {
131 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
132 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
133 ASSERT_TRUE(processor);
134 const cpuinfo_cache* l3 = processor->cache.l3;
135 if (l3 != nullptr) {
136 EXPECT_GE(i, l3->processor_start);
137 EXPECT_LT(i, l3->processor_start + l3->processor_count);
138 }
139 }
140}
141
142TEST(PROCESSOR, consistent_l4) {
143 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
144 const cpuinfo_processor* processor = cpuinfo_get_processor(i);
145 ASSERT_TRUE(processor);
146 const cpuinfo_cache* l4 = processor->cache.l4;
147 if (l4 != nullptr) {
148 EXPECT_GE(i, l4->processor_start);
149 EXPECT_LT(i, l4->processor_start + l4->processor_count);
150 }
151 }
152}
153
154TEST(CORES_COUNT, within_bounds) {
155 EXPECT_NE(0, cpuinfo_get_cores_count());
156 EXPECT_LE(cpuinfo_get_cores_count(), cpuinfo_get_processors_count());
157 EXPECT_GE(cpuinfo_get_cores_count(), cpuinfo_get_packages_count());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700158}
159
160TEST(CORES, non_null) {
Marat Dukhane8464012018-03-18 00:30:45 -0700161 EXPECT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700162}
163
Marat Dukhane8464012018-03-18 00:30:45 -0700164TEST(CORE, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700165 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700166 EXPECT_TRUE(cpuinfo_get_core(i));
Marat Dukhan4f639922017-05-08 07:24:37 +0000167 }
168}
169
Marat Dukhane8464012018-03-18 00:30:45 -0700170TEST(CORE, non_zero_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700171 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700172 const cpuinfo_core* core = cpuinfo_get_core(i);
173 ASSERT_TRUE(core);
174
175 EXPECT_NE(0, core->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +0000176 }
177}
178
Marat Dukhane8464012018-03-18 00:30:45 -0700179TEST(CORE, consistent_processors) {
180 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
181 const cpuinfo_core* core = cpuinfo_get_core(i);
182 ASSERT_TRUE(core);
183
184 for (uint32_t i = 0; i < core->processor_count; i++) {
185 const cpuinfo_processor* processor = cpuinfo_get_processor(core->processor_start + i);
Marat Dukhan4d376c32018-03-18 11:36:39 -0700186 ASSERT_TRUE(processor);
187
Marat Dukhane8464012018-03-18 00:30:45 -0700188 EXPECT_EQ(core, processor->core);
189 }
190 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000191}
192
Marat Dukhane8464012018-03-18 00:30:45 -0700193TEST(CORE, valid_core_id) {
194 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
195 const cpuinfo_core* core = cpuinfo_get_core(i);
196 ASSERT_TRUE(core);
197 const cpuinfo_package* package = core->package;
198 ASSERT_TRUE(package);
199
200 EXPECT_LT(core->core_id, package->core_count);
201 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000202}
203
Marat Dukhan4d376c32018-03-18 11:36:39 -0700204TEST(CORE, valid_cluster) {
205 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
206 const cpuinfo_core* core = cpuinfo_get_core(i);
207 ASSERT_TRUE(core);
208
209 EXPECT_TRUE(core->cluster);
210 }
211}
212
213TEST(CORE, consistent_cluster) {
214 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
215 const cpuinfo_core* core = cpuinfo_get_core(i);
216 ASSERT_TRUE(core);
217 const cpuinfo_cluster* cluster = core->cluster;
218 ASSERT_TRUE(cluster);
219
220 EXPECT_GE(i, cluster->core_start);
221 EXPECT_LT(i, cluster->core_start + cluster->core_count);
222 }
223}
224
225TEST(CORE, valid_package) {
226 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
227 const cpuinfo_core* core = cpuinfo_get_core(i);
228 ASSERT_TRUE(core);
229
230 EXPECT_TRUE(core->package);
231 }
232}
233
Marat Dukhane8464012018-03-18 00:30:45 -0700234TEST(CORE, consistent_package) {
235 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
236 const cpuinfo_core* core = cpuinfo_get_core(i);
237 ASSERT_TRUE(core);
238 const cpuinfo_package* package = core->package;
239 ASSERT_TRUE(package);
240
241 EXPECT_GE(i, package->core_start);
242 EXPECT_LT(i, package->core_start + package->core_count);
243 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000244}
245
Marat Dukhane8464012018-03-18 00:30:45 -0700246TEST(CORE, known_vendor) {
247 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
248 const cpuinfo_core* core = cpuinfo_get_core(i);
249 ASSERT_TRUE(core);
250
251 EXPECT_NE(cpuinfo_vendor_unknown, core->vendor);
252 }
253}
254
255TEST(CORE, known_uarch) {
256 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
257 const cpuinfo_core* core = cpuinfo_get_core(i);
258 ASSERT_TRUE(core);
259
260 EXPECT_NE(cpuinfo_uarch_unknown, core->uarch);
261 }
262}
263
Marat Dukhan4d376c32018-03-18 11:36:39 -0700264TEST(CLUSTERS_COUNT, within_bounds) {
265 EXPECT_NE(0, cpuinfo_get_clusters_count());
266 EXPECT_LE(cpuinfo_get_clusters_count(), cpuinfo_get_cores_count());
267 EXPECT_LE(cpuinfo_get_clusters_count(), cpuinfo_get_processors_count());
268 EXPECT_GE(cpuinfo_get_clusters_count(), cpuinfo_get_packages_count());
269}
270
271TEST(CLUSTERS, non_null) {
272 EXPECT_TRUE(cpuinfo_get_clusters());
273}
274
275TEST(CLUSTER, non_null) {
276 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
277 EXPECT_TRUE(cpuinfo_get_cluster(i));
278 }
279}
280
281TEST(CLUSTER, non_zero_processors) {
282 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
283 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
284 ASSERT_TRUE(cluster);
285
286 EXPECT_NE(0, cluster->processor_count);
287 }
288}
289
290TEST(CLUSTER, valid_processors) {
291 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
292 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
293 ASSERT_TRUE(cluster);
294
295 EXPECT_LT(cluster->processor_start, cpuinfo_get_processors_count());
296 EXPECT_LE(cluster->processor_start + cluster->processor_count, cpuinfo_get_processors_count());
297 }
298}
299
300TEST(CLUSTER, consistent_processors) {
301 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
302 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
303 ASSERT_TRUE(cluster);
304
305 for (uint32_t j = 0; j < cluster->processor_count; j++) {
306 const cpuinfo_processor* processor = cpuinfo_get_processor(cluster->processor_start + j);
307 EXPECT_EQ(cluster, processor->cluster);
308 }
309 }
310}
311
312TEST(CLUSTER, non_zero_cores) {
313 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
314 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
315 ASSERT_TRUE(cluster);
316
317 EXPECT_NE(0, cluster->core_count);
318 }
319}
320
321TEST(CLUSTER, valid_cores) {
322 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
323 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
324 ASSERT_TRUE(cluster);
325
326 EXPECT_LT(cluster->core_start, cpuinfo_get_cores_count());
327 EXPECT_LE(cluster->core_start + cluster->core_count, cpuinfo_get_cores_count());
328 }
329}
330
331TEST(CLUSTER, consistent_cores) {
332 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
333 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
334 ASSERT_TRUE(cluster);
335
336 for (uint32_t j = 0; j < cluster->core_count; j++) {
337 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
338 ASSERT_TRUE(core);
339
340 EXPECT_EQ(cluster, core->cluster);
341 }
342 }
343}
344
345TEST(CLUSTER, valid_cluster_id) {
346 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
347 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
348 ASSERT_TRUE(cluster);
349
350 for (uint32_t j = 0; j < cluster->core_count; j++) {
351 const cpuinfo_package* package = cluster->package;
352 ASSERT_TRUE(package);
353
354 EXPECT_LT(cluster->cluster_id, package->cluster_count);
355 }
356 }
357}
358
359TEST(CLUSTER, valid_package) {
360 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
361 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
362 ASSERT_TRUE(cluster);
363
364 EXPECT_TRUE(cluster->package);
365 }
366}
367
368TEST(CLUSTER, consistent_package) {
369 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
370 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
371 ASSERT_TRUE(cluster);
372 const cpuinfo_package* package = cluster->package;
373 ASSERT_TRUE(package);
374
375 EXPECT_GE(i, package->cluster_start);
376 EXPECT_LT(i, package->cluster_start + package->cluster_count);
377 }
378}
379
380TEST(CLUSTER, consistent_vendor) {
381 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
382 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
383 ASSERT_TRUE(cluster);
384
385 for (uint32_t j = 0; j < cluster->core_count; j++) {
386 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
387 ASSERT_TRUE(core);
388
389 EXPECT_EQ(cluster->vendor, core->vendor);
390 }
391 }
392}
393
394TEST(CLUSTER, consistent_uarch) {
395 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
396 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
397 ASSERT_TRUE(cluster);
398
399 for (uint32_t j = 0; j < cluster->core_count; j++) {
400 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
401 ASSERT_TRUE(core);
402
403 EXPECT_EQ(cluster->uarch, core->uarch);
404 }
405 }
406}
407
408#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
409TEST(CLUSTER, consistent_cpuid) {
410 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
411 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
412 ASSERT_TRUE(cluster);
413
414 for (uint32_t j = 0; j < cluster->core_count; j++) {
415 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
416 ASSERT_TRUE(core);
417
418 EXPECT_EQ(cluster->cpuid, core->cpuid);
419 }
420 }
421}
422#endif /* CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 */
423
424#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
425TEST(CLUSTER, consistent_midr) {
426 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
427 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
428 ASSERT_TRUE(cluster);
429
430 for (uint32_t j = 0; j < cluster->core_count; j++) {
431 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
432 ASSERT_TRUE(core);
433
434 EXPECT_EQ(cluster->midr, core->midr);
435 }
436 }
437}
438#endif /* CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 */
439
440TEST(CLUSTER, consistent_frequency) {
441 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
442 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(i);
443 ASSERT_TRUE(cluster);
444
445 for (uint32_t j = 0; j < cluster->core_count; j++) {
446 const cpuinfo_core* core = cpuinfo_get_core(cluster->core_start + j);
447 ASSERT_TRUE(core);
448
449 EXPECT_EQ(cluster->frequency, core->frequency);
450 }
451 }
452}
453
Marat Dukhane8464012018-03-18 00:30:45 -0700454TEST(PACKAGES_COUNT, within_bounds) {
455 EXPECT_NE(0, cpuinfo_get_packages_count());
456 EXPECT_LE(cpuinfo_get_packages_count(), cpuinfo_get_cores_count());
457 EXPECT_LE(cpuinfo_get_packages_count(), cpuinfo_get_processors_count());
458}
459
460TEST(PACKAGES, non_null) {
461 EXPECT_TRUE(cpuinfo_get_packages());
462}
463
464TEST(PACKAGE, non_null) {
465 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
466 EXPECT_TRUE(cpuinfo_get_package(i));
467 }
468}
469
470TEST(PACKAGE, non_zero_processors) {
471 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
472 const cpuinfo_package* package = cpuinfo_get_package(i);
473 ASSERT_TRUE(package);
474
475 EXPECT_NE(0, package->processor_count);
476 }
477}
478
479TEST(PACKAGE, valid_processors) {
480 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
481 const cpuinfo_package* package = cpuinfo_get_package(i);
482 ASSERT_TRUE(package);
483
484 EXPECT_LT(package->processor_start, cpuinfo_get_processors_count());
485 EXPECT_LE(package->processor_start + package->processor_count, cpuinfo_get_processors_count());
486 }
487}
488
489TEST(PACKAGE, consistent_processors) {
490 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
491 const cpuinfo_package* package = cpuinfo_get_package(i);
492 ASSERT_TRUE(package);
493
494 for (uint32_t j = 0; j < package->processor_count; j++) {
495 const cpuinfo_processor* processor = cpuinfo_get_processor(package->processor_start + j);
Marat Dukhan4d376c32018-03-18 11:36:39 -0700496 ASSERT_TRUE(processor);
497
Marat Dukhane8464012018-03-18 00:30:45 -0700498 EXPECT_EQ(package, processor->package);
499 }
500 }
501}
502
503TEST(PACKAGE, non_zero_cores) {
504 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
505 const cpuinfo_package* package = cpuinfo_get_package(i);
506 ASSERT_TRUE(package);
507
Marat Dukhan4d376c32018-03-18 11:36:39 -0700508 EXPECT_NE(0, package->core_count);
Marat Dukhane8464012018-03-18 00:30:45 -0700509 }
510}
511
512TEST(PACKAGE, valid_cores) {
513 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
514 const cpuinfo_package* package = cpuinfo_get_package(i);
515 ASSERT_TRUE(package);
516
517 EXPECT_LT(package->core_start, cpuinfo_get_cores_count());
518 EXPECT_LE(package->core_start + package->core_count, cpuinfo_get_cores_count());
519 }
520}
521
522TEST(PACKAGE, consistent_cores) {
523 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
524 const cpuinfo_package* package = cpuinfo_get_package(i);
525 ASSERT_TRUE(package);
526
527 for (uint32_t j = 0; j < package->core_count; j++) {
528 const cpuinfo_core* core = cpuinfo_get_core(package->core_start + j);
Marat Dukhan4d376c32018-03-18 11:36:39 -0700529 ASSERT_TRUE(core);
530
Marat Dukhane8464012018-03-18 00:30:45 -0700531 EXPECT_EQ(package, core->package);
532 }
533 }
534}
535
Marat Dukhan4d376c32018-03-18 11:36:39 -0700536TEST(PACKAGE, non_zero_clusters) {
537 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
538 const cpuinfo_package* package = cpuinfo_get_package(i);
539 ASSERT_TRUE(package);
540
541 EXPECT_NE(0, package->cluster_count);
542 }
543}
544
545TEST(PACKAGE, valid_clusters) {
546 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
547 const cpuinfo_package* package = cpuinfo_get_package(i);
548 ASSERT_TRUE(package);
549
550 EXPECT_LT(package->cluster_start, cpuinfo_get_clusters_count());
551 EXPECT_LE(package->cluster_start + package->cluster_count, cpuinfo_get_clusters_count());
552 }
553}
554
555TEST(PACKAGE, consistent_cluster) {
556 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
557 const cpuinfo_package* package = cpuinfo_get_package(i);
558 ASSERT_TRUE(package);
559
560 for (uint32_t j = 0; j < package->cluster_count; j++) {
561 const cpuinfo_cluster* cluster = cpuinfo_get_cluster(package->cluster_start + j);
562 ASSERT_TRUE(cluster);
563
564 EXPECT_EQ(package, cluster->package);
565 }
566 }
567}
568
Marat Dukhane8464012018-03-18 00:30:45 -0700569TEST(L1I_CACHES_COUNT, within_bounds) {
570 EXPECT_NE(0, cpuinfo_get_l1i_caches_count());
571 EXPECT_LE(cpuinfo_get_l1i_caches_count(), cpuinfo_get_processors_count());
572}
573
574TEST(L1I_CACHES, non_null) {
575 EXPECT_TRUE(cpuinfo_get_l1i_caches());
576}
577
578TEST(L1I_CACHE, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700579 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700580 EXPECT_TRUE(cpuinfo_get_l1i_cache(i));
Marat Dukhan4f639922017-05-08 07:24:37 +0000581 }
582}
583
Marat Dukhane8464012018-03-18 00:30:45 -0700584TEST(L1I_CACHE, non_zero_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700585 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700586 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
587 ASSERT_TRUE(cache);
588
589 EXPECT_NE(0, cache->size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000590 }
591}
592
Marat Dukhane8464012018-03-18 00:30:45 -0700593TEST(L1I_CACHE, valid_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700594 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700595 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
596 ASSERT_TRUE(cache);
597
598 EXPECT_EQ(cache->size,
599 cache->associativity * cache->sets * cache->partitions * cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000600 }
601}
602
Marat Dukhane8464012018-03-18 00:30:45 -0700603TEST(L1I_CACHE, non_zero_associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700604 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700605 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
606 ASSERT_TRUE(cache);
607
608 EXPECT_NE(0, cache->associativity);
Marat Dukhan4f639922017-05-08 07:24:37 +0000609 }
610}
611
Marat Dukhane8464012018-03-18 00:30:45 -0700612TEST(L1I_CACHE, non_zero_partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700613 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700614 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
615 ASSERT_TRUE(cache);
616
617 EXPECT_NE(0, cache->partitions);
Marat Dukhan4f639922017-05-08 07:24:37 +0000618 }
619}
620
Marat Dukhane8464012018-03-18 00:30:45 -0700621TEST(L1I_CACHE, non_zero_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700622 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700623 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
624 ASSERT_TRUE(cache);
625
626 EXPECT_NE(0, cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000627 }
628}
629
Marat Dukhane8464012018-03-18 00:30:45 -0700630TEST(L1I_CACHE, power_of_2_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700631 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700632 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
633 ASSERT_TRUE(cache);
634
635 const uint32_t line_size = cache->line_size;
636 EXPECT_NE(0, line_size);
637 EXPECT_EQ(0, line_size & (line_size - 1));
Marat Dukhan4f639922017-05-08 07:24:37 +0000638 }
639}
640
Marat Dukhane8464012018-03-18 00:30:45 -0700641TEST(L1I_CACHE, reasonable_line_size) {
642 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
643 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
644 ASSERT_TRUE(cache);
645
646 EXPECT_GE(cache->line_size, 16);
647 EXPECT_LE(cache->line_size, 128);
648 }
649}
650
651TEST(L1I_CACHE, valid_flags) {
Marat Dukhan4f639922017-05-08 07:24:37 +0000652 const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING;
Marat Dukhan30401972017-09-26 18:35:52 -0700653 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700654 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
655 ASSERT_TRUE(cache);
656
657 EXPECT_EQ(0, cache->flags & ~valid_flags);
Marat Dukhan4f639922017-05-08 07:24:37 +0000658 }
659}
660
Marat Dukhane8464012018-03-18 00:30:45 -0700661TEST(L1I_CACHE, non_inclusive) {
Marat Dukhan30401972017-09-26 18:35:52 -0700662 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700663 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
664 ASSERT_TRUE(cache);
665
666 EXPECT_NE(CPUINFO_CACHE_INCLUSIVE, cache->flags & CPUINFO_CACHE_INCLUSIVE);
Marat Dukhan4f639922017-05-08 07:24:37 +0000667 }
668}
669
Marat Dukhane8464012018-03-18 00:30:45 -0700670TEST(L1I_CACHE, non_zero_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700671 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700672 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
673 ASSERT_TRUE(cache);
674
675 EXPECT_NE(0, cache->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +0000676 }
677}
678
Marat Dukhane8464012018-03-18 00:30:45 -0700679TEST(L1I_CACHE, valid_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700680 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700681 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
682 ASSERT_TRUE(cache);
683
684 EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count());
685 EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +0000686 }
687}
688
Marat Dukhane8464012018-03-18 00:30:45 -0700689TEST(L1I_CACHE, consistent_processors) {
690 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
691 const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i);
692 ASSERT_TRUE(cache);
693
694 for (uint32_t j = 0; j < cache->processor_count; j++) {
695 const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j);
696 ASSERT_TRUE(processor);
697
698 EXPECT_EQ(cache, processor->cache.l1i);
699 }
700 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000701}
702
Marat Dukhane8464012018-03-18 00:30:45 -0700703TEST(L1D_CACHES_COUNT, within_bounds) {
704 EXPECT_NE(0, cpuinfo_get_l1d_caches_count());
705 EXPECT_LE(cpuinfo_get_l1d_caches_count(), cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +0000706}
707
Marat Dukhane8464012018-03-18 00:30:45 -0700708TEST(L1D_CACHES, non_null) {
709 EXPECT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan4f639922017-05-08 07:24:37 +0000710}
711
Marat Dukhane8464012018-03-18 00:30:45 -0700712TEST(L1D_CACHE, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700713 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700714 EXPECT_TRUE(cpuinfo_get_l1d_cache(i));
Marat Dukhan4f639922017-05-08 07:24:37 +0000715 }
716}
717
Marat Dukhane8464012018-03-18 00:30:45 -0700718TEST(L1D_CACHE, non_zero_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700719 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700720 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
721 ASSERT_TRUE(cache);
722
723 EXPECT_NE(0, cache->size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000724 }
725}
726
Marat Dukhane8464012018-03-18 00:30:45 -0700727TEST(L1D_CACHE, valid_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700728 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700729 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
730 ASSERT_TRUE(cache);
731
732 EXPECT_EQ(cache->size,
733 cache->associativity * cache->sets * cache->partitions * cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000734 }
735}
736
Marat Dukhane8464012018-03-18 00:30:45 -0700737TEST(L1D_CACHE, non_zero_associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700738 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700739 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
740 ASSERT_TRUE(cache);
741
742 EXPECT_NE(0, cache->associativity);
Marat Dukhan4f639922017-05-08 07:24:37 +0000743 }
744}
745
Marat Dukhane8464012018-03-18 00:30:45 -0700746TEST(L1D_CACHE, non_zero_partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700747 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700748 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
749 ASSERT_TRUE(cache);
750
751 EXPECT_NE(0, cache->partitions);
Marat Dukhan4f639922017-05-08 07:24:37 +0000752 }
753}
754
Marat Dukhane8464012018-03-18 00:30:45 -0700755TEST(L1D_CACHE, non_zero_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700756 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700757 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
758 ASSERT_TRUE(cache);
759
760 EXPECT_NE(0, cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000761 }
762}
763
Marat Dukhane8464012018-03-18 00:30:45 -0700764TEST(L1D_CACHE, power_of_2_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700765 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700766 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
767 ASSERT_TRUE(cache);
768
769 const uint32_t line_size = cache->line_size;
770 EXPECT_NE(0, line_size);
771 EXPECT_EQ(0, line_size & (line_size - 1));
Marat Dukhan4f639922017-05-08 07:24:37 +0000772 }
773}
774
Marat Dukhane8464012018-03-18 00:30:45 -0700775TEST(L1D_CACHE, reasonable_line_size) {
776 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
777 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
778 ASSERT_TRUE(cache);
779
780 EXPECT_GE(cache->line_size, 16);
781 EXPECT_LE(cache->line_size, 128);
782 }
783}
784
785TEST(L1D_CACHE, valid_flags) {
Marat Dukhan4f639922017-05-08 07:24:37 +0000786 const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING;
Marat Dukhan30401972017-09-26 18:35:52 -0700787 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700788 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
789 ASSERT_TRUE(cache);
790
791 EXPECT_EQ(0, cache->flags & ~valid_flags);
Marat Dukhan4f639922017-05-08 07:24:37 +0000792 }
793}
794
Marat Dukhane8464012018-03-18 00:30:45 -0700795TEST(L1D_CACHE, non_inclusive) {
Marat Dukhan30401972017-09-26 18:35:52 -0700796 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700797 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
798 ASSERT_TRUE(cache);
799
800 EXPECT_NE(CPUINFO_CACHE_INCLUSIVE, cache->flags & CPUINFO_CACHE_INCLUSIVE);
Marat Dukhan4f639922017-05-08 07:24:37 +0000801 }
802}
803
Marat Dukhane8464012018-03-18 00:30:45 -0700804TEST(L1D_CACHE, non_zero_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700805 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700806 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
807 ASSERT_TRUE(cache);
808
809 EXPECT_NE(0, cache->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +0000810 }
811}
812
Marat Dukhane8464012018-03-18 00:30:45 -0700813TEST(L1D_CACHE, valid_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700814 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700815 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
816 ASSERT_TRUE(cache);
817
818 EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count());
819 EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +0000820 }
821}
822
Marat Dukhane8464012018-03-18 00:30:45 -0700823TEST(L1D_CACHE, consistent_processors) {
824 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
825 const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i);
826 ASSERT_TRUE(cache);
Marat Dukhan4f639922017-05-08 07:24:37 +0000827
Marat Dukhane8464012018-03-18 00:30:45 -0700828 for (uint32_t j = 0; j < cache->processor_count; j++) {
829 const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j);
830 ASSERT_TRUE(processor);
831
832 EXPECT_EQ(cache, processor->cache.l1d);
833 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000834 }
835}
836
Marat Dukhane8464012018-03-18 00:30:45 -0700837TEST(L2_CACHES_COUNT, within_bounds) {
838 EXPECT_NE(0, cpuinfo_get_l2_caches_count());
839 EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_processors_count());
840 EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_l1d_caches_count());
841 EXPECT_LE(cpuinfo_get_l2_caches_count(), cpuinfo_get_l1i_caches_count());
842}
843
844TEST(L2_CACHES, non_null) {
845 EXPECT_TRUE(cpuinfo_get_l2_caches());
846}
847
848TEST(L2_CACHE, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700849 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700850 EXPECT_TRUE(cpuinfo_get_l2_cache(i));
Marat Dukhan4f639922017-05-08 07:24:37 +0000851 }
852}
853
Marat Dukhane8464012018-03-18 00:30:45 -0700854TEST(L2_CACHE, non_zero_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700855 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700856 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
857 ASSERT_TRUE(cache);
858
859 EXPECT_NE(0, cache->size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000860 }
861}
862
Marat Dukhane8464012018-03-18 00:30:45 -0700863TEST(L2_CACHE, valid_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700864 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700865 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
866 ASSERT_TRUE(cache);
867
868 EXPECT_EQ(cache->size,
869 cache->associativity * cache->sets * cache->partitions * cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000870 }
871}
872
Marat Dukhane8464012018-03-18 00:30:45 -0700873TEST(L2_CACHE, non_zero_associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700874 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700875 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
876 ASSERT_TRUE(cache);
877
878 EXPECT_NE(0, cache->associativity);
Marat Dukhan4f639922017-05-08 07:24:37 +0000879 }
880}
881
Marat Dukhane8464012018-03-18 00:30:45 -0700882TEST(L2_CACHE, non_zero_partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700883 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700884 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
885 ASSERT_TRUE(cache);
886
887 EXPECT_NE(0, cache->partitions);
Marat Dukhan4f639922017-05-08 07:24:37 +0000888 }
889}
890
Marat Dukhane8464012018-03-18 00:30:45 -0700891TEST(L2_CACHE, non_zero_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700892 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700893 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
894 ASSERT_TRUE(cache);
895
896 EXPECT_NE(0, cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000897 }
898}
899
Marat Dukhane8464012018-03-18 00:30:45 -0700900TEST(L2_CACHE, power_of_2_line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700901 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700902 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
903 ASSERT_TRUE(cache);
904
905 const uint32_t line_size = cache->line_size;
906 EXPECT_NE(0, line_size);
907 EXPECT_EQ(0, line_size & (line_size - 1));
Marat Dukhan4f639922017-05-08 07:24:37 +0000908 }
909}
910
Marat Dukhane8464012018-03-18 00:30:45 -0700911TEST(L2_CACHE, reasonable_line_size) {
912 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
913 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
914 ASSERT_TRUE(cache);
915
916 EXPECT_GE(cache->line_size, 16);
917 EXPECT_LE(cache->line_size, 128);
918 }
919}
920
921TEST(L2_CACHE, valid_flags) {
Marat Dukhan4f639922017-05-08 07:24:37 +0000922 const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING;
Marat Dukhan30401972017-09-26 18:35:52 -0700923 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700924 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
925 ASSERT_TRUE(cache);
926
927 EXPECT_EQ(0, cache->flags & ~valid_flags);
Marat Dukhan4f639922017-05-08 07:24:37 +0000928 }
929}
930
Marat Dukhane8464012018-03-18 00:30:45 -0700931TEST(L2_CACHE, non_zero_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700932 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700933 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
934 ASSERT_TRUE(cache);
935
936 EXPECT_NE(0, cache->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +0000937 }
938}
939
Marat Dukhane8464012018-03-18 00:30:45 -0700940TEST(L2_CACHE, valid_processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700941 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
Marat Dukhane8464012018-03-18 00:30:45 -0700942 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
943 ASSERT_TRUE(cache);
944
945 EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count());
946 EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +0000947 }
948}
949
Marat Dukhane8464012018-03-18 00:30:45 -0700950TEST(L2_CACHE, consistent_processors) {
951 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
952 const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i);
953 ASSERT_TRUE(cache);
Marat Dukhan4f639922017-05-08 07:24:37 +0000954
Marat Dukhane8464012018-03-18 00:30:45 -0700955 for (uint32_t j = 0; j < cache->processor_count; j++) {
956 const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j);
957 ASSERT_TRUE(processor);
958
959 EXPECT_EQ(cache, processor->cache.l2);
960 }
Marat Dukhan4f639922017-05-08 07:24:37 +0000961 }
962}
963
Marat Dukhane8464012018-03-18 00:30:45 -0700964TEST(L3_CACHES_COUNT, within_bounds) {
965 EXPECT_LE(cpuinfo_get_l3_caches_count(), cpuinfo_get_processors_count());
966 EXPECT_LE(cpuinfo_get_l3_caches_count(), cpuinfo_get_l2_caches_count());
967}
968
969TEST(L3_CACHE, non_null) {
970 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
971 EXPECT_TRUE(cpuinfo_get_l3_cache(i));
Marat Dukhan4f639922017-05-08 07:24:37 +0000972 }
973}
974
Marat Dukhane8464012018-03-18 00:30:45 -0700975TEST(L3_CACHE, non_zero_size) {
976 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
977 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
978 ASSERT_TRUE(cache);
979
980 EXPECT_NE(0, cache->size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000981 }
982}
983
Marat Dukhane8464012018-03-18 00:30:45 -0700984TEST(L3_CACHE, valid_size) {
985 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
986 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
987 ASSERT_TRUE(cache);
988
989 EXPECT_EQ(cache->size,
990 cache->associativity * cache->sets * cache->partitions * cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +0000991 }
992}
993
Marat Dukhane8464012018-03-18 00:30:45 -0700994TEST(L3_CACHE, non_zero_associativity) {
995 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
996 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
997 ASSERT_TRUE(cache);
998
999 EXPECT_NE(0, cache->associativity);
Marat Dukhan4f639922017-05-08 07:24:37 +00001000 }
1001}
1002
Marat Dukhane8464012018-03-18 00:30:45 -07001003TEST(L3_CACHE, non_zero_partitions) {
1004 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1005 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1006 ASSERT_TRUE(cache);
1007
1008 EXPECT_NE(0, cache->partitions);
Marat Dukhan4f639922017-05-08 07:24:37 +00001009 }
1010}
1011
Marat Dukhane8464012018-03-18 00:30:45 -07001012TEST(L3_CACHE, non_zero_line_size) {
1013 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1014 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1015 ASSERT_TRUE(cache);
1016
1017 EXPECT_NE(0, cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +00001018 }
1019}
1020
Marat Dukhane8464012018-03-18 00:30:45 -07001021TEST(L3_CACHE, power_of_2_line_size) {
1022 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1023 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1024 ASSERT_TRUE(cache);
1025
1026 const uint32_t line_size = cache->line_size;
1027 EXPECT_NE(0, line_size);
1028 EXPECT_EQ(0, line_size & (line_size - 1));
Marat Dukhan4f639922017-05-08 07:24:37 +00001029 }
1030}
1031
Marat Dukhane8464012018-03-18 00:30:45 -07001032TEST(L3_CACHE, reasonable_line_size) {
1033 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1034 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1035 ASSERT_TRUE(cache);
1036
1037 EXPECT_GE(cache->line_size, 16);
1038 EXPECT_LE(cache->line_size, 128);
1039 }
1040}
1041
1042TEST(L3_CACHE, valid_flags) {
Marat Dukhan4f639922017-05-08 07:24:37 +00001043 const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING;
Marat Dukhane8464012018-03-18 00:30:45 -07001044 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1045 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1046 ASSERT_TRUE(cache);
1047
1048 EXPECT_EQ(0, cache->flags & ~valid_flags);
Marat Dukhan4f639922017-05-08 07:24:37 +00001049 }
1050}
1051
Marat Dukhane8464012018-03-18 00:30:45 -07001052TEST(L3_CACHE, non_zero_processors) {
1053 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1054 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1055 ASSERT_TRUE(cache);
1056
1057 EXPECT_NE(0, cache->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +00001058 }
1059}
1060
Marat Dukhane8464012018-03-18 00:30:45 -07001061TEST(L3_CACHE, valid_processors) {
1062 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1063 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1064 ASSERT_TRUE(cache);
1065
1066 EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count());
1067 EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count());
Marat Dukhan4f639922017-05-08 07:24:37 +00001068 }
1069}
1070
Marat Dukhane8464012018-03-18 00:30:45 -07001071TEST(L3_CACHE, consistent_processors) {
1072 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
1073 const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i);
1074 ASSERT_TRUE(cache);
Marat Dukhan4f639922017-05-08 07:24:37 +00001075
Marat Dukhane8464012018-03-18 00:30:45 -07001076 for (uint32_t j = 0; j < cache->processor_count; j++) {
1077 const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j);
1078 ASSERT_TRUE(processor);
1079
1080 EXPECT_EQ(cache, processor->cache.l3);
1081 }
Marat Dukhan4f639922017-05-08 07:24:37 +00001082 }
1083}
1084
Marat Dukhane8464012018-03-18 00:30:45 -07001085TEST(L4_CACHES_COUNT, within_bounds) {
1086 EXPECT_LE(cpuinfo_get_l4_caches_count(), cpuinfo_get_processors_count());
1087 EXPECT_LE(cpuinfo_get_l4_caches_count(), cpuinfo_get_l3_caches_count());
1088}
1089
1090TEST(L4_CACHE, non_null) {
1091 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1092 EXPECT_TRUE(cpuinfo_get_l4_cache(i));
Marat Dukhan4f639922017-05-08 07:24:37 +00001093 }
1094}
1095
Marat Dukhane8464012018-03-18 00:30:45 -07001096TEST(L4_CACHE, non_zero_size) {
1097 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1098 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1099 ASSERT_TRUE(cache);
1100
1101 EXPECT_NE(0, cache->size);
Marat Dukhan4f639922017-05-08 07:24:37 +00001102 }
1103}
1104
Marat Dukhane8464012018-03-18 00:30:45 -07001105TEST(L4_CACHE, valid_size) {
1106 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1107 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1108 ASSERT_TRUE(cache);
1109
1110 EXPECT_EQ(cache->size,
1111 cache->associativity * cache->sets * cache->partitions * cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +00001112 }
1113}
1114
Marat Dukhane8464012018-03-18 00:30:45 -07001115TEST(L4_CACHE, non_zero_associativity) {
1116 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1117 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1118 ASSERT_TRUE(cache);
1119
1120 EXPECT_NE(0, cache->associativity);
Marat Dukhan4f639922017-05-08 07:24:37 +00001121 }
1122}
1123
Marat Dukhane8464012018-03-18 00:30:45 -07001124TEST(L4_CACHE, non_zero_partitions) {
1125 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1126 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1127 ASSERT_TRUE(cache);
1128
1129 EXPECT_NE(0, cache->partitions);
Marat Dukhan4f639922017-05-08 07:24:37 +00001130 }
1131}
1132
Marat Dukhane8464012018-03-18 00:30:45 -07001133TEST(L4_CACHE, non_zero_line_size) {
1134 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1135 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1136 ASSERT_TRUE(cache);
1137
1138 EXPECT_NE(0, cache->line_size);
Marat Dukhan4f639922017-05-08 07:24:37 +00001139 }
1140}
1141
Marat Dukhane8464012018-03-18 00:30:45 -07001142TEST(L4_CACHE, power_of_2_line_size) {
1143 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1144 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1145 ASSERT_TRUE(cache);
1146
1147 const uint32_t line_size = cache->line_size;
1148 EXPECT_NE(0, line_size);
1149 EXPECT_EQ(0, line_size & (line_size - 1));
Marat Dukhan4f639922017-05-08 07:24:37 +00001150 }
1151}
1152
Marat Dukhane8464012018-03-18 00:30:45 -07001153TEST(L4_CACHE, reasonable_line_size) {
1154 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1155 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1156 ASSERT_TRUE(cache);
1157
1158 EXPECT_GE(cache->line_size, 16);
1159 EXPECT_LE(cache->line_size, 128);
1160 }
1161}
1162
1163TEST(L4_CACHE, valid_flags) {
Marat Dukhan4f639922017-05-08 07:24:37 +00001164 const uint32_t valid_flags = CPUINFO_CACHE_UNIFIED | CPUINFO_CACHE_INCLUSIVE | CPUINFO_CACHE_COMPLEX_INDEXING;
Marat Dukhane8464012018-03-18 00:30:45 -07001165 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1166 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1167 ASSERT_TRUE(cache);
1168
1169 EXPECT_EQ(0, cache->flags & ~valid_flags);
Marat Dukhan4f639922017-05-08 07:24:37 +00001170 }
1171}
1172
Marat Dukhane8464012018-03-18 00:30:45 -07001173TEST(L4_CACHE, non_zero_processors) {
1174 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1175 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1176 ASSERT_TRUE(cache);
1177
1178 EXPECT_NE(0, cache->processor_count);
Marat Dukhan4f639922017-05-08 07:24:37 +00001179 }
1180}
1181
Marat Dukhane8464012018-03-18 00:30:45 -07001182TEST(L4_CACHE, valid_processors) {
1183 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1184 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1185 ASSERT_TRUE(cache);
1186
1187 EXPECT_LT(cache->processor_start, cpuinfo_get_processors_count());
1188 EXPECT_LE(cache->processor_start + cache->processor_count, cpuinfo_get_processors_count());
1189 }
1190}
1191
1192TEST(L4_CACHE, consistent_processors) {
1193 for (uint32_t i = 0; i < cpuinfo_get_l4_caches_count(); i++) {
1194 const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i);
1195 ASSERT_TRUE(cache);
1196
1197 for (uint32_t j = 0; j < cache->processor_count; j++) {
1198 const cpuinfo_processor* processor = cpuinfo_get_processor(cache->processor_start + j);
1199 ASSERT_TRUE(processor);
1200
1201 EXPECT_EQ(cache, processor->cache.l4);
1202 }
Marat Dukhan4f639922017-05-08 07:24:37 +00001203 }
1204}
1205
1206int main(int argc, char* argv[]) {
1207 cpuinfo_initialize();
1208 ::testing::InitGoogleTest(&argc, argv);
1209 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -07001210}