Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 1 | #include <gtest/gtest.h> |
| 2 | |
| 3 | #include <cpuinfo.h> |
| 4 | #include <cpuinfo-mock.h> |
| 5 | |
| 6 | |
| 7 | TEST(PROCESSORS, count) { |
| 8 | ASSERT_EQ(2, cpuinfo_processors_count); |
| 9 | } |
| 10 | |
| 11 | TEST(PROCESSORS, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 12 | ASSERT_TRUE(cpuinfo_get_processors()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 13 | } |
| 14 | |
Marat Dukhan | 67d4b01 | 2017-08-28 11:06:35 -0700 | [diff] [blame] | 15 | TEST(PROCESSORS, vendor) { |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 16 | for (uint32_t i = 0; i < cpuinfo_processors_count; i++) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 17 | ASSERT_EQ(cpuinfo_vendor_cavium, cpuinfo_get_processors()[i].vendor); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 18 | } |
| 19 | } |
| 20 | |
Marat Dukhan | 67d4b01 | 2017-08-28 11:06:35 -0700 | [diff] [blame] | 21 | TEST(PROCESSORS, uarch) { |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 22 | for (uint32_t i = 0; i < cpuinfo_processors_count; i++) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 23 | ASSERT_EQ(cpuinfo_uarch_thunderx, cpuinfo_get_processors()[i].uarch); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 24 | } |
| 25 | } |
| 26 | |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 27 | TEST(ISA, thumb) { |
| 28 | ASSERT_TRUE(cpuinfo_isa.thumb); |
| 29 | } |
| 30 | |
| 31 | TEST(ISA, thumb2) { |
| 32 | ASSERT_TRUE(cpuinfo_isa.thumb2); |
| 33 | } |
| 34 | |
| 35 | TEST(ISA, thumbee) { |
| 36 | ASSERT_FALSE(cpuinfo_isa.thumbee); |
| 37 | } |
| 38 | |
| 39 | TEST(ISA, jazelle) { |
| 40 | ASSERT_FALSE(cpuinfo_isa.jazelle); |
| 41 | } |
| 42 | |
| 43 | TEST(ISA, armv5e) { |
| 44 | ASSERT_TRUE(cpuinfo_isa.armv5e); |
| 45 | } |
| 46 | |
| 47 | TEST(ISA, armv6) { |
| 48 | ASSERT_TRUE(cpuinfo_isa.armv6); |
| 49 | } |
| 50 | |
| 51 | TEST(ISA, armv6k) { |
| 52 | ASSERT_TRUE(cpuinfo_isa.armv6k); |
| 53 | } |
| 54 | |
| 55 | TEST(ISA, armv7) { |
| 56 | ASSERT_TRUE(cpuinfo_isa.armv7); |
| 57 | } |
| 58 | |
| 59 | TEST(ISA, armv7mp) { |
| 60 | ASSERT_TRUE(cpuinfo_isa.armv7mp); |
| 61 | } |
| 62 | |
| 63 | TEST(ISA, idiv) { |
| 64 | ASSERT_TRUE(cpuinfo_isa.idiv); |
| 65 | } |
| 66 | |
| 67 | TEST(ISA, vfpv2) { |
| 68 | ASSERT_FALSE(cpuinfo_isa.vfpv2); |
| 69 | } |
| 70 | |
| 71 | TEST(ISA, vfpv3) { |
| 72 | ASSERT_TRUE(cpuinfo_isa.vfpv3); |
| 73 | } |
| 74 | |
| 75 | TEST(ISA, d32) { |
| 76 | ASSERT_TRUE(cpuinfo_isa.d32); |
| 77 | } |
| 78 | |
| 79 | TEST(ISA, fp16) { |
| 80 | ASSERT_TRUE(cpuinfo_isa.fp16); |
| 81 | } |
| 82 | |
| 83 | TEST(ISA, fma) { |
| 84 | ASSERT_TRUE(cpuinfo_isa.fma); |
| 85 | } |
| 86 | |
| 87 | TEST(ISA, wmmx) { |
| 88 | ASSERT_FALSE(cpuinfo_isa.wmmx); |
| 89 | } |
| 90 | |
| 91 | TEST(ISA, wmmx2) { |
| 92 | ASSERT_FALSE(cpuinfo_isa.wmmx2); |
| 93 | } |
| 94 | |
| 95 | TEST(ISA, neon) { |
| 96 | ASSERT_TRUE(cpuinfo_isa.neon); |
| 97 | } |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 98 | |
| 99 | TEST(ISA, aes) { |
| 100 | ASSERT_TRUE(cpuinfo_isa.aes); |
| 101 | } |
| 102 | |
| 103 | TEST(ISA, sha1) { |
| 104 | ASSERT_TRUE(cpuinfo_isa.sha1); |
| 105 | } |
| 106 | |
| 107 | TEST(ISA, sha2) { |
| 108 | ASSERT_TRUE(cpuinfo_isa.sha2); |
| 109 | } |
| 110 | |
| 111 | TEST(ISA, pmull) { |
| 112 | ASSERT_TRUE(cpuinfo_isa.pmull); |
| 113 | } |
| 114 | |
| 115 | TEST(ISA, crc32) { |
| 116 | ASSERT_TRUE(cpuinfo_isa.crc32); |
| 117 | } |
| 118 | |
| 119 | #if CPUINFO_ARCH_ARM64 |
| 120 | TEST(ISA, atomics) { |
| 121 | ASSERT_TRUE(cpuinfo_isa.atomics); |
| 122 | } |
| 123 | |
| 124 | TEST(ISA, rdm) { |
| 125 | ASSERT_FALSE(cpuinfo_isa.rdm); |
| 126 | } |
| 127 | |
| 128 | TEST(ISA, fp16arith) { |
| 129 | ASSERT_FALSE(cpuinfo_isa.fp16arith); |
| 130 | } |
| 131 | |
| 132 | TEST(ISA, jscvt) { |
| 133 | ASSERT_FALSE(cpuinfo_isa.jscvt); |
| 134 | } |
| 135 | |
| 136 | TEST(ISA, fcma) { |
| 137 | ASSERT_FALSE(cpuinfo_isa.fcma); |
| 138 | } |
| 139 | #endif /* CPUINFO_ARCH_ARM64 */ |
| 140 | |
| 141 | TEST(L1I, count) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 142 | ASSERT_EQ(2, cpuinfo_get_l1i_caches_count()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | TEST(L1I, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 146 | ASSERT_TRUE(cpuinfo_get_l1i_caches()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | TEST(L1I, size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 150 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 151 | ASSERT_EQ(78 * 1024, cpuinfo_get_l1i_cache(i)->size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 152 | } |
| 153 | } |
| 154 | |
| 155 | TEST(L1I, associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 156 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 157 | ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 158 | } |
| 159 | } |
| 160 | |
| 161 | TEST(L1I, sets) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 162 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 163 | ASSERT_EQ(312, cpuinfo_get_l1i_cache(i)->sets); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 164 | } |
| 165 | } |
| 166 | |
| 167 | TEST(L1I, partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 168 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 169 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 170 | } |
| 171 | } |
| 172 | |
| 173 | TEST(L1I, line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 174 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 175 | ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
| 179 | TEST(L1I, flags) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 180 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 181 | ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 182 | } |
| 183 | } |
| 184 | |
| 185 | TEST(L1I, processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 186 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 187 | ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start); |
| 188 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 189 | } |
| 190 | } |
| 191 | |
| 192 | TEST(L1D, count) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 193 | ASSERT_EQ(2, cpuinfo_get_l1d_caches_count()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | TEST(L1D, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 197 | ASSERT_TRUE(cpuinfo_get_l1d_caches()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | TEST(L1D, size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 201 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 202 | ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 203 | } |
| 204 | } |
| 205 | |
| 206 | TEST(L1D, associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 207 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 208 | ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 209 | } |
| 210 | } |
| 211 | |
| 212 | TEST(L1D, sets) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 213 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 214 | ASSERT_EQ(128, cpuinfo_get_l1d_cache(i)->sets); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 215 | } |
| 216 | } |
| 217 | |
| 218 | TEST(L1D, partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 219 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 220 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 221 | } |
| 222 | } |
| 223 | |
| 224 | TEST(L1D, line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 225 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 226 | ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
| 230 | TEST(L1D, flags) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 231 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 232 | ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 233 | } |
| 234 | } |
| 235 | |
| 236 | TEST(L1D, processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 237 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 238 | ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start); |
| 239 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 240 | } |
| 241 | } |
| 242 | |
| 243 | TEST(L2, count) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 244 | ASSERT_EQ(1, cpuinfo_get_l2_caches_count()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | TEST(L2, non_null) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 248 | ASSERT_TRUE(cpuinfo_get_l2_caches()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | TEST(L2, size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 252 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 253 | ASSERT_EQ(16 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
| 257 | TEST(L2, associativity) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 258 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 259 | ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 260 | } |
| 261 | } |
| 262 | |
| 263 | TEST(L2, sets) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 264 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 265 | ASSERT_EQ(32768, cpuinfo_get_l2_cache(i)->sets); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 266 | } |
| 267 | } |
| 268 | |
| 269 | TEST(L2, partitions) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 270 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 271 | ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 272 | } |
| 273 | } |
| 274 | |
| 275 | TEST(L2, line_size) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 276 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 277 | ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 278 | } |
| 279 | } |
| 280 | |
| 281 | TEST(L2, flags) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 282 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 283 | ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 284 | } |
| 285 | } |
| 286 | |
| 287 | TEST(L2, processors) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 288 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 289 | ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start); |
| 290 | ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 291 | } |
| 292 | } |
| 293 | |
| 294 | TEST(L3, none) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 295 | ASSERT_EQ(0, cpuinfo_get_l3_caches_count()); |
| 296 | ASSERT_FALSE(cpuinfo_get_l3_caches()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | TEST(L4, none) { |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 300 | ASSERT_EQ(0, cpuinfo_get_l4_caches_count()); |
| 301 | ASSERT_FALSE(cpuinfo_get_l4_caches()); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 302 | } |
| 303 | |
Marat Dukhan | a70e55d | 2017-08-18 08:33:38 +0000 | [diff] [blame] | 304 | #include <scaleway.h> |
| 305 | |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 306 | int main(int argc, char* argv[]) { |
Marat Dukhan | a70e55d | 2017-08-18 08:33:38 +0000 | [diff] [blame] | 307 | cpuinfo_mock_filesystem(filesystem); |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 308 | cpuinfo_initialize(); |
| 309 | ::testing::InitGoogleTest(&argc, argv); |
| 310 | return RUN_ALL_TESTS(); |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 311 | } |