Marat Dukhan | a5fda23 | 2017-12-04 16:08:25 -0800 | [diff] [blame] | 1 | #include <gtest/gtest.h> |
| 2 | |
| 3 | #include <cpuinfo.h> |
| 4 | #include <cpuinfo-mock.h> |
| 5 | |
| 6 | |
| 7 | TEST(PROCESSORS, count) { |
| 8 | ASSERT_EQ(8, cpuinfo_get_processors_count()); |
| 9 | } |
| 10 | |
| 11 | TEST(PROCESSORS, non_null) { |
| 12 | ASSERT_TRUE(cpuinfo_get_processors()); |
| 13 | } |
| 14 | |
| 15 | TEST(PROCESSORS, smt_id) { |
| 16 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 17 | ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id); |
| 18 | } |
| 19 | } |
| 20 | |
| 21 | TEST(PROCESSORS, core) { |
| 22 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 23 | ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core); |
| 24 | } |
| 25 | } |
| 26 | |
| 27 | TEST(PROCESSORS, package) { |
| 28 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 29 | ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package); |
| 30 | } |
| 31 | } |
| 32 | |
| 33 | TEST(PROCESSORS, linux_id) { |
| 34 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 35 | switch (i) { |
| 36 | case 0: |
| 37 | case 1: |
| 38 | case 2: |
| 39 | case 3: |
| 40 | ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id); |
| 41 | break; |
| 42 | case 4: |
| 43 | case 5: |
| 44 | case 6: |
| 45 | case 7: |
| 46 | ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id); |
| 47 | break; |
| 48 | } |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | TEST(PROCESSORS, l1i) { |
| 53 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 54 | ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | TEST(PROCESSORS, l1d) { |
| 59 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 60 | ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d); |
| 61 | } |
| 62 | } |
| 63 | |
| 64 | TEST(PROCESSORS, l2) { |
| 65 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 66 | switch (i) { |
| 67 | case 0: |
| 68 | case 1: |
| 69 | case 2: |
| 70 | case 3: |
| 71 | ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2); |
| 72 | break; |
| 73 | case 4: |
| 74 | case 5: |
| 75 | case 6: |
| 76 | case 7: |
| 77 | ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2); |
| 78 | break; |
| 79 | } |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | TEST(PROCESSORS, l3) { |
| 84 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 85 | ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3); |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | TEST(PROCESSORS, l4) { |
| 90 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 91 | ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4); |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | TEST(CORES, count) { |
| 96 | ASSERT_EQ(8, cpuinfo_get_cores_count()); |
| 97 | } |
| 98 | |
| 99 | TEST(CORES, non_null) { |
| 100 | ASSERT_TRUE(cpuinfo_get_cores()); |
| 101 | } |
| 102 | |
| 103 | TEST(CORES, processor_start) { |
| 104 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 105 | ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start); |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | TEST(CORES, processor_count) { |
| 110 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 111 | ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | TEST(CORES, core_id) { |
| 116 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 117 | ASSERT_EQ(i, cpuinfo_get_core(i)->core_id); |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | TEST(CORES, package) { |
| 122 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 123 | ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | TEST(CORES, vendor) { |
| 128 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 129 | ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | TEST(CORES, uarch) { |
| 134 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 135 | ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | TEST(CORES, midr) { |
| 140 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 141 | ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr); |
| 142 | } |
| 143 | } |
| 144 | |
Marat Dukhan | 575a630 | 2018-03-10 14:38:49 -0800 | [diff] [blame^] | 145 | TEST(CORES, DISABLED_frequency) { |
| 146 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 147 | ASSERT_EQ(UINT64_C(2016000000), cpuinfo_get_core(i)->frequency); |
| 148 | } |
| 149 | } |
| 150 | |
Marat Dukhan | a5fda23 | 2017-12-04 16:08:25 -0800 | [diff] [blame] | 151 | TEST(PACKAGES, count) { |
| 152 | ASSERT_EQ(1, cpuinfo_get_packages_count()); |
| 153 | } |
| 154 | |
| 155 | TEST(PACKAGES, name) { |
| 156 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 157 | ASSERT_EQ("Qualcomm MSM8953", |
| 158 | std::string(cpuinfo_get_package(i)->name, |
| 159 | strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); |
| 160 | } |
| 161 | } |
| 162 | |
Marat Dukhan | fd0f3ef | 2017-12-18 17:45:18 -0800 | [diff] [blame] | 163 | TEST(PACKAGES, gpu_name) { |
| 164 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 165 | ASSERT_EQ("Qualcomm Adreno 506", |
| 166 | std::string(cpuinfo_get_package(i)->gpu_name, |
| 167 | strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX))); |
| 168 | } |
| 169 | } |
| 170 | |
Marat Dukhan | a5fda23 | 2017-12-04 16:08:25 -0800 | [diff] [blame] | 171 | TEST(PACKAGES, processor_start) { |
| 172 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 173 | ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | TEST(PACKAGES, processor_count) { |
| 178 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 179 | ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count); |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | TEST(PACKAGES, core_start) { |
| 184 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 185 | ASSERT_EQ(0, cpuinfo_get_package(i)->core_start); |
| 186 | } |
| 187 | } |
| 188 | |
| 189 | TEST(PACKAGES, core_count) { |
| 190 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 191 | ASSERT_EQ(8, cpuinfo_get_package(i)->core_count); |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | TEST(ISA, thumb) { |
| 196 | #if CPUINFO_ARCH_ARM |
| 197 | ASSERT_TRUE(cpuinfo_has_arm_thumb()); |
| 198 | #elif CPUINFO_ARCH_ARM64 |
| 199 | ASSERT_FALSE(cpuinfo_has_arm_thumb()); |
| 200 | #endif |
| 201 | } |
| 202 | |
| 203 | TEST(ISA, thumb2) { |
| 204 | #if CPUINFO_ARCH_ARM |
| 205 | ASSERT_TRUE(cpuinfo_has_arm_thumb2()); |
| 206 | #elif CPUINFO_ARCH_ARM64 |
| 207 | ASSERT_FALSE(cpuinfo_has_arm_thumb2()); |
| 208 | #endif |
| 209 | } |
| 210 | |
| 211 | TEST(ISA, armv5e) { |
| 212 | #if CPUINFO_ARCH_ARM |
| 213 | ASSERT_TRUE(cpuinfo_has_arm_v5e()); |
| 214 | #elif CPUINFO_ARCH_ARM64 |
| 215 | ASSERT_FALSE(cpuinfo_has_arm_v5e()); |
| 216 | #endif |
| 217 | } |
| 218 | |
| 219 | TEST(ISA, armv6) { |
| 220 | #if CPUINFO_ARCH_ARM |
| 221 | ASSERT_TRUE(cpuinfo_has_arm_v6()); |
| 222 | #elif CPUINFO_ARCH_ARM64 |
| 223 | ASSERT_FALSE(cpuinfo_has_arm_v6()); |
| 224 | #endif |
| 225 | } |
| 226 | |
| 227 | TEST(ISA, armv6k) { |
| 228 | #if CPUINFO_ARCH_ARM |
| 229 | ASSERT_TRUE(cpuinfo_has_arm_v6k()); |
| 230 | #elif CPUINFO_ARCH_ARM64 |
| 231 | ASSERT_FALSE(cpuinfo_has_arm_v6k()); |
| 232 | #endif |
| 233 | } |
| 234 | |
| 235 | TEST(ISA, armv7) { |
| 236 | #if CPUINFO_ARCH_ARM |
| 237 | ASSERT_TRUE(cpuinfo_has_arm_v7()); |
| 238 | #elif CPUINFO_ARCH_ARM64 |
| 239 | ASSERT_FALSE(cpuinfo_has_arm_v7()); |
| 240 | #endif |
| 241 | } |
| 242 | |
| 243 | TEST(ISA, armv7mp) { |
| 244 | #if CPUINFO_ARCH_ARM |
| 245 | ASSERT_TRUE(cpuinfo_has_arm_v7mp()); |
| 246 | #elif CPUINFO_ARCH_ARM64 |
| 247 | ASSERT_FALSE(cpuinfo_has_arm_v7mp()); |
| 248 | #endif |
| 249 | } |
| 250 | |
| 251 | TEST(ISA, idiv) { |
| 252 | ASSERT_TRUE(cpuinfo_has_arm_idiv()); |
| 253 | } |
| 254 | |
| 255 | TEST(ISA, vfpv2) { |
| 256 | ASSERT_FALSE(cpuinfo_has_arm_vfpv2()); |
| 257 | } |
| 258 | |
| 259 | TEST(ISA, vfpv3) { |
| 260 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3()); |
| 261 | } |
| 262 | |
| 263 | TEST(ISA, vfpv3_d32) { |
| 264 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32()); |
| 265 | } |
| 266 | |
| 267 | TEST(ISA, vfpv3_fp16) { |
| 268 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16()); |
| 269 | } |
| 270 | |
| 271 | TEST(ISA, vfpv3_fp16_d32) { |
| 272 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32()); |
| 273 | } |
| 274 | |
| 275 | TEST(ISA, vfpv4) { |
| 276 | ASSERT_TRUE(cpuinfo_has_arm_vfpv4()); |
| 277 | } |
| 278 | |
| 279 | TEST(ISA, vfpv4_d32) { |
| 280 | ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32()); |
| 281 | } |
| 282 | |
| 283 | TEST(ISA, wmmx) { |
| 284 | ASSERT_FALSE(cpuinfo_has_arm_wmmx()); |
| 285 | } |
| 286 | |
| 287 | TEST(ISA, wmmx2) { |
| 288 | ASSERT_FALSE(cpuinfo_has_arm_wmmx2()); |
| 289 | } |
| 290 | |
| 291 | TEST(ISA, neon) { |
| 292 | ASSERT_TRUE(cpuinfo_has_arm_neon()); |
| 293 | } |
| 294 | |
| 295 | TEST(ISA, neon_fp16) { |
| 296 | ASSERT_TRUE(cpuinfo_has_arm_neon_fp16()); |
| 297 | } |
| 298 | |
| 299 | TEST(ISA, neon_fma) { |
| 300 | ASSERT_TRUE(cpuinfo_has_arm_neon_fma()); |
| 301 | } |
| 302 | |
| 303 | TEST(ISA, atomics) { |
| 304 | ASSERT_FALSE(cpuinfo_has_arm_atomics()); |
| 305 | } |
| 306 | |
| 307 | TEST(ISA, neon_rdm) { |
| 308 | ASSERT_FALSE(cpuinfo_has_arm_neon_rdm()); |
| 309 | } |
| 310 | |
| 311 | TEST(ISA, fp16_arith) { |
| 312 | ASSERT_FALSE(cpuinfo_has_arm_fp16_arith()); |
| 313 | } |
| 314 | |
| 315 | TEST(ISA, jscvt) { |
| 316 | ASSERT_FALSE(cpuinfo_has_arm_jscvt()); |
| 317 | } |
| 318 | |
| 319 | TEST(ISA, fcma) { |
| 320 | ASSERT_FALSE(cpuinfo_has_arm_fcma()); |
| 321 | } |
| 322 | |
| 323 | TEST(ISA, aes) { |
| 324 | ASSERT_TRUE(cpuinfo_has_arm_aes()); |
| 325 | } |
| 326 | |
| 327 | TEST(ISA, sha1) { |
| 328 | ASSERT_TRUE(cpuinfo_has_arm_sha1()); |
| 329 | } |
| 330 | |
| 331 | TEST(ISA, sha2) { |
| 332 | ASSERT_TRUE(cpuinfo_has_arm_sha2()); |
| 333 | } |
| 334 | |
| 335 | TEST(ISA, pmull) { |
| 336 | ASSERT_TRUE(cpuinfo_has_arm_pmull()); |
| 337 | } |
| 338 | |
| 339 | TEST(ISA, crc32) { |
| 340 | ASSERT_TRUE(cpuinfo_has_arm_crc32()); |
| 341 | } |
| 342 | |
| 343 | TEST(L1I, count) { |
| 344 | ASSERT_EQ(8, cpuinfo_get_l1i_caches_count()); |
| 345 | } |
| 346 | |
| 347 | TEST(L1I, non_null) { |
| 348 | ASSERT_TRUE(cpuinfo_get_l1i_caches()); |
| 349 | } |
| 350 | |
| 351 | TEST(L1I, size) { |
| 352 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 353 | ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size); |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | TEST(L1I, associativity) { |
| 358 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 359 | ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity); |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | TEST(L1I, sets) { |
| 364 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 365 | ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, |
| 366 | cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | TEST(L1I, partitions) { |
| 371 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 372 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions); |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | TEST(L1I, line_size) { |
| 377 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 378 | ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size); |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | TEST(L1I, flags) { |
| 383 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 384 | ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags); |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | TEST(L1I, processors) { |
| 389 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 390 | ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start); |
| 391 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | TEST(L1D, count) { |
| 396 | ASSERT_EQ(8, cpuinfo_get_l1d_caches_count()); |
| 397 | } |
| 398 | |
| 399 | TEST(L1D, non_null) { |
| 400 | ASSERT_TRUE(cpuinfo_get_l1d_caches()); |
| 401 | } |
| 402 | |
| 403 | TEST(L1D, size) { |
| 404 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 405 | ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size); |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | TEST(L1D, associativity) { |
| 410 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 411 | ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | TEST(L1D, sets) { |
| 416 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 417 | ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, |
| 418 | cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); |
| 419 | } |
| 420 | } |
| 421 | |
| 422 | TEST(L1D, partitions) { |
| 423 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 424 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions); |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | TEST(L1D, line_size) { |
| 429 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 430 | ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size); |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | TEST(L1D, flags) { |
| 435 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 436 | ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags); |
| 437 | } |
| 438 | } |
| 439 | |
| 440 | TEST(L1D, processors) { |
| 441 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 442 | ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start); |
| 443 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count); |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | TEST(L2, count) { |
| 448 | ASSERT_EQ(2, cpuinfo_get_l2_caches_count()); |
| 449 | } |
| 450 | |
| 451 | TEST(L2, non_null) { |
| 452 | ASSERT_TRUE(cpuinfo_get_l2_caches()); |
| 453 | } |
| 454 | |
| 455 | TEST(L2, size) { |
| 456 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 457 | switch (i) { |
| 458 | case 0: |
| 459 | ASSERT_EQ(1024 * 1024, cpuinfo_get_l2_cache(i)->size); |
| 460 | break; |
| 461 | case 1: |
| 462 | ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size); |
| 463 | break; |
| 464 | } |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | TEST(L2, associativity) { |
| 469 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 470 | ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity); |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | TEST(L2, sets) { |
| 475 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 476 | ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, |
| 477 | cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | TEST(L2, partitions) { |
| 482 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 483 | ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions); |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | TEST(L2, line_size) { |
| 488 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 489 | ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size); |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | TEST(L2, flags) { |
| 494 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 495 | ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags); |
| 496 | } |
| 497 | } |
| 498 | |
| 499 | TEST(L2, processors) { |
| 500 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 501 | switch (i) { |
| 502 | case 0: |
| 503 | ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start); |
| 504 | ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count); |
| 505 | break; |
| 506 | case 1: |
| 507 | ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start); |
| 508 | ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count); |
| 509 | break; |
| 510 | } |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | TEST(L3, none) { |
| 515 | ASSERT_EQ(0, cpuinfo_get_l3_caches_count()); |
| 516 | ASSERT_FALSE(cpuinfo_get_l3_caches()); |
| 517 | } |
| 518 | |
| 519 | TEST(L4, none) { |
| 520 | ASSERT_EQ(0, cpuinfo_get_l4_caches_count()); |
| 521 | ASSERT_FALSE(cpuinfo_get_l4_caches()); |
| 522 | } |
| 523 | |
| 524 | #include <xiaomi-redmi-note-4.h> |
| 525 | |
| 526 | int main(int argc, char* argv[]) { |
| 527 | #if CPUINFO_ARCH_ARM |
| 528 | cpuinfo_set_hwcap(UINT32_C(0x0037B0D6)); |
| 529 | cpuinfo_set_hwcap2(UINT32_C(0x0000001F)); |
| 530 | #elif CPUINFO_ARCH_ARM64 |
| 531 | cpuinfo_set_hwcap(UINT32_C(0x000000FF)); |
| 532 | #endif |
| 533 | cpuinfo_mock_filesystem(filesystem); |
| 534 | #ifdef __ANDROID__ |
| 535 | cpuinfo_mock_android_properties(properties); |
Marat Dukhan | fd0f3ef | 2017-12-18 17:45:18 -0800 | [diff] [blame] | 536 | cpuinfo_mock_gl_renderer("Adreno (TM) 506"); |
Marat Dukhan | a5fda23 | 2017-12-04 16:08:25 -0800 | [diff] [blame] | 537 | #endif |
| 538 | cpuinfo_initialize(); |
| 539 | ::testing::InitGoogleTest(&argc, argv); |
| 540 | return RUN_ALL_TESTS(); |
| 541 | } |