blob: 41beabb8a1e9745a18e7146611e11e5f65b717a6 [file] [log] [blame]
Hao Lu922070c2017-10-18 16:29:02 -07001#include <stdio.h>
2#include <stdint.h>
3#include <stdlib.h>
4#include <string.h>
5#include <alloca.h>
6
7#include <errno.h>
8#include <sys/types.h>
9#include <sys/sysctl.h>
Hao Lu922070c2017-10-18 16:29:02 -070010#include <mach/machine.h>
11
12#include <cpuinfo.h>
13#include <mach/api.h>
Hao Lu3617d5b2017-10-23 15:16:50 -070014#include <gpu/api.h>
Hao Lu922070c2017-10-18 16:29:02 -070015#include <api.h>
16#include <log.h>
17
18
Marat Dukhanec862142017-10-18 17:24:46 -070019struct cpuinfo_arm_isa cpuinfo_isa = {
20#if CPUINFO_ARCH_ARM
21 .thumb = true,
22 .thumb2 = true,
23 .thumbee = false,
24 .jazelle = false,
25 .armv5e = true,
26 .armv6 = true,
27 .armv6k = true,
28 .armv7 = true,
29 .vfpv2 = false,
30 .vfpv3 = true,
31 .d32 = true,
32 .wmmx = false,
33 .wmmx2 = false,
34 .neon = true,
35#endif
36#if CPUINFO_ARCH_ARM64
37 .aes = true,
38 .sha1 = true,
39 .sha2 = true,
40 .pmull = true,
41 .crc32 = true,
42#endif
43};
Marat Dukhan7b738882017-10-18 16:59:28 -070044
Marat Dukhan7d52b052018-03-18 22:57:05 -070045static uint32_t get_sys_info(int type_specifier, const char* name) {
Hao Lu922070c2017-10-18 16:29:02 -070046 size_t size = 0;
47 uint32_t result = 0;
48 int mib[2] = { CTL_HW, type_specifier };
49 if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) {
50 cpuinfo_log_error("sysctl(\"%s\") failed: %s", name, strerror(errno));
51 } else if (size == sizeof(uint32_t)) {
52 sysctl(mib, 2, &result, &size, NULL, 0);
53 cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", name, result, size);
54 } else {
55 cpuinfo_log_warning("sysctl does not support non-integer lookup for (\"%s\")", name);
56 }
57 return result;
58}
59
Marat Dukhan7d52b052018-03-18 22:57:05 -070060static uint64_t get_sys_info_by_name(const char* type_specifier) {
Hao Lu922070c2017-10-18 16:29:02 -070061 size_t size = 0;
62 uint32_t result = 0;
63 if (sysctlbyname(type_specifier, NULL, &size, NULL, 0) != 0) {
64 cpuinfo_log_error("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno));
65 } else if (size == sizeof(uint32_t)) {
66 sysctlbyname(type_specifier, &result, &size, NULL, 0);
67 cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", type_specifier, result, size);
68 } else {
69 cpuinfo_log_warning("sysctl does not support non-integer lookup for (\"%s\")", type_specifier);
70 }
71 return result;
72}
73
74static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t cpu_subtype, uint32_t core_index) {
75 switch (cpu_family) {
76 case CPUFAMILY_ARM_SWIFT:
77 return cpuinfo_uarch_swift;
78 case CPUFAMILY_ARM_CYCLONE:
79 return cpuinfo_uarch_cyclone;
80 case CPUFAMILY_ARM_TYPHOON:
81 return cpuinfo_uarch_typhoon;
82 case CPUFAMILY_ARM_TWISTER:
83 return cpuinfo_uarch_twister;
84 case CPUFAMILY_ARM_HURRICANE:
85 return cpuinfo_uarch_hurricane;
Marat Dukhan7b738882017-10-18 16:59:28 -070086#ifdef CPUFAMILY_ARM_MONSOON_MISTRAL
Hao Lu922070c2017-10-18 16:29:02 -070087 case CPUFAMILY_ARM_MONSOON_MISTRAL:
Marat Dukhan7b738882017-10-18 16:59:28 -070088#else
89 case 0xe81e7ef6:
90 /* Hard-coded value for older SDKs which do not define CPUFAMILY_ARM_MONSOON_MISTRAL */
91#endif
Hao Lu922070c2017-10-18 16:29:02 -070092 /* 2x Monsoon + 4x Mistral cores */
93 return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral;
94 default:
95 /* Use hw.cpusubtype for detection */
96 break;
97 }
98
99 switch (cpu_subtype) {
100 case CPU_SUBTYPE_ARM_V7:
101 return cpuinfo_uarch_cortex_a8;
102 case CPU_SUBTYPE_ARM_V7F:
103 return cpuinfo_uarch_cortex_a9;
104 case CPU_SUBTYPE_ARM_V7K:
105 return cpuinfo_uarch_cortex_a7;
106 default:
107 return cpuinfo_uarch_unknown;
108 }
109}
110
111static void decode_package_name(char* package_name) {
112 size_t size;
113 if (sysctlbyname("hw.machine", NULL, &size, NULL, 0) != 0) {
114 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
115 return;
116 }
117
118 char *machine_name = alloca(size);
119 if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) {
120 cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
121 return;
122 }
123 cpuinfo_log_debug("hw.machine: %s", machine_name);
Hao Lu8c2a3832018-07-23 23:12:11 -0700124
Hao Lu922070c2017-10-18 16:29:02 -0700125 char name[10];
126 uint32_t major = 0, minor = 0;
127 if (sscanf(machine_name, "%9[^,0123456789]%"SCNu32",%"SCNu32, name, &major, &minor) != 3) {
128 cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno));
129 return;
130 }
Hao Lu8c2a3832018-07-23 23:12:11 -0700131
Hao Lu922070c2017-10-18 16:29:02 -0700132 uint32_t chip_model = 0;
133 char suffix = '\0';
134 if (strcmp(name, "iPhone") == 0) {
135 /*
136 * iPhone 4 and up are supported:
137 * - iPhone 4 [A4]: iPhone3,1, iPhone3,2, iPhone3,3
138 * - iPhone 4S [A5]: iPhone4,1
139 * - iPhone 5 [A6]: iPhone5,1, iPhone5,2
140 * - iPhone 5c [A6]: iPhone5,3, iPhone5,4
141 * - iPhone 5s [A7]: iPhone6,1, iPhone6,2
142 * - iPhone 6 [A8]: iPhone7,2
143 * - iPhone 6 Plus [A8]: iPhone7,1
144 * - iPhone 6s [A9]: iPhone8,1
145 * - iPhone 6s Plus [A9]: iPhone8,2
146 * - iPhone SE [A9]: iPhone8,4
147 * - iPhone 7 [A10]: iPhone9,1, iPhone9,3
148 * - iPhone 7 Plus [A10]: iPhone9,2, iPhone9,4
149 * - iPhone 8 [A11]: iPhone10,1, iPhone10,4
150 * - iPhone 8 Plus [A11]: iPhone10,2, iPhone10,5
151 * - iPhone X [A11]: iPhone10,3, iPhone10,6
152 */
153 chip_model = major + 1;
154 } else if (strcmp(name, "iPad") == 0) {
155 switch (major) {
156 /* iPad 2 and up are supported */
157 case 2:
158 /*
159 * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, iPad2,4
160 * iPad mini [A5]: iPad2,5, iPad2,6, iPad2,7
161 */
162 chip_model = major + 3;
163 break;
164 case 3:
165 /*
166 * iPad 3rd Gen [A5X]: iPad3,1, iPad3,2, iPad3,3
167 * iPad 4th Gen [A6X]: iPad3,4, iPad3,5, iPad3,6
168 */
169 chip_model = (minor <= 3) ? 5 : 6;
170 suffix = 'X';
171 break;
172 case 4:
173 /*
174 * iPad Air [A7]: iPad4,1, iPad4,2, iPad4,3
175 * iPad mini Retina [A7]: iPad4,4, iPad4,5, iPad4,6
176 * iPad mini 3 [A7]: iPad4,7, iPad4,8, iPad4,9
177 */
178 chip_model = major + 3;
179 break;
180 case 5:
181 /*
182 * iPad mini 4 [A8]: iPad5,1, iPad5,2
183 * iPad Air 2 [A8X]: iPad5,3, iPad5,4
184 */
185 chip_model = major + 3;
186 suffix = (minor <= 2) ? '\0' : 'X';
187 break;
188 case 6:
189 /*
190 * iPad Pro 9.7" [A9X]: iPad6,3, iPad6,4
191 * iPad Pro [A9X]: iPad6,7, iPad6,8
192 * iPad 5th Gen [A9]: iPad6,11, iPad6,12
193 */
194 chip_model = major + 3;
195 suffix = minor <= 8 ? 'X' : '\0';
196 break;
197 case 7:
198 /*
199 * iPad Pro 12.9" [A10X]: iPad7,1, iPad7,2
200 * iPad Pro 10.5" [A10X]: iPad7,3, iPad7,4
201 */
202 chip_model = major + 3;
203 suffix = 'X';
204 break;
205 default:
206 cpuinfo_log_info("unknown iPad: %s", machine_name);
207 break;
208 }
209 } else if (strcmp(name, "iPod") == 0) {
210 switch (major) {
211 case 5:
212 chip_model = 5;
213 break;
214 /* iPod touch (5th Gen) [A5]: iPod5,1 */
215 case 7:
216 /* iPod touch (6th Gen, 2015) [A8]: iPod7,1 */
217 chip_model = 8;
218 break;
219 default:
220 cpuinfo_log_info("unknown iPod: %s", machine_name);
221 break;
222 }
223 } else {
224 cpuinfo_log_info("unknown device: %s", machine_name);
225 }
226 if (chip_model != 0) {
227 snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%"PRIu32"%c", chip_model, suffix);
228 }
229}
230
231void cpuinfo_arm_mach_init(void) {
232 struct cpuinfo_processor* processors = NULL;
233 struct cpuinfo_core* cores = NULL;
Hao Lu8c2a3832018-07-23 23:12:11 -0700234 struct cpuinfo_cluster* clusters = NULL;
Hao Lu922070c2017-10-18 16:29:02 -0700235 struct cpuinfo_package* packages = NULL;
236 struct cpuinfo_cache* l1i = NULL;
237 struct cpuinfo_cache* l1d = NULL;
238 struct cpuinfo_cache* l2 = NULL;
239 struct cpuinfo_cache* l3 = NULL;
240
241 struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology();
242 processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor));
243 if (processors == NULL) {
244 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors",
245 mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads);
246 goto cleanup;
247 }
248 cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core));
249 if (cores == NULL) {
250 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores",
251 mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores);
252 goto cleanup;
253 }
254 packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package));
255 if (packages == NULL) {
256 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" packages",
257 mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages);
258 goto cleanup;
259 }
260
261 const uint32_t threads_per_core = mach_topology.threads / mach_topology.cores;
262 const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages;
263 const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages;
Hao Lu8c2a3832018-07-23 23:12:11 -0700264
Hao Lu922070c2017-10-18 16:29:02 -0700265 for (uint32_t i = 0; i < mach_topology.packages; i++) {
266 packages[i] = (struct cpuinfo_package) {
267 .processor_start = i * threads_per_package,
268 .processor_count = threads_per_package,
269 .core_start = i * cores_per_package,
270 .core_count = cores_per_package,
271 };
272 decode_package_name(packages[i].name);
Hao Lu3617d5b2017-10-23 15:16:50 -0700273 cpuinfo_gpu_ios_query_gles2(packages[i].gpu_name);
Hao Lu922070c2017-10-18 16:29:02 -0700274 }
Marat Dukhanec862142017-10-18 17:24:46 -0700275
276
Hao Lu922070c2017-10-18 16:29:02 -0700277 const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
Marat Dukhanec862142017-10-18 17:24:46 -0700278 const uint32_t cpu_type = get_sys_info_by_name("hw.cputype");
Hao Lu922070c2017-10-18 16:29:02 -0700279 const uint32_t cpu_subtype = get_sys_info_by_name("hw.cpusubtype");
Marat Dukhanec862142017-10-18 17:24:46 -0700280 switch (cpu_type) {
281 case CPU_TYPE_ARM64:
282 cpuinfo_isa.aes = true;
283 cpuinfo_isa.sha1 = true;
284 cpuinfo_isa.sha2 = true;
285 cpuinfo_isa.pmull = true;
286 cpuinfo_isa.crc32 = true;
287 break;
288#if CPUINFO_ARCH_ARM
289 case CPU_TYPE_ARM:
290 switch (cpu_subtype) {
291 case CPU_SUBTYPE_ARM_V8:
292 cpuinfo_isa.aes = true;
293 cpuinfo_isa.sha1 = true;
294 cpuinfo_isa.sha2 = true;
295 cpuinfo_isa.pmull = true;
296 cpuinfo_isa.crc32 = true;
297 /* Fall-through to add ARMv7S features */
298 case CPU_SUBTYPE_ARM_V7S:
299 case CPU_SUBTYPE_ARM_V7K:
300 cpuinfo_isa.fma = true;
301 /* Fall-through to add ARMv7F features */
302 case CPU_SUBTYPE_ARM_V7F:
303 cpuinfo_isa.armv7mp = true;
304 cpuinfo_isa.fp16 = true;
305 /* Fall-through to add ARMv7 features */
306 case CPU_SUBTYPE_ARM_V7:
307 break;
308 default:
309 break;
310 }
311 break;
312#endif
313 }
314
Hao Lu8c2a3832018-07-23 23:12:11 -0700315 uint32_t num_clusters = 1;
Hao Lu922070c2017-10-18 16:29:02 -0700316 for (uint32_t i = 0; i < mach_topology.cores; i++) {
317 cores[i] = (struct cpuinfo_core) {
318 .processor_start = i * threads_per_core,
319 .processor_count = threads_per_core,
320 .core_id = i % cores_per_package,
321 .package = packages + i / cores_per_package,
322 .vendor = cpuinfo_vendor_apple,
323 .uarch = decode_uarch(cpu_family, cpu_subtype, i),
324 };
Hao Lu8c2a3832018-07-23 23:12:11 -0700325 if (i != 0 && cores[i].uarch != cores[i - 1].uarch) {
326 num_clusters++;
327 }
Hao Lu922070c2017-10-18 16:29:02 -0700328 }
329 for (uint32_t i = 0; i < mach_topology.threads; i++) {
330 const uint32_t smt_id = i % threads_per_core;
331 const uint32_t core_id = i / threads_per_core;
332 const uint32_t package_id = i / threads_per_package;
333
334 processors[i].smt_id = smt_id;
Marat Dukhan7fcd4412017-11-30 09:46:49 -0800335 processors[i].core = &cores[core_id];
336 processors[i].package = &packages[package_id];
Hao Lu922070c2017-10-18 16:29:02 -0700337 }
338
Hao Lu8c2a3832018-07-23 23:12:11 -0700339 clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster));
340 if (clusters == NULL) {
341 cpuinfo_log_error(
342 "failed to allocate %zu bytes for descriptions of %"PRIu32" clusters",
343 num_clusters * sizeof(struct cpuinfo_cluster), num_clusters);
344 goto cleanup;
345 }
346 uint32_t cluster_idx = UINT32_MAX;
347 for (uint32_t i = 0; i < mach_topology.cores; i++) {
348 if (i == 0 || cores[i].uarch != cores[i - 1].uarch) {
349 cluster_idx++;
350 clusters[cluster_idx] = (struct cpuinfo_cluster) {
351 .processor_start = i * threads_per_core,
352 .processor_count = 1,
353 .core_start = i,
354 .core_count = 1,
355 .cluster_id = cluster_idx,
356 .package = cores[i].package,
357 .vendor = cores[i].vendor,
358 .uarch = cores[i].uarch,
359 };
360 } else {
361 clusters[cluster_idx].processor_count++;
362 clusters[cluster_idx].core_count++;
363 }
364 cores[i].cluster = &clusters[cluster_idx];
365 }
366
367 for (uint32_t i = 0; i < mach_topology.threads; i++) {
368 const uint32_t core_id = i / threads_per_core;
369 processors[i].cluster = cores[core_id].cluster;
370 }
371
372 for (uint32_t i = 0; i < mach_topology.packages; i++) {
373 packages[i].cluster_start = 0;
374 packages[i].cluster_count = num_clusters;
375 }
376
Hao Lu922070c2017-10-18 16:29:02 -0700377 const uint32_t cacheline_size = get_sys_info(HW_CACHELINE, "HW_CACHELINE");
378 const uint32_t l1d_cache_size = get_sys_info(HW_L1DCACHESIZE, "HW_L1DCACHESIZE");
379 const uint32_t l1i_cache_size = get_sys_info(HW_L1ICACHESIZE, "HW_L1ICACHESIZE");
380 const uint32_t l2_cache_size = get_sys_info(HW_L2CACHESIZE, "HW_L2CACHESIZE");
381 const uint32_t l3_cache_size = get_sys_info(HW_L3CACHESIZE, "HW_L3CACHESIZE");
382 const uint32_t l1_cache_associativity = 4;
383 const uint32_t l2_cache_associativity = 8;
384 const uint32_t l3_cache_associativity = 16;
385 const uint32_t cache_partitions = 1;
386 const uint32_t cache_flags = 0;
387
388 uint32_t threads_per_l1 = 0, l1_count = 0;
389 if (l1i_cache_size != 0 || l1d_cache_size != 0) {
Hao Lu3617d5b2017-10-23 15:16:50 -0700390 /* Assume L1 caches are private to each core */
Hao Lu922070c2017-10-18 16:29:02 -0700391 threads_per_l1 = 1;
392 l1_count = mach_topology.threads / threads_per_l1;
393 cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count);
394 }
395
396 uint32_t threads_per_l2 = 0, l2_count = 0;
397 if (l2_cache_size != 0) {
Hao Lu3617d5b2017-10-23 15:16:50 -0700398 /* Assume L2 cache is shared between all cores */
Hao Lu922070c2017-10-18 16:29:02 -0700399 threads_per_l2 = mach_topology.cores;
400 l2_count = 1;
401 cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count);
402 }
Hao Lu8c2a3832018-07-23 23:12:11 -0700403
Hao Lu922070c2017-10-18 16:29:02 -0700404 uint32_t threads_per_l3 = 0, l3_count = 0;
405 if (l3_cache_size != 0) {
Hao Lu3617d5b2017-10-23 15:16:50 -0700406 /* Assume L3 cache is shared between all cores */
Hao Lu922070c2017-10-18 16:29:02 -0700407 threads_per_l3 = mach_topology.cores;
408 l3_count = 1;
409 cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count);
410 }
411
412 if (l1i_cache_size != 0) {
413 l1i = calloc(l1_count, sizeof(struct cpuinfo_cache));
414 if (l1i == NULL) {
415 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches",
416 l1_count * sizeof(struct cpuinfo_cache), l1_count);
417 goto cleanup;
418 }
419 for (uint32_t c = 0; c < l1_count; c++) {
420 l1i[c] = (struct cpuinfo_cache) {
421 .size = l1i_cache_size,
422 .associativity = l1_cache_associativity,
423 .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size),
424 .partitions = cache_partitions,
425 .line_size = cacheline_size,
426 .flags = cache_flags,
427 .processor_start = c * threads_per_l1,
428 .processor_count = threads_per_l1,
429 };
430 }
431 for (uint32_t t = 0; t < mach_topology.threads; t++) {
432 processors[t].cache.l1i = &l1i[t / threads_per_l1];
433 }
434 }
435
436 if (l1d_cache_size != 0) {
437 l1d = calloc(l1_count, sizeof(struct cpuinfo_cache));
438 if (l1d == NULL) {
439 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches",
440 l1_count * sizeof(struct cpuinfo_cache), l1_count);
441 goto cleanup;
442 }
443 for (uint32_t c = 0; c < l1_count; c++) {
444 l1d[c] = (struct cpuinfo_cache) {
445 .size = l1d_cache_size,
446 .associativity = l1_cache_associativity,
447 .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size),
448 .partitions = cache_partitions,
449 .line_size = cacheline_size,
450 .flags = cache_flags,
451 .processor_start = c * threads_per_l1,
452 .processor_count = threads_per_l1,
453 };
454 }
455 for (uint32_t t = 0; t < mach_topology.threads; t++) {
456 processors[t].cache.l1d = &l1d[t / threads_per_l1];
457 }
458 }
459
460 if (l2_count != 0) {
461 l2 = calloc(l2_count, sizeof(struct cpuinfo_cache));
462 if (l2 == NULL) {
463 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches",
464 l2_count * sizeof(struct cpuinfo_cache), l2_count);
465 goto cleanup;
466 }
467 for (uint32_t c = 0; c < l2_count; c++) {
468 l2[c] = (struct cpuinfo_cache) {
469 .size = l2_cache_size,
470 .associativity = l2_cache_associativity,
471 .sets = l2_cache_size / (l2_cache_associativity * cacheline_size),
472 .partitions = cache_partitions,
473 .line_size = cacheline_size,
474 .flags = cache_flags,
475 .processor_start = c * threads_per_l2,
476 .processor_count = threads_per_l2,
477 };
478 }
479 for (uint32_t t = 0; t < mach_topology.threads; t++) {
480 processors[t].cache.l2 = &l2[0];
481 }
482 }
Hao Lu8c2a3832018-07-23 23:12:11 -0700483
Hao Lu922070c2017-10-18 16:29:02 -0700484 if (l3_count != 0) {
485 l3 = calloc(l3_count, sizeof(struct cpuinfo_cache));
486 if (l3 == NULL) {
487 cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches",
488 l3_count * sizeof(struct cpuinfo_cache), l3_count);
489 goto cleanup;
490 }
491 for (uint32_t c = 0; c < l3_count; c++) {
492 l3[c] = (struct cpuinfo_cache) {
493 .size = l3_cache_size,
494 .associativity = l3_cache_associativity,
495 .sets = l3_cache_size / (l3_cache_associativity * cacheline_size),
496 .partitions = cache_partitions,
497 .line_size = cacheline_size,
498 .flags = cache_flags,
499 .processor_start = c * threads_per_l3,
500 .processor_count = threads_per_l3,
501 };
502 }
503 for (uint32_t t = 0; t < mach_topology.threads; t++) {
504 processors[t].cache.l3 = &l3[0];
505 }
506 }
507
508 /* Commit changes */
509 cpuinfo_cache[cpuinfo_cache_level_1i] = l1i;
510 cpuinfo_cache[cpuinfo_cache_level_1d] = l1d;
511 cpuinfo_cache[cpuinfo_cache_level_2] = l2;
512 cpuinfo_cache[cpuinfo_cache_level_3] = l3;
513
514 cpuinfo_processors = processors;
515 cpuinfo_cores = cores;
Hao Lu8c2a3832018-07-23 23:12:11 -0700516 cpuinfo_clusters = clusters;
Hao Lu922070c2017-10-18 16:29:02 -0700517 cpuinfo_packages = packages;
518
519 cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count;
520 cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count;
521 cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count;
522 cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count;
523
524 cpuinfo_processors_count = mach_topology.threads;
525 cpuinfo_cores_count = mach_topology.cores;
Hao Lu8c2a3832018-07-23 23:12:11 -0700526 cpuinfo_clusters_count = num_clusters;
Hao Lu922070c2017-10-18 16:29:02 -0700527 cpuinfo_packages_count = mach_topology.packages;
528
Marat Dukhancf70aee2018-03-24 23:21:02 -0700529 __sync_synchronize();
530
531 cpuinfo_is_initialized = true;
532
Hao Lu922070c2017-10-18 16:29:02 -0700533 processors = NULL;
534 cores = NULL;
Hao Lu8c2a3832018-07-23 23:12:11 -0700535 clusters = NULL;
Hao Lu922070c2017-10-18 16:29:02 -0700536 packages = NULL;
537 l1i = l1d = l2 = l3 = NULL;
538
539cleanup:
540 free(processors);
541 free(cores);
Hao Lu8c2a3832018-07-23 23:12:11 -0700542 free(clusters);
Hao Lu922070c2017-10-18 16:29:02 -0700543 free(packages);
544 free(l1i);
545 free(l1d);
546 free(l2);
547 free(l3);
548}