Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 1 | #include <gtest/gtest.h> |
| 2 | |
| 3 | #include <cpuinfo.h> |
| 4 | #include <cpuinfo-mock.h> |
| 5 | |
| 6 | |
| 7 | TEST(PROCESSORS, count) { |
| 8 | ASSERT_EQ(8, cpuinfo_get_processors_count()); |
| 9 | } |
| 10 | |
| 11 | TEST(PROCESSORS, non_null) { |
| 12 | ASSERT_TRUE(cpuinfo_get_processors()); |
| 13 | } |
| 14 | |
| 15 | TEST(PROCESSORS, smt_id) { |
| 16 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 17 | ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id); |
| 18 | } |
| 19 | } |
| 20 | |
| 21 | TEST(PROCESSORS, core) { |
| 22 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 23 | ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core); |
| 24 | } |
| 25 | } |
| 26 | |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 27 | TEST(PROCESSORS, cluster) { |
| 28 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 29 | switch (i) { |
| 30 | case 0: |
| 31 | case 1: |
| 32 | case 2: |
| 33 | case 3: |
| 34 | ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster); |
| 35 | break; |
| 36 | case 4: |
| 37 | case 5: |
| 38 | case 6: |
| 39 | case 7: |
| 40 | ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster); |
| 41 | break; |
| 42 | } |
| 43 | } |
| 44 | } |
| 45 | |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 46 | TEST(PROCESSORS, package) { |
| 47 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 48 | ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package); |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | TEST(PROCESSORS, linux_id) { |
| 53 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 54 | switch (i) { |
| 55 | case 0: |
| 56 | case 1: |
| 57 | case 2: |
| 58 | case 3: |
| 59 | ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id); |
| 60 | break; |
| 61 | case 4: |
| 62 | case 5: |
| 63 | case 6: |
| 64 | case 7: |
| 65 | ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id); |
| 66 | break; |
| 67 | } |
| 68 | } |
| 69 | } |
| 70 | |
| 71 | TEST(PROCESSORS, l1i) { |
| 72 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 73 | ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | TEST(PROCESSORS, l1d) { |
| 78 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 79 | ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d); |
| 80 | } |
| 81 | } |
| 82 | |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 83 | TEST(PROCESSORS, DISABLED_l2) { |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 84 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 85 | ASSERT_EQ(cpuinfo_get_l2_cache(i), cpuinfo_get_processor(i)->cache.l2); |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 86 | } |
| 87 | } |
| 88 | |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 89 | TEST(PROCESSORS, DISABLED_l3) { |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 90 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 91 | ASSERT_EQ(cpuinfo_get_l3_cache(0), cpuinfo_get_processor(i)->cache.l3); |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 92 | } |
| 93 | } |
| 94 | |
| 95 | TEST(PROCESSORS, l4) { |
| 96 | for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { |
| 97 | ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | TEST(CORES, count) { |
| 102 | ASSERT_EQ(8, cpuinfo_get_cores_count()); |
| 103 | } |
| 104 | |
| 105 | TEST(CORES, non_null) { |
| 106 | ASSERT_TRUE(cpuinfo_get_cores()); |
| 107 | } |
| 108 | |
| 109 | TEST(CORES, processor_start) { |
| 110 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 111 | ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | TEST(CORES, processor_count) { |
| 116 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 117 | ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count); |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | TEST(CORES, core_id) { |
| 122 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 123 | ASSERT_EQ(i, cpuinfo_get_core(i)->core_id); |
| 124 | } |
| 125 | } |
| 126 | |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 127 | TEST(CORES, cluster) { |
| 128 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 129 | switch (i) { |
| 130 | case 0: |
| 131 | case 1: |
| 132 | case 2: |
| 133 | case 3: |
| 134 | ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster); |
| 135 | break; |
| 136 | case 4: |
| 137 | case 5: |
| 138 | case 6: |
| 139 | case 7: |
| 140 | ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster); |
| 141 | break; |
| 142 | } |
| 143 | } |
| 144 | } |
| 145 | |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 146 | TEST(CORES, package) { |
| 147 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 148 | ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package); |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | TEST(CORES, vendor) { |
| 153 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 154 | ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor); |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | TEST(CORES, uarch) { |
| 159 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 160 | switch (i) { |
| 161 | case 0: |
| 162 | case 1: |
| 163 | case 2: |
| 164 | case 3: |
| 165 | ASSERT_EQ(cpuinfo_uarch_cortex_a75, cpuinfo_get_core(i)->uarch); |
| 166 | break; |
| 167 | case 4: |
| 168 | case 5: |
| 169 | case 6: |
| 170 | case 7: |
| 171 | ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_core(i)->uarch); |
| 172 | break; |
| 173 | } |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | TEST(CORES, midr) { |
| 178 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 179 | switch (i) { |
| 180 | case 0: |
| 181 | case 1: |
| 182 | case 2: |
| 183 | case 3: |
| 184 | ASSERT_EQ(UINT32_C(0x516F802D), cpuinfo_get_core(i)->midr); |
| 185 | break; |
| 186 | case 4: |
| 187 | case 5: |
| 188 | case 6: |
| 189 | case 7: |
| 190 | ASSERT_EQ(UINT32_C(0x517F803C), cpuinfo_get_core(i)->midr); |
| 191 | break; |
| 192 | } |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | TEST(CORES, DISABLED_frequency) { |
| 197 | for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { |
| 198 | switch (i) { |
| 199 | case 0: |
| 200 | case 1: |
| 201 | case 2: |
| 202 | case 3: |
| 203 | ASSERT_EQ(UINT64_C(2803200000), cpuinfo_get_core(i)->frequency); |
| 204 | break; |
| 205 | case 4: |
| 206 | case 5: |
| 207 | case 6: |
| 208 | case 7: |
| 209 | ASSERT_EQ(UINT64_C(1766400000), cpuinfo_get_core(i)->frequency); |
| 210 | break; |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | |
Marat Dukhan | dbc7840 | 2018-03-18 22:49:35 -0700 | [diff] [blame^] | 215 | TEST(CLUSTERS, count) { |
| 216 | ASSERT_EQ(2, cpuinfo_get_clusters_count()); |
| 217 | } |
| 218 | |
| 219 | TEST(CLUSTERS, non_null) { |
| 220 | ASSERT_TRUE(cpuinfo_get_clusters()); |
| 221 | } |
| 222 | |
| 223 | TEST(CLUSTERS, processor_start) { |
| 224 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 225 | switch (i) { |
| 226 | case 0: |
| 227 | ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start); |
| 228 | break; |
| 229 | case 1: |
| 230 | ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start); |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | TEST(CLUSTERS, processor_count) { |
| 237 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 238 | ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | TEST(CLUSTERS, core_start) { |
| 243 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 244 | switch (i) { |
| 245 | case 0: |
| 246 | ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start); |
| 247 | break; |
| 248 | case 1: |
| 249 | ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start); |
| 250 | break; |
| 251 | } |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | TEST(CLUSTERS, core_count) { |
| 256 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 257 | ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count); |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | TEST(CLUSTERS, cluster_id) { |
| 262 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 263 | ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id); |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | TEST(CLUSTERS, package) { |
| 268 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 269 | ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package); |
| 270 | } |
| 271 | } |
| 272 | |
| 273 | TEST(CLUSTERS, vendor) { |
| 274 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 275 | ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor); |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | TEST(CLUSTERS, uarch) { |
| 280 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 281 | switch (i) { |
| 282 | case 0: |
| 283 | ASSERT_EQ(cpuinfo_uarch_cortex_a75, cpuinfo_get_cluster(i)->uarch); |
| 284 | break; |
| 285 | case 1: |
| 286 | ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_cluster(i)->uarch); |
| 287 | break; |
| 288 | } |
| 289 | } |
| 290 | } |
| 291 | |
| 292 | TEST(CLUSTERS, midr) { |
| 293 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 294 | switch (i) { |
| 295 | case 0: |
| 296 | ASSERT_EQ(UINT32_C(0x516F802D), cpuinfo_get_cluster(i)->midr); |
| 297 | break; |
| 298 | case 1: |
| 299 | ASSERT_EQ(UINT32_C(0x517F803C), cpuinfo_get_cluster(i)->midr); |
| 300 | break; |
| 301 | } |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | TEST(CLUSTERS, DISABLED_frequency) { |
| 306 | for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { |
| 307 | switch (i) { |
| 308 | case 0: |
| 309 | ASSERT_EQ(UINT64_C(2803200000), cpuinfo_get_cluster(i)->frequency); |
| 310 | break; |
| 311 | case 1: |
| 312 | ASSERT_EQ(UINT64_C(1766400000), cpuinfo_get_cluster(i)->frequency); |
| 313 | break; |
| 314 | } |
| 315 | } |
| 316 | } |
| 317 | |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 318 | TEST(PACKAGES, count) { |
| 319 | ASSERT_EQ(1, cpuinfo_get_packages_count()); |
| 320 | } |
| 321 | |
| 322 | TEST(PACKAGES, name) { |
| 323 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 324 | ASSERT_EQ("Qualcomm Snapdragon 845", |
| 325 | std::string(cpuinfo_get_package(i)->name, |
| 326 | strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | TEST(PACKAGES, gpu_name) { |
| 331 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 332 | ASSERT_EQ("Qualcomm Adreno 630", |
| 333 | std::string(cpuinfo_get_package(i)->gpu_name, |
| 334 | strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX))); |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | TEST(PACKAGES, processor_start) { |
| 339 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 340 | ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start); |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | TEST(PACKAGES, processor_count) { |
| 345 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 346 | ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | TEST(PACKAGES, core_start) { |
| 351 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 352 | ASSERT_EQ(0, cpuinfo_get_package(i)->core_start); |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | TEST(PACKAGES, core_count) { |
| 357 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 358 | ASSERT_EQ(8, cpuinfo_get_package(i)->core_count); |
| 359 | } |
| 360 | } |
| 361 | |
Marat Dukhan | 2b30793 | 2018-03-18 16:15:36 -0700 | [diff] [blame] | 362 | TEST(PACKAGES, cluster_start) { |
| 363 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 364 | ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start); |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | TEST(PACKAGES, cluster_count) { |
| 369 | for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { |
| 370 | ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count); |
| 371 | } |
| 372 | } |
| 373 | |
Marat Dukhan | d51d395 | 2018-03-17 19:18:06 -0700 | [diff] [blame] | 374 | TEST(ISA, thumb) { |
| 375 | #if CPUINFO_ARCH_ARM |
| 376 | ASSERT_TRUE(cpuinfo_has_arm_thumb()); |
| 377 | #elif CPUINFO_ARCH_ARM64 |
| 378 | ASSERT_FALSE(cpuinfo_has_arm_thumb()); |
| 379 | #endif |
| 380 | } |
| 381 | |
| 382 | TEST(ISA, thumb2) { |
| 383 | #if CPUINFO_ARCH_ARM |
| 384 | ASSERT_TRUE(cpuinfo_has_arm_thumb2()); |
| 385 | #elif CPUINFO_ARCH_ARM64 |
| 386 | ASSERT_FALSE(cpuinfo_has_arm_thumb2()); |
| 387 | #endif |
| 388 | } |
| 389 | |
| 390 | TEST(ISA, armv5e) { |
| 391 | #if CPUINFO_ARCH_ARM |
| 392 | ASSERT_TRUE(cpuinfo_has_arm_v5e()); |
| 393 | #elif CPUINFO_ARCH_ARM64 |
| 394 | ASSERT_FALSE(cpuinfo_has_arm_v5e()); |
| 395 | #endif |
| 396 | } |
| 397 | |
| 398 | TEST(ISA, armv6) { |
| 399 | #if CPUINFO_ARCH_ARM |
| 400 | ASSERT_TRUE(cpuinfo_has_arm_v6()); |
| 401 | #elif CPUINFO_ARCH_ARM64 |
| 402 | ASSERT_FALSE(cpuinfo_has_arm_v6()); |
| 403 | #endif |
| 404 | } |
| 405 | |
| 406 | TEST(ISA, armv6k) { |
| 407 | #if CPUINFO_ARCH_ARM |
| 408 | ASSERT_TRUE(cpuinfo_has_arm_v6k()); |
| 409 | #elif CPUINFO_ARCH_ARM64 |
| 410 | ASSERT_FALSE(cpuinfo_has_arm_v6k()); |
| 411 | #endif |
| 412 | } |
| 413 | |
| 414 | TEST(ISA, armv7) { |
| 415 | #if CPUINFO_ARCH_ARM |
| 416 | ASSERT_TRUE(cpuinfo_has_arm_v7()); |
| 417 | #elif CPUINFO_ARCH_ARM64 |
| 418 | ASSERT_FALSE(cpuinfo_has_arm_v7()); |
| 419 | #endif |
| 420 | } |
| 421 | |
| 422 | TEST(ISA, armv7mp) { |
| 423 | #if CPUINFO_ARCH_ARM |
| 424 | ASSERT_TRUE(cpuinfo_has_arm_v7mp()); |
| 425 | #elif CPUINFO_ARCH_ARM64 |
| 426 | ASSERT_FALSE(cpuinfo_has_arm_v7mp()); |
| 427 | #endif |
| 428 | } |
| 429 | |
| 430 | TEST(ISA, idiv) { |
| 431 | ASSERT_TRUE(cpuinfo_has_arm_idiv()); |
| 432 | } |
| 433 | |
| 434 | TEST(ISA, vfpv2) { |
| 435 | ASSERT_FALSE(cpuinfo_has_arm_vfpv2()); |
| 436 | } |
| 437 | |
| 438 | TEST(ISA, vfpv3) { |
| 439 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3()); |
| 440 | } |
| 441 | |
| 442 | TEST(ISA, vfpv3_d32) { |
| 443 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32()); |
| 444 | } |
| 445 | |
| 446 | TEST(ISA, vfpv3_fp16) { |
| 447 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16()); |
| 448 | } |
| 449 | |
| 450 | TEST(ISA, vfpv3_fp16_d32) { |
| 451 | ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32()); |
| 452 | } |
| 453 | |
| 454 | TEST(ISA, vfpv4) { |
| 455 | ASSERT_TRUE(cpuinfo_has_arm_vfpv4()); |
| 456 | } |
| 457 | |
| 458 | TEST(ISA, vfpv4_d32) { |
| 459 | ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32()); |
| 460 | } |
| 461 | |
| 462 | TEST(ISA, wmmx) { |
| 463 | ASSERT_FALSE(cpuinfo_has_arm_wmmx()); |
| 464 | } |
| 465 | |
| 466 | TEST(ISA, wmmx2) { |
| 467 | ASSERT_FALSE(cpuinfo_has_arm_wmmx2()); |
| 468 | } |
| 469 | |
| 470 | TEST(ISA, neon) { |
| 471 | ASSERT_TRUE(cpuinfo_has_arm_neon()); |
| 472 | } |
| 473 | |
| 474 | TEST(ISA, neon_fp16) { |
| 475 | ASSERT_TRUE(cpuinfo_has_arm_neon_fp16()); |
| 476 | } |
| 477 | |
| 478 | TEST(ISA, neon_fma) { |
| 479 | ASSERT_TRUE(cpuinfo_has_arm_neon_fma()); |
| 480 | } |
| 481 | |
| 482 | TEST(ISA, atomics) { |
| 483 | #if CPUINFO_ARCH_ARM |
| 484 | ASSERT_FALSE(cpuinfo_has_arm_atomics()); |
| 485 | #elif CPUINFO_ARCH_ARM64 |
| 486 | ASSERT_TRUE(cpuinfo_has_arm_atomics()); |
| 487 | #endif |
| 488 | } |
| 489 | |
| 490 | TEST(ISA, neon_rdm) { |
| 491 | ASSERT_FALSE(cpuinfo_has_arm_neon_rdm()); |
| 492 | } |
| 493 | |
| 494 | TEST(ISA, fp16_arith) { |
| 495 | #if CPUINFO_ARCH_ARM |
| 496 | ASSERT_FALSE(cpuinfo_has_arm_fp16_arith()); |
| 497 | #elif CPUINFO_ARCH_ARM64 |
| 498 | ASSERT_TRUE(cpuinfo_has_arm_fp16_arith()); |
| 499 | #endif |
| 500 | } |
| 501 | |
| 502 | TEST(ISA, jscvt) { |
| 503 | ASSERT_FALSE(cpuinfo_has_arm_jscvt()); |
| 504 | } |
| 505 | |
| 506 | TEST(ISA, fcma) { |
| 507 | ASSERT_FALSE(cpuinfo_has_arm_fcma()); |
| 508 | } |
| 509 | |
| 510 | TEST(ISA, aes) { |
| 511 | ASSERT_TRUE(cpuinfo_has_arm_aes()); |
| 512 | } |
| 513 | |
| 514 | TEST(ISA, sha1) { |
| 515 | ASSERT_TRUE(cpuinfo_has_arm_sha1()); |
| 516 | } |
| 517 | |
| 518 | TEST(ISA, sha2) { |
| 519 | ASSERT_TRUE(cpuinfo_has_arm_sha2()); |
| 520 | } |
| 521 | |
| 522 | TEST(ISA, pmull) { |
| 523 | ASSERT_TRUE(cpuinfo_has_arm_pmull()); |
| 524 | } |
| 525 | |
| 526 | TEST(ISA, crc32) { |
| 527 | ASSERT_TRUE(cpuinfo_has_arm_crc32()); |
| 528 | } |
| 529 | |
| 530 | TEST(L1I, count) { |
| 531 | ASSERT_EQ(8, cpuinfo_get_l1i_caches_count()); |
| 532 | } |
| 533 | |
| 534 | TEST(L1I, non_null) { |
| 535 | ASSERT_TRUE(cpuinfo_get_l1i_caches()); |
| 536 | } |
| 537 | |
| 538 | TEST(L1I, DISABLED_size) { |
| 539 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 540 | switch (i) { |
| 541 | case 0: |
| 542 | case 1: |
| 543 | case 2: |
| 544 | case 3: |
| 545 | ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size); |
| 546 | break; |
| 547 | case 4: |
| 548 | case 5: |
| 549 | case 6: |
| 550 | case 7: |
| 551 | ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size); |
| 552 | break; |
| 553 | } |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | TEST(L1I, DISABLED_associativity) { |
| 558 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 559 | ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity); |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | TEST(L1I, sets) { |
| 564 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 565 | ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, |
| 566 | cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); |
| 567 | } |
| 568 | } |
| 569 | |
| 570 | TEST(L1I, partitions) { |
| 571 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 572 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions); |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | TEST(L1I, line_size) { |
| 577 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 578 | ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size); |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | TEST(L1I, flags) { |
| 583 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 584 | ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags); |
| 585 | } |
| 586 | } |
| 587 | |
| 588 | TEST(L1I, processors) { |
| 589 | for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { |
| 590 | ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start); |
| 591 | ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count); |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | TEST(L1D, count) { |
| 596 | ASSERT_EQ(8, cpuinfo_get_l1d_caches_count()); |
| 597 | } |
| 598 | |
| 599 | TEST(L1D, non_null) { |
| 600 | ASSERT_TRUE(cpuinfo_get_l1d_caches()); |
| 601 | } |
| 602 | |
| 603 | TEST(L1D, DISABLED_size) { |
| 604 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 605 | switch (i) { |
| 606 | case 0: |
| 607 | case 1: |
| 608 | case 2: |
| 609 | case 3: |
| 610 | ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size); |
| 611 | break; |
| 612 | case 4: |
| 613 | case 5: |
| 614 | case 6: |
| 615 | case 7: |
| 616 | ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size); |
| 617 | break; |
| 618 | } |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | TEST(L1D, DISABLED_associativity) { |
| 623 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 624 | switch (i) { |
| 625 | case 0: |
| 626 | case 1: |
| 627 | case 2: |
| 628 | case 3: |
| 629 | ASSERT_EQ(16, cpuinfo_get_l1d_cache(i)->associativity); |
| 630 | break; |
| 631 | case 4: |
| 632 | case 5: |
| 633 | case 6: |
| 634 | case 7: |
| 635 | ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity); |
| 636 | break; |
| 637 | } |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | TEST(L1D, sets) { |
| 642 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 643 | ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, |
| 644 | cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | TEST(L1D, partitions) { |
| 649 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 650 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions); |
| 651 | } |
| 652 | } |
| 653 | |
| 654 | TEST(L1D, line_size) { |
| 655 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 656 | ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size); |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | TEST(L1D, flags) { |
| 661 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 662 | ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags); |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | TEST(L1D, processors) { |
| 667 | for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { |
| 668 | ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start); |
| 669 | ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count); |
| 670 | } |
| 671 | } |
| 672 | |
| 673 | TEST(L2, DISABLED_count) { |
| 674 | ASSERT_EQ(8, cpuinfo_get_l2_caches_count()); |
| 675 | } |
| 676 | |
| 677 | TEST(L2, non_null) { |
| 678 | ASSERT_TRUE(cpuinfo_get_l2_caches()); |
| 679 | } |
| 680 | |
| 681 | TEST(L2, DISABLED_size) { |
| 682 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 683 | switch (i) { |
| 684 | case 0: |
| 685 | case 1: |
| 686 | case 2: |
| 687 | case 3: |
| 688 | ASSERT_EQ(128 * 1024, cpuinfo_get_l2_cache(i)->size); |
| 689 | break; |
| 690 | case 4: |
| 691 | case 5: |
| 692 | case 6: |
| 693 | case 7: |
| 694 | ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size); |
| 695 | break; |
| 696 | } |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | TEST(L2, DISABLED_associativity) { |
| 701 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 702 | switch (i) { |
| 703 | case 0: |
| 704 | case 1: |
| 705 | case 2: |
| 706 | case 3: |
| 707 | ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity); |
| 708 | break; |
| 709 | case 4: |
| 710 | case 5: |
| 711 | case 6: |
| 712 | case 7: |
| 713 | ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->associativity); |
| 714 | break; |
| 715 | } |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | TEST(L2, sets) { |
| 720 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 721 | ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, |
| 722 | cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | TEST(L2, partitions) { |
| 727 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 728 | ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions); |
| 729 | } |
| 730 | } |
| 731 | |
| 732 | TEST(L2, line_size) { |
| 733 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 734 | ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size); |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | TEST(L2, DISABLED_flags) { |
| 739 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 740 | ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags); |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | TEST(L2, DISABLED_processors) { |
| 745 | for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { |
| 746 | ASSERT_EQ(i, cpuinfo_get_l2_cache(i)->processor_start); |
| 747 | ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->processor_count); |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | TEST(L3, DISABLED_count) { |
| 752 | ASSERT_EQ(1, cpuinfo_get_l3_caches_count()); |
| 753 | } |
| 754 | |
| 755 | TEST(L3, DISABLED_non_null) { |
| 756 | ASSERT_TRUE(cpuinfo_get_l3_caches()); |
| 757 | } |
| 758 | |
| 759 | TEST(L3, DISABLED_size) { |
| 760 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 761 | ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l3_cache(i)->size); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | TEST(L3, DISABLED_associativity) { |
| 766 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 767 | ASSERT_EQ(8, cpuinfo_get_l3_cache(i)->associativity); |
| 768 | } |
| 769 | } |
| 770 | |
| 771 | TEST(L3, sets) { |
| 772 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 773 | ASSERT_EQ(cpuinfo_get_l3_cache(i)->size, |
| 774 | cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | TEST(L3, partitions) { |
| 779 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 780 | ASSERT_EQ(1, cpuinfo_get_l3_cache(i)->partitions); |
| 781 | } |
| 782 | } |
| 783 | |
| 784 | TEST(L3, line_size) { |
| 785 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 786 | ASSERT_EQ(64, cpuinfo_get_l3_cache(i)->line_size); |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | TEST(L3, DISABLED_flags) { |
| 791 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 792 | ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->flags); |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | TEST(L3, processors) { |
| 797 | for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { |
| 798 | ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->processor_start); |
| 799 | ASSERT_EQ(8, cpuinfo_get_l3_cache(i)->processor_count); |
| 800 | } |
| 801 | } |
| 802 | |
| 803 | TEST(L4, none) { |
| 804 | ASSERT_EQ(0, cpuinfo_get_l4_caches_count()); |
| 805 | ASSERT_FALSE(cpuinfo_get_l4_caches()); |
| 806 | } |
| 807 | |
| 808 | #include <galaxy-s9-us.h> |
| 809 | |
| 810 | int main(int argc, char* argv[]) { |
| 811 | #if CPUINFO_ARCH_ARM |
| 812 | cpuinfo_set_hwcap(UINT32_C(0x0037B0D6)); |
| 813 | cpuinfo_set_hwcap2(UINT32_C(0x0000001F)); |
| 814 | #elif CPUINFO_ARCH_ARM64 |
| 815 | cpuinfo_set_hwcap(UINT32_C(0x000007FF)); |
| 816 | #endif |
| 817 | cpuinfo_mock_filesystem(filesystem); |
| 818 | #ifdef __ANDROID__ |
| 819 | cpuinfo_mock_android_properties(properties); |
| 820 | cpuinfo_mock_gl_renderer("Adreno (TM) 630"); |
| 821 | #endif |
| 822 | cpuinfo_initialize(); |
| 823 | ::testing::InitGoogleTest(&argc, argv); |
| 824 | return RUN_ALL_TESTS(); |
| 825 | } |