Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 1 | #include <stdint.h> |
| 2 | |
| 3 | #include <cpuinfo.h> |
| 4 | #include <log.h> |
| 5 | #include <arm/api.h> |
| 6 | |
| 7 | |
| 8 | void cpuinfo_arm_decode_cache( |
| 9 | enum cpuinfo_uarch uarch, |
| 10 | uint32_t uarch_cores, |
| 11 | uint32_t cpu_part, |
| 12 | uint32_t arch_version, |
| 13 | struct cpuinfo_cache l1i[restrict static 1], |
| 14 | struct cpuinfo_cache l1d[restrict static 1], |
| 15 | struct cpuinfo_cache l2[restrict static 1]) |
| 16 | { |
| 17 | switch (uarch) { |
| 18 | case cpuinfo_uarch_xscale: |
| 19 | switch (cpu_part >> 8) { |
| 20 | case 2: |
| 21 | /* |
| 22 | * PXA 210/25X/26X |
| 23 | * |
| 24 | * See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface" |
| 25 | * by David A. Patterson, John L. Hennessy |
| 26 | */ |
| 27 | *l1i = (struct cpuinfo_cache) { |
| 28 | .size = 16 * 1024, |
| 29 | .associativity = 32, |
| 30 | .line_size = 32 |
| 31 | }; |
| 32 | *l1d = (struct cpuinfo_cache) { |
| 33 | .size = 16 * 1024, |
| 34 | .associativity = 4, |
| 35 | .line_size = 64 |
| 36 | }; |
| 37 | break; |
| 38 | case 4: |
| 39 | /* PXA 27X */ |
| 40 | *l1i = (struct cpuinfo_cache) { |
| 41 | .size = 32 * 1024, |
| 42 | .associativity = 32, |
| 43 | .line_size = 32 |
| 44 | }; |
| 45 | *l1d = (struct cpuinfo_cache) { |
| 46 | .size = 32 * 1024, |
| 47 | .associativity = 32, |
| 48 | .line_size = 32 |
| 49 | }; |
| 50 | break; |
| 51 | case 6: |
| 52 | /* |
| 53 | * PXA 3XX |
| 54 | * |
| 55 | * See http://download.intel.com/design/intelxscale/31628302.pdf |
| 56 | */ |
| 57 | *l1i = (struct cpuinfo_cache) { |
| 58 | .size = 32 * 1024, |
| 59 | .associativity = 4, |
| 60 | .line_size = 32 |
| 61 | }; |
| 62 | *l1d = (struct cpuinfo_cache) { |
| 63 | .size = 32 * 1024, |
| 64 | .associativity = 4, |
| 65 | .line_size = 32 |
| 66 | }; |
| 67 | *l2 = (struct cpuinfo_cache) { |
| 68 | .size = 256 * 1024, |
| 69 | .associativity = 8, |
| 70 | .line_size = 32 |
| 71 | }; |
| 72 | break; |
| 73 | } |
| 74 | break; |
| 75 | case cpuinfo_uarch_arm11: |
| 76 | *l1i = (struct cpuinfo_cache) { |
| 77 | .size = 16 * 1024, |
| 78 | .associativity = 4, |
| 79 | .line_size = 32 |
| 80 | }; |
| 81 | *l1d = (struct cpuinfo_cache) { |
| 82 | .size = 16 * 1024, |
| 83 | .associativity = 4, |
| 84 | .line_size = 32 |
| 85 | }; |
| 86 | break; |
| 87 | case cpuinfo_uarch_cortex_a5: |
| 88 | /* |
| 89 | * Cortex-A5 Technical Reference Manual: |
| 90 | * 7.1.1. Memory system |
| 91 | * The Cortex-A5 processor has separate instruction and data caches. |
| 92 | * The caches have the following features: |
| 93 | * - Data cache is 4-way set-associative. |
| 94 | * - Instruction cache is 2-way set-associative. |
| 95 | * - The cache line length is eight words. |
| 96 | * - You can configure the instruction and data caches independently during implementation |
| 97 | * to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB. |
| 98 | * 1.1.3. System design components |
| 99 | * PrimeCell Level 2 Cache Controller (PL310) |
| 100 | * The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a |
| 101 | * recognized method of improving the performance of ARM-based systems when significant memory traffic |
| 102 | * is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external |
| 103 | * memory accesses and has been optimized for use with the Cortex-A5 processor. |
| 104 | * 8.1.7. Exclusive L2 cache |
| 105 | * The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode. |
| 106 | * This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller. |
| 107 | * |
| 108 | * +--------------------+-----------+-----------+----------+-----------+ |
| 109 | * | Processor model | L1D cache | L1I cache | L2 cache | Reference | |
| 110 | * +--------------------+-----------+-----------+----------+-----------+ |
| 111 | * | Qualcomm MSM7225A | | | | | |
| 112 | * | Qualcomm MSM7625A | | | | | |
| 113 | * | Qualcomm MSM7227A | | | | | |
| 114 | * | Qualcomm MSM7627A | 32K | 32K | 256K | Wiki [1] | |
| 115 | * | Qualcomm MSM7225AB | | | | | |
| 116 | * | Qualcomm MSM7225AB | | | | | |
| 117 | * | Qualcomm QSD8250 | | | | | |
| 118 | * | Qualcomm QSD8650 | | | | | |
| 119 | * +--------------------+-----------+-----------+----------+-----------+ |
| 120 | * | Spreadtrum SC6821 | 32K | 32K | ? | | |
| 121 | * | Spreadtrum SC6825 | 32K | 32K | 256K | Wiki [2] | |
| 122 | * | Spreadtrum SC8810 | ? | ? | ? | | |
| 123 | * | Spreadtrum SC8825 | 32K | 32K | ? | | |
| 124 | * +--------------------+-----------+-----------+----------+-----------+ |
| 125 | * |
| 126 | * [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1 |
| 127 | * [2] https://en.wikipedia.org/wiki/Spreadtrum |
| 128 | */ |
| 129 | *l1i = (struct cpuinfo_cache) { |
| 130 | .size = 32 * 1024, |
| 131 | .associativity = 2, |
| 132 | .line_size = 32 |
| 133 | }; |
| 134 | *l1d = (struct cpuinfo_cache) { |
| 135 | .size = 32 * 1024, |
| 136 | .associativity = 4, |
| 137 | .line_size = 32 |
| 138 | }; |
| 139 | *l2 = (struct cpuinfo_cache) { |
| 140 | .size = 256 * 1024, |
| 141 | /* |
| 142 | * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size" |
| 143 | * Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf |
| 144 | */ |
| 145 | .associativity = 8, |
| 146 | .line_size = 32 |
| 147 | }; |
| 148 | break; |
| 149 | case cpuinfo_uarch_cortex_a7: |
| 150 | /* |
| 151 | * Cortex-A7 MPCore Technical Reference Manual: |
| 152 | * 6.1. About the L1 memory system |
| 153 | * The L1 memory system consists of separate instruction and data caches. You can configure the |
| 154 | * instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB. |
| 155 | * |
| 156 | * The L1 instruction memory system has the following features: |
| 157 | * - Instruction side cache line length of 32-bytes. |
| 158 | * - 2-way set-associative instruction cache. |
| 159 | * |
| 160 | * The L1 data memory system has the following features: |
| 161 | * - Data side cache line length of 64-bytes. |
| 162 | * - 4-way set-associative data cache. |
| 163 | * |
| 164 | * 7.1. About the L2 Memory system |
| 165 | * The L2 memory system consists of an: |
| 166 | * - Optional tightly-coupled L2 cache that includes: |
| 167 | * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB. |
| 168 | * |
| 169 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 170 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 171 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 172 | * | Allwinner A20 | 2 | 32K | 32K | 256K | [1] | |
| 173 | * | Allwinner A23 | 2 | 32K | 32K | 256K | [2] | |
| 174 | * | Allwinner A31 | 4 | 32K | 32K | 1M | [3] | |
| 175 | * | Allwinner A31s | 4 | 32K | 32K | 1M | [4] | |
| 176 | * | Allwinner A33 | 4 | 32K | 32K | 512K | [5] | |
| 177 | * | Allwinner A80 Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] | |
| 178 | * | Allwinner A81T | 8 | 32K | 32K | 1M | [7] | |
| 179 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 180 | * | Broadcom BCM2836 | 4 | 32K | 32K | 512K | [8] | |
| 181 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 182 | * |
| 183 | * [1] https://linux-sunxi.org/A20 |
| 184 | * [2] https://linux-sunxi.org/A23 |
| 185 | * [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf |
| 186 | * [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf |
| 187 | * [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf |
| 188 | * [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf |
| 189 | * [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf |
| 190 | * [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428 |
| 191 | */ |
| 192 | *l1i = (struct cpuinfo_cache) { |
| 193 | .size = 32 * 1024, |
| 194 | .associativity = 2, |
| 195 | .line_size = 32 |
| 196 | }; |
| 197 | *l1d = (struct cpuinfo_cache) { |
| 198 | .size = 32 * 1024, |
| 199 | .associativity = 4, |
| 200 | .line_size = 64 |
| 201 | }; |
| 202 | *l2 = (struct cpuinfo_cache) { |
| 203 | .size = 128 * 1024 * uarch_cores, |
| 204 | .associativity = 8, |
| 205 | .line_size = 64 |
| 206 | }; |
| 207 | break; |
| 208 | case cpuinfo_uarch_cortex_a8: |
| 209 | /* |
| 210 | * Cortex-A8 Technical Reference Manual: |
| 211 | * 7.1. About the L1 memory system |
| 212 | * The L1 memory system consists of separate instruction and data caches in a Harvard arrangement. |
| 213 | * The L1 memory system provides the core with: |
| 214 | * - fixed line length of 64 bytes |
| 215 | * - support for 16KB or 32KB caches |
| 216 | * - 4-way set associative cache structure |
| 217 | * 8.1. About the L2 memory system |
| 218 | * The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache. |
| 219 | * The key features of the L2 memory system include: |
| 220 | * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB |
| 221 | * - fixed line length of 64 bytes |
| 222 | * - 8-way set associative cache structure |
| 223 | */ |
| 224 | *l1i = (struct cpuinfo_cache) { |
| 225 | .size = 16 * 1024, |
| 226 | .associativity = 4, |
| 227 | .line_size = 64 |
| 228 | }; |
| 229 | *l1d = (struct cpuinfo_cache) { |
| 230 | .size = 16 * 1024, |
| 231 | .associativity = 4, |
| 232 | .line_size = 64 |
| 233 | }; |
| 234 | *l2 = (struct cpuinfo_cache) { |
| 235 | .size = 128 * 1024, |
| 236 | .associativity = 8, |
| 237 | .line_size = 64 |
| 238 | }; |
| 239 | break; |
| 240 | case cpuinfo_uarch_cortex_a9: |
| 241 | /* |
| 242 | * ARM Cortex‑A9 Technical Reference Manual: |
| 243 | * 7.1.1 Memory system |
| 244 | * The Cortex‑A9 processor has separate instruction and data caches. |
| 245 | * The caches have the following features: |
| 246 | * - Both caches are 4-way set-associative. |
| 247 | * - The cache line length is eight words. |
| 248 | * - You can configure the instruction and data caches independently during implementation |
| 249 | * to sizes of 16KB, 32KB, or 64KB. |
| 250 | * 8.1.5 Exclusive L2 cache |
| 251 | * The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode. |
| 252 | * This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller. |
| 253 | * |
| 254 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 255 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 256 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 257 | * | Exynos 4 Dual 4210 | 2 | 32K | 32K | 1M | [1] | |
| 258 | * | Exynos 4 Dual 4212 | 2 | 32K | 32K | 1M | [2] | |
| 259 | * | Exynos 4 Quad 4412 | 4 | 32K | 32K | 1M | [3] | |
| 260 | * | Exynos 4 Quad 4415 | 4 | 32K | 32K | 1M | | |
| 261 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 262 | * |
| 263 | * [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf |
| 264 | * [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf |
| 265 | * [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf |
| 266 | */ |
| 267 | |
| 268 | /* Use Exynos 4 specs */ |
| 269 | *l1i = (struct cpuinfo_cache) { |
| 270 | .size = 32 * 1024, |
| 271 | .associativity = 4, |
| 272 | .line_size = 32 |
| 273 | }; |
| 274 | *l1d = (struct cpuinfo_cache) { |
| 275 | .size = 32 * 1024, |
| 276 | .associativity = 4, |
| 277 | .line_size = 32 |
| 278 | }; |
| 279 | *l2 = (struct cpuinfo_cache) { |
| 280 | .size = 1024 * 1024, |
| 281 | .associativity = 8, |
| 282 | .line_size = 32 |
| 283 | }; |
| 284 | break; |
| 285 | case cpuinfo_uarch_cortex_a15: |
| 286 | /* |
| 287 | * 6.1. About the L1 memory system |
| 288 | * The L1 memory system consists of separate instruction and data caches. |
| 289 | * The L1 instruction memory system has the following features: |
| 290 | * - 32KB 2-way set-associative instruction cache. |
| 291 | * - Fixed line length of 64 bytes. |
| 292 | * The L1 data memory system has the following features: |
| 293 | * - 32KB 2-way set-associative data cache. |
| 294 | * - Fixed line length of 64 bytes. |
| 295 | * 7.1. About the L2 memory system |
| 296 | * The features of the L2 memory system include: |
| 297 | * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. |
| 298 | * - Fixed line length of 64 bytes. |
| 299 | * - 16-way set-associative cache structure. |
| 300 | * |
| 301 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 302 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 303 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 304 | * | Exynos 5 Dual 5250 | 2 | 32K | 32K | 1M | [1] | |
| 305 | * | Exynos 5 Hexa 5260 | 2(+4) | 32K | 32K | 1M(+512K) | [2] | |
| 306 | * | Exynos 5 Octa 5410 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | |
| 307 | * | Exynos 5 Octa 5420 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | |
| 308 | * | Exynos 5 Octa 5422 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | |
| 309 | * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | |
| 310 | * | Exynos 5 Octa 5800 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | |
| 311 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 312 | * |
| 313 | * [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf |
| 314 | * [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf |
| 315 | * [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 |
| 316 | */ |
| 317 | *l1i = (struct cpuinfo_cache) { |
| 318 | .size = 32 * 1024, |
| 319 | .associativity = 2, |
| 320 | .line_size = 64 |
| 321 | }; |
| 322 | *l1d = (struct cpuinfo_cache) { |
| 323 | .size = 32 * 1024, |
| 324 | .associativity = 2, |
| 325 | .line_size = 64 |
| 326 | }; |
| 327 | *l2 = (struct cpuinfo_cache) { |
| 328 | .size = uarch_cores * 512 * 1024, |
| 329 | .associativity = 16, |
| 330 | .line_size = 64 |
| 331 | }; |
| 332 | break; |
Marat Dukhan | ee705c7 | 2017-05-08 10:18:03 +0000 | [diff] [blame^] | 333 | case cpuinfo_uarch_cortex_a53: |
| 334 | /* |
| 335 | * ARM Cortex-A53 MPCore Processor Technical Reference Manual: |
| 336 | * 6.1. About the L1 memory system |
| 337 | * he L1 memory system consists of separate instruction and data caches. The implementer configures the |
| 338 | * instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB. |
| 339 | * |
| 340 | * The L1 Instruction memory system has the following key features: |
| 341 | * - Instruction side cache line length of 64 bytes. |
| 342 | * - 2-way set associative L1 Instruction cache. |
| 343 | * |
| 344 | * The L1 Data memory system has the following features: |
| 345 | * - Data side cache line length of 64 bytes. |
| 346 | * - 4-way set associative L1 Data cache. |
| 347 | * |
| 348 | * 7.1. About the L2 memory system |
| 349 | * The L2 memory system consists of an: |
| 350 | * - Optional tightly-coupled L2 cache that includes: |
| 351 | * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. |
| 352 | * - Fixed line length of 64 bytes. |
| 353 | * - 16-way set-associative cache structure. |
| 354 | * |
| 355 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 356 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 357 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 358 | * | Broadcom BCM2837 | 4 | 16K | 16K | 512K | [1] | |
| 359 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 360 | * |
| 361 | * [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766 |
| 362 | */ |
| 363 | *l1i = (struct cpuinfo_cache) { |
| 364 | .size = 16 * 1024, |
| 365 | .associativity = 2, |
| 366 | .line_size = 64 |
| 367 | }; |
| 368 | *l1d = (struct cpuinfo_cache) { |
| 369 | .size = 16 * 1024, |
| 370 | .associativity = 4, |
| 371 | .line_size = 64 |
| 372 | }; |
| 373 | *l2 = (struct cpuinfo_cache) { |
| 374 | .size = uarch_cores * 128 * 1024, |
| 375 | .associativity = 16, |
| 376 | .line_size = 64 |
| 377 | }; |
| 378 | break; |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 379 | case cpuinfo_uarch_scorpion: |
| 380 | /* |
| 381 | * - "The CPU includes 32KB instruction and data caches as |
| 382 | * well as a complete memory-management unit (MMU) suitable |
| 383 | * for high-level operating systems. The CPU also has |
| 384 | * 256KB of SRAM that can be allocated in 64KB increments |
| 385 | * to level-two (L2) cache or tightly coupled memory (TCM)." [1] |
| 386 | * We interpret it as L2 cache being 4-way set-associative on single-core Scorpion. |
| 387 | * - L1 Data Cache = 32 KB. 32 B/line. [2] |
| 388 | * - L2 Cache = 256 KB. 128 B/line. [2] |
| 389 | * - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3] |
| 390 | * - Single or dual-core configuration [3] |
| 391 | * - For L1 cache assume the same associativity as Krait |
| 392 | * |
| 393 | * [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf |
| 394 | * [2] http://www.7-cpu.com/cpu/Snapdragon.html |
| 395 | * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU) |
| 396 | */ |
| 397 | *l1i = (struct cpuinfo_cache) { |
| 398 | .size = 32 * 1024, |
| 399 | .associativity = 4, |
| 400 | .line_size = 32 |
| 401 | }; |
| 402 | *l1d = (struct cpuinfo_cache) { |
| 403 | .size = 32 * 1024, |
| 404 | .associativity = 4, |
| 405 | .line_size = 32 |
| 406 | }; |
| 407 | *l2 = (struct cpuinfo_cache) { |
| 408 | .size = uarch_cores * 256 * 1024, |
| 409 | .associativity = 4, |
| 410 | .line_size = 128 |
| 411 | }; |
| 412 | break; |
| 413 | case cpuinfo_uarch_krait: |
| 414 | /* |
| 415 | * - L0 Data cache = 4 KB. 64 B/line, direct mapped [1] |
| 416 | * - L0 Instruction cache = 4 KB. [1] |
| 417 | * - L1 Data cache = 16 KB. 64 B/line, 4-way [1] |
| 418 | * - L1 Instruction cache = 16 KB, 4-way [1] |
| 419 | * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1] |
| 420 | * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set associative [2] |
| 421 | * |
| 422 | * [1] http://www.7-cpu.com/cpu/Krait.html |
| 423 | * [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2 |
| 424 | */ |
| 425 | *l1i = (struct cpuinfo_cache) { |
| 426 | .size = 16 * 1024, |
| 427 | .associativity = 4, |
| 428 | .line_size = 64 /* assume same as L1D */ |
| 429 | }; |
| 430 | *l1d = (struct cpuinfo_cache) { |
| 431 | .size = 16 * 1024, |
| 432 | .associativity = 4, |
| 433 | .line_size = 64 |
| 434 | }; |
| 435 | *l2 = (struct cpuinfo_cache) { |
| 436 | .size = uarch_cores * 512 * 1024, |
| 437 | .associativity = 8, |
| 438 | .line_size = 128 |
| 439 | }; |
| 440 | break; |
| 441 | case cpuinfo_uarch_kryo: |
| 442 | /* |
| 443 | * +-----------------+-------+-----------+-----------+-----------+-----------+ |
| 444 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 445 | * +-----------------+-------+-----------+-----------+-----------+-----------+ |
| 446 | * | Snapdragon 820 | 2+2 | 32K | 32K | 1M+512K | [1] | |
| 447 | * | Snapdragon 821 | 2+2 | 32K | 32K | 1M+512K | [1] | |
| 448 | * | Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K | 2M(+1M) | sysfs | |
| 449 | * +-----------------+-------+-----------+-----------+-----------+-----------+ |
| 450 | * |
| 451 | * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2 |
| 452 | */ |
| 453 | *l1i = (struct cpuinfo_cache) { |
| 454 | .size = 32 * 1024, |
| 455 | .associativity = 4 /* assume same as Krait */, |
| 456 | .line_size = 64 /* assume same as Krait */ |
| 457 | }; |
| 458 | *l1d = (struct cpuinfo_cache) { |
| 459 | .size = 32 * 1024, |
| 460 | .associativity = 4 /* assume same as Krait */, |
| 461 | .line_size = 64 /* assume same as Krait */ |
| 462 | }; |
| 463 | *l2 = (struct cpuinfo_cache) { |
| 464 | .size = uarch_cores * 512 * 1024, |
| 465 | .associativity = 16 /* sysfs-reported on Snapdragon 835 */, |
| 466 | .line_size = 64 /* assume same as Krait */ |
| 467 | }; |
| 468 | break; |
| 469 | case cpuinfo_uarch_mongoose: |
| 470 | /* |
| 471 | * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$, |
| 472 | * namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1] |
| 473 | * - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1] |
| 474 | * - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split |
| 475 | * into 4 banks and has a 22 cycle latency" [1] |
| 476 | * |
| 477 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 478 | * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | |
| 479 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 480 | * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | 2M | [1] | |
| 481 | * | Exynos 8 Octa 8895 | 4(+4) | 64K | 32K | 2M | [2] | |
| 482 | * +--------------------+-------+-----------+-----------+-----------+-----------+ |
| 483 | * |
| 484 | * [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed |
| 485 | * [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market |
| 486 | */ |
| 487 | *l1i = (struct cpuinfo_cache) { |
| 488 | .size = 64 * 1024, |
| 489 | .associativity = 4, |
| 490 | .line_size = 128 |
| 491 | }; |
| 492 | *l1d = (struct cpuinfo_cache) { |
| 493 | .size = 32 * 1024, |
| 494 | .associativity = 8, |
| 495 | .line_size = 64 |
| 496 | }; |
| 497 | *l2 = (struct cpuinfo_cache) { |
| 498 | .size = 2 * 1024 * 1024, |
| 499 | .associativity = 16, |
| 500 | .line_size = 64 |
| 501 | }; |
| 502 | break; |
| 503 | case cpuinfo_uarch_cortex_a12: |
| 504 | case cpuinfo_uarch_cortex_a17: |
| 505 | case cpuinfo_uarch_cortex_a32: |
| 506 | case cpuinfo_uarch_cortex_a35: |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 507 | case cpuinfo_uarch_cortex_a57: |
| 508 | case cpuinfo_uarch_cortex_a72: |
| 509 | case cpuinfo_uarch_cortex_a73: |
| 510 | default: |
| 511 | cpuinfo_log_warning("target uarch not recognized; using generic cache parameters"); |
| 512 | /* Follow OpenBLAS */ |
| 513 | if (arch_version >= 8) { |
| 514 | *l1i = (struct cpuinfo_cache) { |
| 515 | .size = 32 * 1024, |
| 516 | .associativity = 4, |
| 517 | .line_size = 64 |
| 518 | }; |
| 519 | *l1d = (struct cpuinfo_cache) { |
| 520 | .size = 32 * 1024, |
| 521 | .associativity = 4, |
| 522 | .line_size = 64 |
| 523 | }; |
| 524 | *l2 = (struct cpuinfo_cache) { |
| 525 | .size = uarch_cores * 256 * 1024, |
| 526 | .associativity = 8, |
| 527 | .line_size = 64 |
| 528 | }; |
| 529 | } else { |
| 530 | *l1i = (struct cpuinfo_cache) { |
| 531 | .size = 16 * 1024, |
| 532 | .associativity = 4, |
| 533 | .line_size = 32 |
| 534 | }; |
| 535 | *l1d = (struct cpuinfo_cache) { |
| 536 | .size = 16 * 1024, |
| 537 | .associativity = 4, |
| 538 | .line_size = 32 |
| 539 | }; |
| 540 | if (arch_version >= 7) { |
| 541 | *l2 = (struct cpuinfo_cache) { |
| 542 | .size = uarch_cores * 128 * 1024, |
| 543 | .associativity = 8, |
| 544 | .line_size = 32 |
| 545 | }; |
| 546 | } |
| 547 | } |
| 548 | break; |
| 549 | } |
| 550 | l1i->sets = l1i->size / (l1i->associativity * l1i->line_size); |
| 551 | l1i->partitions = 1; |
| 552 | l1d->sets = l1d->size / (l1d->associativity * l1d->line_size); |
| 553 | l1d->partitions = 1; |
| 554 | if (l2->size != 0) { |
Marat Dukhan | 8ecad1a | 2017-05-08 07:21:57 +0000 | [diff] [blame] | 555 | l2->sets = l2->size / (l2->associativity * l2->line_size); |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 556 | l2->partitions = 1; |
| 557 | } |
| 558 | } |