Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010-2011 Chia-I Wu <olvaffe@gmail.com> |
| 3 | * Copyright (C) 2010-2011 LunarG Inc. |
| 4 | * |
| 5 | * Based on xf86-video-ati, which has |
| 6 | * |
| 7 | * Copyright © 2009 Red Hat, Inc. |
| 8 | * |
| 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 10 | * copy of this software and associated documentation files (the "Software"), |
| 11 | * to deal in the Software without restriction, including without limitation |
| 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 13 | * and/or sell copies of the Software, and to permit persons to whom the |
| 14 | * Software is furnished to do so, subject to the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice shall be included |
| 17 | * in all copies or substantial portions of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 24 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 25 | * DEALINGS IN THE SOFTWARE. |
| 26 | */ |
| 27 | |
| 28 | /* XXX This driver assumes evergreen. */ |
| 29 | |
| 30 | #define LOG_TAG "GRALLOC-RADEON" |
| 31 | |
| 32 | #include <cutils/log.h> |
| 33 | #include <stdlib.h> |
| 34 | #include <errno.h> |
| 35 | #include <drm.h> |
| 36 | #include <radeon_drm.h> |
| 37 | #include <radeon_bo_gem.h> |
| 38 | #include <radeon_bo.h> |
| 39 | |
| 40 | #include "gralloc_drm.h" |
| 41 | #include "gralloc_drm_priv.h" |
| 42 | |
| 43 | #define RADEON_GPU_PAGE_SIZE 4096 |
| 44 | |
| 45 | #define MAX(a, b) (((a) > (b)) ? (a) : (b)) |
| 46 | #define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1)) |
| 47 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 48 | enum { |
| 49 | CHIP_FAMILY_R600, |
| 50 | CHIP_FAMILY_CEDAR, |
| 51 | CHIP_FAMILY_PALM, |
| 52 | CHIP_FAMILY_LAST |
| 53 | }; |
| 54 | |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 55 | struct radeon_info { |
| 56 | struct gralloc_drm_drv_t base; |
| 57 | |
| 58 | int fd; |
| 59 | struct radeon_bo_manager *bufmgr; |
| 60 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 61 | int chipset; |
| 62 | int chip_family; |
| 63 | |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 64 | uint32_t tile_config; |
| 65 | int num_channels; |
| 66 | int num_banks; |
| 67 | int group_bytes; |
| 68 | /* r6xx+ tile config */ |
| 69 | int have_tiling_info; |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 70 | |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 71 | int allow_color_tiling; |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 72 | |
| 73 | int vram_size; |
| 74 | int gart_size; |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | struct radeon_buffer { |
| 78 | struct gralloc_drm_bo_t base; |
| 79 | |
| 80 | struct radeon_bo *rbo; |
| 81 | }; |
| 82 | |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 83 | /* returns pitch alignment in pixels */ |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 84 | static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 85 | { |
| 86 | int pitch_align = 1; |
| 87 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 88 | if (info->chip_family >= CHIP_FAMILY_R600) { |
| 89 | if (tiling & RADEON_TILING_MACRO) { |
| 90 | /* general surface requirements */ |
| 91 | pitch_align = (((info->group_bytes / 8) / bpe) * |
| 92 | info->num_banks) * 8; |
| 93 | /* further restrictions for scanout */ |
| 94 | pitch_align = MAX(info->num_banks * 8, pitch_align); |
| 95 | } else if (tiling & RADEON_TILING_MICRO) { |
| 96 | /* general surface requirements */ |
| 97 | pitch_align = MAX(8, (info->group_bytes / (8 * bpe))); |
| 98 | /* further restrictions for scanout */ |
| 99 | pitch_align = MAX(info->group_bytes / bpe, pitch_align); |
| 100 | } else { |
| 101 | if (info->have_tiling_info) |
| 102 | /* linear aligned requirements */ |
| 103 | pitch_align = MAX(64, info->group_bytes / bpe); |
| 104 | else |
| 105 | /* default to 512 elements if we don't know the real |
| 106 | * group size otherwise the kernel may reject the CS |
| 107 | * if the group sizes don't match as the pitch won't |
| 108 | * be aligned properly. |
| 109 | */ |
| 110 | pitch_align = 512; |
| 111 | } |
| 112 | } |
| 113 | else { |
| 114 | /* general surface requirements */ |
| 115 | if (tiling) |
| 116 | pitch_align = 256 / bpe; |
| 117 | else |
| 118 | pitch_align = 64; |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | return pitch_align; |
| 122 | } |
| 123 | |
| 124 | /* returns height alignment in pixels */ |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 125 | static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 126 | { |
| 127 | int height_align = 1; |
| 128 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 129 | if (info->chip_family >= CHIP_FAMILY_R600) { |
| 130 | if (tiling & RADEON_TILING_MACRO) |
| 131 | height_align = info->num_channels * 8; |
| 132 | else if (tiling & RADEON_TILING_MICRO) |
| 133 | height_align = 8; |
| 134 | else |
| 135 | height_align = 8; |
| 136 | } |
| 137 | else { |
| 138 | if (tiling) |
| 139 | height_align = 16; |
| 140 | else |
| 141 | height_align = 1; |
| 142 | } |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 143 | |
| 144 | return height_align; |
| 145 | } |
| 146 | |
| 147 | /* returns base alignment in bytes */ |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 148 | static int radeon_get_base_align(struct radeon_info *info, |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 149 | int bpe, uint32_t tiling) |
| 150 | { |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 151 | int pixel_align = radeon_get_pitch_align(info, bpe, tiling); |
| 152 | int height_align = radeon_get_height_align(info, tiling); |
| 153 | int base_align = RADEON_GPU_PAGE_SIZE; |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 154 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 155 | if (info->chip_family >= CHIP_FAMILY_R600) { |
| 156 | if (tiling & RADEON_TILING_MACRO) |
| 157 | base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe, |
| 158 | pixel_align * bpe * height_align); |
| 159 | else { |
| 160 | if (info->have_tiling_info) |
| 161 | base_align = info->group_bytes; |
| 162 | else |
| 163 | /* default to 512 if we don't know the real |
| 164 | * group size otherwise the kernel may reject the CS |
| 165 | * if the group sizes don't match as the base won't |
| 166 | * be aligned properly. |
| 167 | */ |
| 168 | base_align = 512; |
| 169 | } |
| 170 | } |
| 171 | return base_align; |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | static uint32_t drm_gem_get_tiling(const struct gralloc_drm_handle_t *handle) |
| 175 | { |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 176 | /* tiling must be disabled for CPU access */ |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static struct gralloc_drm_bo_t * |
| 181 | drm_gem_radeon_alloc(struct gralloc_drm_drv_t *drv, struct gralloc_drm_handle_t *handle) |
| 182 | { |
| 183 | struct radeon_info *info = (struct radeon_info *) drv; |
| 184 | struct radeon_buffer *rbuf; |
| 185 | uint32_t tiling, domain; |
| 186 | int cpp; |
| 187 | |
| 188 | tiling = drm_gem_get_tiling(handle); |
| 189 | domain = RADEON_GEM_DOMAIN_VRAM; |
| 190 | cpp = gralloc_drm_get_bpp(handle->format); |
| 191 | if (!cpp) { |
| 192 | LOGE("unrecognized format 0x%x", handle->format); |
| 193 | return NULL; |
| 194 | } |
| 195 | |
| 196 | rbuf = calloc(1, sizeof(*rbuf)); |
| 197 | if (!rbuf) |
| 198 | return NULL; |
| 199 | |
| 200 | |
| 201 | if (handle->name) { |
| 202 | rbuf->rbo = radeon_bo_open(info->bufmgr, handle->name, |
| 203 | 0, 0, domain, 0); |
| 204 | if (!rbuf->rbo) { |
| 205 | LOGE("failed to create rbo from name %u", |
| 206 | handle->name); |
| 207 | free(rbuf); |
| 208 | return NULL; |
| 209 | } |
| 210 | } |
| 211 | else { |
| 212 | int aligned_width, aligned_height; |
| 213 | int pitch, size, base_align; |
| 214 | |
| 215 | if (handle->usage & (GRALLOC_USAGE_HW_FB | |
| 216 | GRALLOC_USAGE_HW_TEXTURE)) { |
| 217 | aligned_width = ALIGN(handle->width, |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 218 | radeon_get_pitch_align(info, cpp, tiling)); |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 219 | aligned_height = ALIGN(handle->height, |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 220 | radeon_get_height_align(info, tiling)); |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 221 | } |
| 222 | else { |
| 223 | aligned_width = handle->width; |
| 224 | aligned_height = handle->height; |
| 225 | } |
| 226 | |
| 227 | if (!(handle->usage & (GRALLOC_USAGE_HW_FB | |
| 228 | GRALLOC_USAGE_HW_RENDER)) && |
| 229 | (handle->usage & GRALLOC_USAGE_SW_READ_OFTEN)) |
| 230 | domain = RADEON_GEM_DOMAIN_GTT; |
| 231 | |
| 232 | pitch = aligned_width * cpp; |
| 233 | size = ALIGN(aligned_height * pitch, RADEON_GPU_PAGE_SIZE); |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 234 | base_align = radeon_get_base_align(info, cpp, tiling); |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 235 | |
| 236 | rbuf->rbo = radeon_bo_open(info->bufmgr, 0, |
| 237 | size, base_align, domain, 0); |
| 238 | if (!rbuf->rbo) { |
| 239 | LOGE("failed to allocate rbo %dx%dx%d", |
| 240 | handle->width, handle->height, cpp); |
| 241 | free(rbuf); |
| 242 | return NULL; |
| 243 | } |
| 244 | |
| 245 | if (tiling) |
| 246 | radeon_bo_set_tiling(rbuf->rbo, tiling, pitch); |
| 247 | |
| 248 | if (radeon_gem_get_kernel_name(rbuf->rbo, |
| 249 | (uint32_t *) &handle->name)) { |
| 250 | LOGE("failed to flink rbo"); |
| 251 | radeon_bo_unref(rbuf->rbo); |
| 252 | free(rbuf); |
| 253 | return NULL; |
| 254 | } |
| 255 | |
| 256 | handle->stride = pitch; |
| 257 | } |
| 258 | |
| 259 | if (handle->usage & GRALLOC_USAGE_HW_FB) |
| 260 | rbuf->base.fb_handle = rbuf->rbo->handle; |
| 261 | |
| 262 | rbuf->base.handle = handle; |
| 263 | |
| 264 | return &rbuf->base; |
| 265 | } |
| 266 | |
| 267 | static void drm_gem_radeon_free(struct gralloc_drm_drv_t *drv, |
| 268 | struct gralloc_drm_bo_t *bo) |
| 269 | { |
| 270 | struct radeon_buffer *rbuf = (struct radeon_buffer *) bo; |
| 271 | radeon_bo_unref(rbuf->rbo); |
| 272 | } |
| 273 | |
| 274 | static int drm_gem_radeon_map(struct gralloc_drm_drv_t *drv, |
| 275 | struct gralloc_drm_bo_t *bo, int x, int y, int w, int h, |
| 276 | int enable_write, void **addr) |
| 277 | { |
| 278 | struct radeon_buffer *rbuf = (struct radeon_buffer *) bo; |
| 279 | int err; |
| 280 | |
| 281 | err = radeon_bo_map(rbuf->rbo, enable_write); |
| 282 | if (!err) |
| 283 | *addr = rbuf->rbo->ptr; |
| 284 | |
| 285 | return err; |
| 286 | } |
| 287 | |
| 288 | static void drm_gem_radeon_unmap(struct gralloc_drm_drv_t *drv, |
| 289 | struct gralloc_drm_bo_t *bo) |
| 290 | { |
| 291 | struct radeon_buffer *rbuf = (struct radeon_buffer *) bo; |
| 292 | radeon_bo_unmap(rbuf->rbo); |
| 293 | } |
| 294 | |
| 295 | static void drm_gem_radeon_init_kms_features(struct gralloc_drm_drv_t *drv, |
| 296 | struct gralloc_drm_t *drm) |
| 297 | { |
Chia-I Wu | e59db8f | 2011-07-10 23:12:26 +0800 | [diff] [blame] | 298 | drm->fb_format = HAL_PIXEL_FORMAT_BGRA_8888; |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 299 | drm->mode_dirty_fb = 0; |
| 300 | drm->swap_mode = DRM_SWAP_FLIP; |
| 301 | drm->mode_sync_flip = 1; |
| 302 | drm->swap_interval = 1; |
| 303 | drm->vblank_secondary = 0; |
| 304 | } |
| 305 | |
| 306 | static void drm_gem_radeon_destroy(struct gralloc_drm_drv_t *drv) |
| 307 | { |
| 308 | struct radeon_info *info = (struct radeon_info *) drv; |
| 309 | |
| 310 | radeon_bo_manager_gem_dtor(info->bufmgr); |
| 311 | free(info); |
| 312 | } |
| 313 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 314 | static int radeon_init_tile_config(struct radeon_info *info) |
| 315 | { |
| 316 | struct drm_radeon_info ginfo; |
| 317 | uint32_t val; |
| 318 | int ret; |
| 319 | |
| 320 | memset(&ginfo, 0, sizeof(ginfo)); |
| 321 | ginfo.request = RADEON_INFO_TILING_CONFIG; |
| 322 | ginfo.value = (long) &val; |
| 323 | ret = drmCommandWriteRead(info->fd, DRM_RADEON_INFO, |
| 324 | &ginfo, sizeof(ginfo)); |
| 325 | if (ret) |
| 326 | return ret; |
| 327 | |
| 328 | info->tile_config = val; |
| 329 | |
| 330 | if (info->chip_family >= CHIP_FAMILY_CEDAR) { |
| 331 | switch (info->tile_config & 0xf) { |
| 332 | case 0: |
| 333 | info->num_channels = 1; |
| 334 | break; |
| 335 | case 1: |
| 336 | info->num_channels = 2; |
| 337 | break; |
| 338 | case 2: |
| 339 | info->num_channels = 4; |
| 340 | break; |
| 341 | case 3: |
| 342 | info->num_channels = 8; |
| 343 | break; |
| 344 | default: |
| 345 | return -EINVAL; |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | switch ((info->tile_config & 0xf0) >> 4) { |
| 350 | case 0: |
| 351 | info->num_banks = 4; |
| 352 | break; |
| 353 | case 1: |
| 354 | info->num_banks = 8; |
| 355 | break; |
| 356 | case 2: |
| 357 | info->num_banks = 16; |
| 358 | break; |
| 359 | default: |
| 360 | return -EINVAL; |
| 361 | break; |
| 362 | } |
| 363 | |
| 364 | switch ((info->tile_config & 0xf00) >> 8) { |
| 365 | case 0: |
| 366 | info->group_bytes = 256; |
| 367 | break; |
| 368 | case 1: |
| 369 | info->group_bytes = 512; |
| 370 | break; |
| 371 | default: |
| 372 | return -EINVAL; |
| 373 | break; |
| 374 | } |
| 375 | } |
| 376 | else { |
| 377 | switch ((info->tile_config & 0xe) >> 1) { |
| 378 | case 0: |
| 379 | info->num_channels = 1; |
| 380 | break; |
| 381 | case 1: |
| 382 | info->num_channels = 2; |
| 383 | break; |
| 384 | case 2: |
| 385 | info->num_channels = 4; |
| 386 | break; |
| 387 | case 3: |
| 388 | info->num_channels = 8; |
| 389 | break; |
| 390 | default: |
| 391 | return -EINVAL; |
| 392 | break; |
| 393 | } |
| 394 | |
| 395 | switch ((info->tile_config & 0x30) >> 4) { |
| 396 | case 0: |
| 397 | info->num_banks = 4; |
| 398 | break; |
| 399 | case 1: |
| 400 | info->num_banks = 8; |
| 401 | break; |
| 402 | default: |
| 403 | return -EINVAL; |
| 404 | break; |
| 405 | } |
| 406 | |
| 407 | switch ((info->tile_config & 0xc0) >> 6) { |
| 408 | case 0: |
| 409 | info->group_bytes = 256; |
| 410 | break; |
| 411 | case 1: |
| 412 | info->group_bytes = 512; |
| 413 | break; |
| 414 | default: |
| 415 | return -EINVAL; |
| 416 | break; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | info->have_tiling_info = 1; |
| 421 | |
| 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | static int radeon_probe(struct radeon_info *info) |
| 426 | { |
| 427 | struct drm_radeon_info kinfo; |
| 428 | struct drm_radeon_gem_info mminfo; |
| 429 | int err; |
| 430 | |
| 431 | memset(&kinfo, 0, sizeof(kinfo)); |
| 432 | kinfo.request = RADEON_INFO_DEVICE_ID; |
| 433 | kinfo.value = (long) &info->chipset; |
| 434 | err = drmCommandWriteRead(info->fd, DRM_RADEON_INFO, &kinfo, sizeof(kinfo)); |
| 435 | if (err) |
| 436 | return err; |
| 437 | |
| 438 | /* XXX this is wrong and a table should be used */ |
| 439 | if (info->chipset >= 0x68e4 && info->chipset <= 0x68fe) |
| 440 | info->chip_family = CHIP_FAMILY_CEDAR; |
| 441 | else if (info->chipset >= 0x9802 && info->chipset <= 0x9807) |
| 442 | info->chip_family = CHIP_FAMILY_PALM; |
| 443 | else |
| 444 | return -EINVAL; |
| 445 | |
| 446 | err = radeon_init_tile_config(info); |
| 447 | if (err) |
| 448 | return err; |
| 449 | |
| 450 | info->allow_color_tiling = |
| 451 | (info->chip_family != CHIP_FAMILY_CEDAR); |
| 452 | |
| 453 | memset(&mminfo, 0, sizeof(mminfo)); |
| 454 | err = drmCommandWriteRead(info->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)); |
| 455 | if (err) |
| 456 | return err; |
| 457 | |
| 458 | info->vram_size = mminfo.vram_visible; |
| 459 | info->gart_size = mminfo.gart_size; |
| 460 | |
| 461 | LOGI("detected chip family %s (vram size %dMiB, gart size %dMiB)", |
| 462 | (info->chip_family == CHIP_FAMILY_CEDAR) ? |
| 463 | "CEDAR" : "PALM", |
| 464 | info->vram_size / 1024 / 1024, |
| 465 | info->gart_size / 1024 / 1024); |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 470 | struct gralloc_drm_drv_t *gralloc_drm_drv_create_for_radeon(int fd) |
| 471 | { |
| 472 | struct radeon_info *info; |
| 473 | |
| 474 | info = calloc(1, sizeof(*info)); |
| 475 | if (!info) |
| 476 | return NULL; |
| 477 | |
| 478 | info->fd = fd; |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 479 | if (radeon_probe(info)) { |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 480 | free(info); |
| 481 | return NULL; |
| 482 | } |
| 483 | |
Chia-I Wu | 896fbd1 | 2011-07-14 14:42:30 +0800 | [diff] [blame^] | 484 | info->bufmgr = radeon_bo_manager_gem_ctor(info->fd); |
| 485 | if (!info->bufmgr) { |
| 486 | LOGE("failed to create buffer manager"); |
Chia-I Wu | 2ec32d4 | 2011-06-12 16:21:30 +0800 | [diff] [blame] | 487 | free(info); |
| 488 | return NULL; |
| 489 | } |
| 490 | |
| 491 | info->base.destroy = drm_gem_radeon_destroy; |
| 492 | info->base.init_kms_features = drm_gem_radeon_init_kms_features; |
| 493 | info->base.alloc = drm_gem_radeon_alloc; |
| 494 | info->base.free = drm_gem_radeon_free; |
| 495 | info->base.map = drm_gem_radeon_map; |
| 496 | info->base.unmap = drm_gem_radeon_unmap; |
| 497 | |
| 498 | return &info->base; |
| 499 | } |