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gerrit-public.fairphone.software / platform / external / elfutils / 96a739922f7bc651ecfacaf9c70168b015ec5e96 / . / libcpu / defs / i386
blob: b545c48160f0594f8339fe1e4ec54f6082af5a26 [file] [log] [blame]
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1%mask {s} 1
2%mask {w} 1
3%mask {w1} 1
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]4%mask {W1} 1
5%mask {W2} 1
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]6dnl floating point reg suffix
7%mask {D} 1
8%mask {imm8} 8
9%mask {imms8} 8
10%mask {imm16} 16
11%mask {reg} 3
12%mask {reg16} 3
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]13%mask {reg64} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]14%mask {tttn} 4
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]15%mask {mod} 2
16%mask {moda} 2
17%mask {MOD} 2
18%mask {r_m} 3
19dnl like {r_m} but referencing byte register
20%mask {8r_m} 3
21dnl like {r_m} but referencing 16-bit register
22%mask {16r_m} 3
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]23dnl like {r_m} but referencing 32- or 64-bit register
24%mask {64r_m} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]25%mask {disp8} 8
26dnl imm really is 8/16/32 bit depending on the situation.
27%mask {imm} 8
28%mask {imms} 8
29%mask {rel} 32
30%mask {abs} 32
31%mask {absval} 32
32%mask {sel} 16
33%mask {imm32} 32
34%mask {ccc} 3
35%mask {ddd} 3
36%mask {sreg3} 3
37%mask {sreg2} 2
38%mask {mmxreg} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]39%mask {R_M} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]40%mask {Mod} 2
41%mask {xmmreg} 3
42%mask {R_m} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]43%mask {xmmreg1} 3
44%mask {xmmreg2} 3
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]45%mask {mmxreg1} 3
46%mask {mmxreg2} 3
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]47%mask {predps} 8
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]48%mask {freg} 3
49%mask {fmod} 2
50%mask {fr_m} 3
51%prefix {R}
52%prefix {RE}
53%suffix {W}
54%suffix {w0}
55%synonym {xmmreg1} {xmmreg}
56%synonym {xmmreg2} {xmmreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]57%synonym {mmxreg1} {mmxreg}
58%synonym {mmxreg2} {mmxreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]59
60%%
61ifdef(`i386',
62`00110111:aaa
6311010101,00001010:aad
6411010100,00001010:aam
6500111111:aas
66')dnl
670001010{w},{imm}:adc {imm}{w},{ax}{w}
681000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w}
691000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]700001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}{w}
710001001{w},{mod}{reg}{r_m}:adc {mod}{r_m}{w},{reg}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]720000010{w},{imm}:add {imm}{w},{ax}{w}
731000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepper96a73992008-01-11 06:17:06 +0000[diff] [blame^]7410000011,{mod}000{r_m},{imms8}:add{w} {imms8},{mod}{r_m}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]750000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}{w}
760000001{w},{mod}{reg}{r_m}:add {mod}{r_m}{w},{reg}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]7701100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg}
7811110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg}
790010010{w},{imm}:and {imm}{w},{ax}{w}
801000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]811000001{w},{mod}100{r_m},{imms8}:and{w} {imms8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]820010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w}
830010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w}
8401100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
8500001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
8601100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
8700001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
88ifdef(`i386',
89`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m}
9001100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]91',
92`01100011,{mod}{reg64}{r_m}:movslq {mod}{r_m},{reg64}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]93')dnl
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]9400001111,10111100,{mod}{reg}{r_m}:bsf {mod}{r_m},{reg}
9500001111,10111101,{mod}{reg}{r_m}:bsr {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9600001111,11001{reg}:bswap {reg}
9700001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]9800001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]9900001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]10000001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]10100001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]10200001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]10300001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]10400001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]10511101000,{rel}:call{W} {rel}
10611111111,{mod}010{64r_m}:call{W} *{mod}{64r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]107ifdef(`i386',
108`10011010,{absval},{sel}:lcall {sel},{absval}
109')dnl
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]11011111111,{mod}011{64r_m}:lcall{W} *{mod}{64r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]111# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl]
11210011000:INVALID
113# SPECIAL 10011001:[{rew.w}?cqto:{dpfx}?cltd:cwtd]
11410011001:INVALID
11511111000:clc
11611111100:cld
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]11711111010:cli
11800001111,00000101:syscall
11900001111,00000110:clts
12000001111,00000111:sysret
12100001111,00110100:sysenter
12200001111,00110101:sysexit
12311110101:cmc
12400001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg}
1250011110{w},{imm}:cmp {imm}{w},{ax}{w}
1261000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepper96a73992008-01-11 06:17:06 +0000[diff] [blame^]12710000011,{mod}111{r_m},{imms8}:cmp{w} {imms8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1280011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w}
1290011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]130ifdef(`ASSEMBLER',
131`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]13211110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
13301100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg}
13400001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]135',
136`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
13711110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
13801100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
13900001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
140')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1411010011{w}:{RE}cmps{w} {es_di},{ds_si}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]14200001111,1011000{w},{mod}{reg}{r_m}:cmpxchg {reg}{w},{mod}{r_m}{w}
143ifdef(`i386',
144`00001111,11000111,{mod}001{r_m}:cmpxchg8b {mod}{r_m}
145',
146`# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m}
14700001111,11000111,{mod}001{r_m}:INVALID {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]148')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]14900001111,10100010:cpuid
15011110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]15111110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]15201100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]153ifdef(`i386',
154`00100111:daa
15500101111:das
156')dnl
1571111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w}
158ifdef(`i386',
159`01001{reg}:dec {reg}
160')dnl
1611111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]16200001111,01110111:emms
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]16311001000,{imm16},{imm8}:enter{W} {imm16},{imm8}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]16411011001,11010000:fnop
16511011001,11100000:fchs
16611011001,11100001:fabs
16711011001,11100100:ftst
16811011001,11100101:fxam
16911011001,11101000:fld1
17011011001,11101001:fldl2t
17111011001,11101010:fldl2e
17211011001,11101011:fldpi
17311011001,11101100:fldlg2
17411011001,11101101:fldln2
17511011001,11101110:fldz
17611011001,11110000:f2xm1
17711011001,11110001:fyl2x
17811011001,11110010:fptan
17911011001,11110011:fpatan
18011011001,11110100:fxtract
18111011001,11110101:fprem1
18211011001,11110110:fdecstp
18311011001,11110111:fincstp
18411011001,11111000:fprem
18511011001,11111001:fyl2xp1
18611011001,11111010:fsqrt
18711011001,11111011:fsincos
18811011001,11111100:frndint
18911011001,11111101:fscale
19011011001,11111110:fsin
19111011001,11111111:fcos
192# ORDER
19311011000,11000{freg}:fadd {freg},%st
19411011100,11000{freg}:fadd %st,{freg}
19511011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m}
196# ORDER END
197# ORDER
19811011000,11001{freg}:fmul {freg},%st
19911011100,11001{freg}:fmul %st,{freg}
20011011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m}
201# ORDER END
202# ORDER
20311011000,11100{freg}:fsub {freg},%st
20411011100,11100{freg}:fsub %st,{freg}
20511011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m}
206# ORDER END
207# ORDER
20811011000,11101{freg}:fsubr {freg},%st
20911011100,11101{freg}:fsubr %st,{freg}
21011011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m}
211# ORDER END
212# ORDER
21311011101,11010{freg}:fst {freg}
21411011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m}
215# ORDER END
216# ORDER
21711011101,11011{freg}:fstp {freg}
21811011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m}
219# ORDER END
22011011001,{mod}100{r_m}:fldenv {mod}{r_m}
22111011001,{mod}101{r_m}:fldcw {mod}{r_m}
22211011001,{mod}110{r_m}:fnstenv {mod}{r_m}
22311011001,{mod}111{r_m}:fnstcw {mod}{r_m}
22411011001,11001{freg}:fxch {freg}
225# ORDER
22611011110,11000{freg}:faddp %st,{freg}
227ifdef(`ASSEMBLER',
228`11011110,11000001:faddp
229')dnl
230# ORDER
23111011010,11000{freg}:fcmovb {freg},%st
23211011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m}
233# ORDER END
234# ORDER
23511011010,11001{freg}:fcmove {freg},%st
23611011110,11001{freg}:fmulp %st,{freg}
23711011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m}
238# ORDER END
239# ORDER
24011011110,11100{freg}:fsubp %st,{freg}
24111011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m}
242# ORDER END
243# ORDER
24411011110,11101{freg}:fsubrp %st,{freg}
24511011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m}
246# ORDER END
247# ORDER
24811011111,11100000:fnstsw %ax
24911011111,{mod}100{r_m}:fbld {mod}{r_m}
250# ORDER END
251# ORDER
25211011111,11110{freg}:fcomip {freg},%st
25311011111,{mod}110{r_m}:fbstp {mod}{r_m}
254# ORDER END
25511011001,11100000:fchs
256# ORDER
25710011011,11011011,11100010:fclex
25810011011,11011011,11100011:finit
25910011011:fwait
260# END ORDER
26111011011,11100010:fnclex
26211011010,11000{freg}:fcmovb {freg},%st
26311011010,11001{freg}:fcmove {freg},%st
26411011010,11010{freg}:fcmovbe {freg},%st
26511011010,11011{freg}:fcmovu {freg},%st
26611011011,11000{freg}:fcmovnb {freg},%st
26711011011,11001{freg}:fcmovne {freg},%st
26811011011,11010{freg}:fcmovnbe {freg},%st
26911011011,11011{freg}:fcmovnu {freg},%st
270# ORDER
27111011000,11010{freg}:fcom {freg}
272ifdef(`ASSEMBLER',
273`11011000,11010001:fcom
274')dnl
27511011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m}
276# END ORDER
277# ORDER
27811011000,11011{freg}:fcomp {freg}
279ifdef(`ASSEMBLER',
280`11011000,11011001:fcomp
281')dnl
28211011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m}
283# END ORDER
28411011110,11011001:fcompp
28511011011,11110{freg}:fcomi {freg},%st
28611011111,11110{freg}:fcomip {freg},%st
28711011011,11101{freg}:fucomi {freg},%st
28811011111,11101{freg}:fucomip {freg},%st
28911011001,11111111:fcos
29011011001,11110110:fdecstp
291# ORDER
29211011000,11110{freg}:fdiv {freg},%st
29311011100,11110{freg}:fdiv %st,{freg}
29411011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m}
295# END ORDER
29611011010,{mod}110{r_m}:fidivl {mod}{r_m}
297# ORDER
29811011110,11110{freg}:fdivp %st,{freg}
29911011110,{mod}110{r_m}:fidiv {mod}{r_m}
300# END ORDER
30111011110,11111{freg}:fdivrp %st,{freg}
302ifdef(`ASSEMBLER',
303`11011110,11111001:fdivp
304')dnl
305# ORDER
30611011000,11111{freg}:fdivr {freg},%st
30711011100,11111{freg}:fdivr %st,{freg}
30811011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
309# END ORDER
31011011010,{mod}111{r_m}:fidivrl {mod}{r_m}
31111011110,{mod}111{r_m}:fidivr {mod}{r_m}
31211011110,11110{freg}:fdivrp %st,{freg}
313ifdef(`ASSEMBLER',
314`11011110,11110001:fdivrp
315')dnl
31611011101,11000{freg}:ffree {freg}
31711011010,11010{freg}:fcmovbe {freg}
31811011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m}
31911011010,11011{freg}:fcmovu {freg}
32011011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m}
32111011111,{mod}000{r_m}:fild {mod}{r_m}
32211011011,{mod}000{r_m}:fildl {mod}{r_m}
32311011111,{mod}101{r_m}:fildll {mod}{r_m}
32411011001,11110111:fincstp
32511011011,11100011:fninit
32611011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m}
32711011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m}
32811011111,{mod}111{r_m}:fistpll {mod}{r_m}
32911011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m}
33011011101,{mod}001{r_m}:fisttpll {mod}{r_m}
33111011011,{mod}101{r_m}:fldt {mod}{r_m}
33211011011,{mod}111{r_m}:fstpt {mod}{r_m}
333# ORDER
33411011001,11000{freg}:fld {freg}
33511011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m}
336# ORDER END
337# ORDER
33811011101,11100{freg}:fucom {freg}
33911011101,{mod}100{r_m}:frstor {mod}{r_m}
340# ORDER END
34111011101,11101{freg}:fucomp {freg}
34211011101,{mod}110{r_m}:fnsave {mod}{r_m}
34311011101,{mod}111{r_m}:fnstsw {mod}{r_m}
344#
345#
346#
34711110100:hlt
3481111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w}
3491111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]35000001111,10101111,{mod}{reg}{r_m}:imul {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]351011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg}
3521110010{w},{imm8}:in {imm8},{ax}{w}
3531110110{w}:in {dx},{ax}{w}
3541111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w}
35501000{reg}:inc {reg}
3560110110{w}:{R}ins{w} {dx},{es_di}
35711001101,{imm8}:int {imm8}
35811001100:int3
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]359ifdef(`i386',
360`11001110:into
361')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]36200001111,00001000:invd
363# ORDER
36400001111,00000001,11111000:swapgs
36500001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m}
366# ORDER END
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]36711001111:iret{W1}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]3680111{tttn},{disp8}:j{tttn} {disp8}
36900001111,1000{tttn},{rel}:j{tttn} {rel}
37000001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m}
371# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8}
37211100011,{disp8}:INVALID {disp8}
37311101011,{disp8}:jmp {disp8}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]37411101001,{rel}:jmp{W} {rel}
37511111111,{mod}100{64r_m}:jmp{W} *{mod}{64r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]37611101010,{absval},{sel}:ljmp {sel},{absval}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]37711111111,{mod}101{64r_m}:ljmp{W} *{mod}{64r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]37810011111:lahf
37900001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]380ifdef(`i386',
381`11000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg}
382')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]38310001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]38411001001:leave{W}
385ifdef(`i386',
386`11000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg}
387')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]38800001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]38900001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]390ifdef(`i386',
391`00001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]39200001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]393',
394`00001111,00000001,{mod}010{r_m}:lgdt {mod}{r_m}
39500001111,00000001,{mod}011{r_m}:lidt {mod}{r_m}
396')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]39700001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m}
39800001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m}
39911110000:lock
4001010110{w}:{R}lods {ds_si},{ax}{w}
40111100010,{disp8}:loop {disp8}
40211100001,{disp8}:loope {disp8}
40311100000,{disp8}:loopne {disp8}
40400001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg}
40500001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg}
40600001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m}
4071000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w}
4081000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w}
4091100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w}
4101011{w}{reg},{imm}:mov {imm}{w},{reg}{w}
4111010000{w},{abs}:mov {abs},{ax}{w}
4121010001{w},{abs}:mov {ax}{w},{abs}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]41300001111,00100000,11{ccc}{reg64}:mov {ccc},{reg64}
41400001111,00100010,11{ccc}{reg64}:mov {reg64},{ccc}
41500001111,00100001,11{ddd}{reg64}:mov {ddd},{reg64}
41600001111,00100011,11{ddd}{reg64}:mov {reg64},{ddd}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]41710001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m}
41810001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3}
4191010010{w}:{R}movs{w} {ds_si},{es_di}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]42000001111,10111110,{mod}{reg}{8r_m}:movsbl {mod}{8r_m},{reg}
42100001111,10111111,{mod}{reg}{16r_m}:movswl {mod}{16r_m},{reg}
42200001111,10110110,{mod}{reg}{8r_m}:movzbl {mod}{8r_m},{reg}
42300001111,10110111,{mod}{reg}{16r_m}:movzwl {mod}{16r_m},{reg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]4241111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w}
4251111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]42611110011,10010000:pause
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]42710010000:nop
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]4281111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w}
4290000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w}
4300000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w}
4311000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepper96a73992008-01-11 06:17:06 +0000[diff] [blame^]4321000001{w},{mod}001{r_m},{imms8}:or{w} {imms8},{mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]4330000110{w},{imm}:or {imm}{w},{ax}{w}
4341110011{w},{imm8}:out {ax}{w},{imm8}
4351110111{w}:out {ax}{w},{dx}
4360110111{w}:{R}outs{w} {ds_si},{dx}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]437ifdef(`i386',
438`10001111,{mod}000{r_m}:pop{w} {mod}{r_m}
439',
440# XXX This is not the cleanest way...
441`10001111,11000{reg64}:pop {reg64}
44210001111,{mod}000{r_m}:pop{W} {mod}{r_m}
443')dnl
44400001111,10{sreg3}001:pop{W} {sreg3}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]44510011101:popf{W}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]446# XXX This is not the cleanest way...
447ifdef(`i386',
448`11111111,{mod}110{r_m}:push{w} {mod}{r_m}
449',
450`11111111,11110{reg64}:push {reg64}
45111111111,{mod}110{r_m}:pushq {mod}{r_m}
452')dnl
453ifdef(`i386',
454`01010{reg}:push {reg}
45501011{reg}:pop {reg}
456',
457`01010{reg64}:push {reg64}
45801011{reg64}:pop {reg64}
459')dnl
460011010{s}0,{imm}:push{W} {imm}{s}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]461000{sreg2}110:push {sreg2}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]46200001111,10{sreg3}000:push{W} {sreg3}
463ifdef(`i386',
464`01100000:pusha{W}
46501100001:popa{W}
466')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]46710011100:pushf{W}
4681101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
4691101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
4701100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
4711101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w}
4721101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w}
4731100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w}
47400001111,00110010:rdmsr
47500001111,00110011:rdpmc
47600001111,00110001:rdtsc
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]47711000011:ret{W}
47811000010,{imm16}:ret{W} {imm16}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]47911001011:lret
48011001010,{imm16}:lret {imm16}
4811101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w}
4821101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w}
4831100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w}
4841101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w}
4851101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w}
4861100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w}
48700001111,10101010:rsm
48810011110:sahf
4891101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w}
4901101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w}
4911100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w}
4920001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w}
4930001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w}
4940001110{w},{imm}:sbb {imm}{w},{ax}{w}
4951000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]4961000001{w},{mod}011{r_m},{imms8}:sbb{w} {imms8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]4971010111{w}:{RE}scas {es_di},{ax}{w}
49800001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m}
4991101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w}
5001101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w}
5011100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w}
5021101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w}
50300001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m}
50400001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m}
5051101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w}
5061100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w}
50700001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m}
50800001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m}
509# ORDER
51000001111,00000001,11000001:vmcall
51100001111,00000001,11000010:vmlaunch
51200001111,00000001,11000011:vmresume
51300001111,00000001,11000100:vmxoff
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]51400001111,01111000,{mod}{reg64}{64r_m}:vmread {reg64},{mod}{64r_m}
51500001111,01111001,{mod}{reg64}{64r_m}:vmwrite {mod}{64r_m},{reg64}
516ifdef(`i386',
517`00001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m}
518',
519`00001111,00000001,{mod}000{r_m}:sgdt {mod}{r_m}
520')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]521# ORDER END
522# ORDER
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]523ifdef(`i386',
524`00001111,00000001,11001000:monitor %eax,%ecx,%edx
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]52500001111,00000001,11001001:mwait %eax,%ecx
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]526',
527`00001111,00000001,11001000:monitor %rax,%rcx,%rdx
52800001111,00000001,11001001:mwait %rax,%rcx
529')dnl
530ifdef(`i386',
531`00001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m}
532',
533`00001111,00000001,{mod}001{r_m}:sidt {mod}{r_m}
534')dnl
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]535# ORDER END
53600001111,00000000,{mod}000{r_m}:sldt {mod}{r_m}
53700001111,00000001,{mod}100{r_m}:smsw {mod}{r_m}
53811111001:stc
53911111101:std
54011111011:sti
5411010101{w}:{R}stos {ax}{w},{es_di}
54200001111,00000000,{mod}001{r_m}:str {mod}{r_m}
5430010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w}
5440010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w}
5450010110{w},{imm}:sub {imm}{w},{ax}{w}
5461000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]5471000001{w},{mod}101{r_m},{imms8}:sub{w} {imms8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]5481000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w}
5491010100{w},{imm}:test {imm}{w},{ax}{w}
5501111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w}
55100001111,00001011:ud2a
55200001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m}
55300001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m}
55400001111,00001001:wbinvd
55500001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m}
55600001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m}
55700001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m}
55800001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m}
55900001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m}
56000001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m}
56100001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]56200001111,00110000:wrmsr
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]56300001111,1100000{w},{mod}{reg}{r_m}:xadd {reg}{w},{mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]5641000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w}
56510010{reg}:xchg {ax},{reg}
56611010111:xlat {ds_bx}
5670011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w}
5680011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w}
5690011010{w},{imm}:xor {imm}{w},{ax}{w}
5701000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w}
Ulrich Drepperff993222008-01-09 05:39:28 +0000[diff] [blame]5711000001{w},{mod}110{r_m},{imms8}:xor{w} {imms8},{mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]57200001111,01110111:emms
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]57301100110,00001111,11011011,{Mod}{xmmreg}{R_m}:pand {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]57400001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]57501100110,00001111,11011111,{Mod}{xmmreg}{R_m}:pandn {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]57600001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]57701100110,00001111,11110101,{Mod}{xmmreg}{R_m}:pmaddwd {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]57800001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]57901100110,00001111,11101011,{Mod}{xmmreg}{R_m}:por {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]58000001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]58101100110,00001111,11101111,{Mod}{xmmreg}{R_m}:pxor {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]58200001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]58300001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
58400001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
58500001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg}
58600001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg}
58700001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg}
58800001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg}
58900001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg}
59000001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg}
59100001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg}
59200001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg}
59311110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg}
59411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg}
59511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg}
59611110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg}
59711110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg}
59811110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg}
59911110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg}
60011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]60100001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m}
60200001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m}
60300001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]60400001111,10101110,{mod}011{r_m}:stmxcsr {mod}{r_m}
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]60511110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg}
60611110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg}
60701100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg}
60800001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg}
60911110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m}
61011110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m}
61101100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m}
61200001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m}
61311110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg}
61411110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg}
61501100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg}
61600001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1}
61700001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg}
61801100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2}
61900001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2}
62001100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m}
62100001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m}
62201100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg}
62300001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg}
62401100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg}
62500001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg}
62611110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg}
62701100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg}
62800001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1}
62900001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg}
63001100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2}
63100001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2}
63201100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m}
63300001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m}
63401100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg}
63500001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg}
63601100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m}
63700001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m}
63811110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg}
63911110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg}
64001100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg}
64100001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg}
64201100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m}
64300001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m}
64411110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg}
64511110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg}
64601100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg}
64700001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg}
64801100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg}
64911110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg}
65011110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg}
65100001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg}
65201100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg}
65300001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg}
65401100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg}
65500001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]65600001111,00110111:getsec
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]65701100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg}
65800001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg}
65901100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg}
66011110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg}
66111110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg}
66200001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg}
66311110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg}
66400001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg}
66511110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg}
66600001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg}
Ulrich Drepperee67b642008-01-03 08:45:10 +0000[diff] [blame]66701100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
66800001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
66901100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
67000001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
67101100110,00001111,01010110,{Mod}{xmmreg}{R_m}:orpd {Mod}{R_m},{xmmreg}
67200001111,01010110,{Mod}{xmmreg}{R_m}:orps {Mod}{R_m},{xmmreg}
67301100110,00001111,01010111,{Mod}{xmmreg}{R_m}:xorpd {Mod}{R_m},{xmmreg}
67400001111,01010111,{Mod}{xmmreg}{R_m}:xorps {Mod}{R_m},{xmmreg}
67511110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg}
67611110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg}
67701100110,00001111,01011000,{Mod}{xmmreg}{R_m}:addpd {Mod}{R_m},{xmmreg}
67800001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg}
67911110010,00001111,01011001,{Mod}{xmmreg}{R_m}:mulsd {Mod}{R_m},{xmmreg}
68011110011,00001111,01011001,{Mod}{xmmreg}{R_m}:mulss {Mod}{R_m},{xmmreg}
68101100110,00001111,01011001,{Mod}{xmmreg}{R_m}:mulpd {Mod}{R_m},{xmmreg}
68200001111,01011001,{Mod}{xmmreg}{R_m}:mulps {Mod}{R_m},{xmmreg}
68311110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg}
68411110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg}
68501100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg}
68600001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg}
68701100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg}
68811110011,00001111,01011011,{Mod}{xmmreg}{R_m}:cvttps2dq {Mod}{R_m},{xmmreg}
68900001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg}
69011110010,00001111,01011100,{Mod}{xmmreg}{R_m}:subsd {Mod}{R_m},{xmmreg}
69111110011,00001111,01011100,{Mod}{xmmreg}{R_m}:subss {Mod}{R_m},{xmmreg}
69201100110,00001111,01011100,{Mod}{xmmreg}{R_m}:subpd {Mod}{R_m},{xmmreg}
69300001111,01011100,{Mod}{xmmreg}{R_m}:subps {Mod}{R_m},{xmmreg}
69411110010,00001111,01011101,{Mod}{xmmreg}{R_m}:minsd {Mod}{R_m},{xmmreg}
69511110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg}
69601100110,00001111,01011101,{Mod}{xmmreg}{R_m}:minpd {Mod}{R_m},{xmmreg}
69700001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg}
69811110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg}
69911110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg}
70001100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg}
70100001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg}
70211110010,00001111,01011111,{Mod}{xmmreg}{R_m}:maxsd {Mod}{R_m},{xmmreg}
70311110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg}
70401100110,00001111,01011111,{Mod}{xmmreg}{R_m}:maxpd {Mod}{R_m},{xmmreg}
70500001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg}
Ulrich Drepperfea4e9d2008-01-04 03:21:38 +0000[diff] [blame]70601100110,00001111,01100000,{Mod}{xmmreg}{R_m}:punpcklbw {Mod}{R_m},{xmmreg}
70700001111,01100000,{MOD}{mmxreg}{R_M}:punpcklbw {MOD}{R_M},{mmxreg}
70801100110,00001111,01100001,{Mod}{xmmreg}{R_m}:punpcklwd {Mod}{R_m},{xmmreg}
70900001111,01100001,{MOD}{mmxreg}{R_M}:punpcklwd {MOD}{R_M},{mmxreg}
71001100110,00001111,01100010,{Mod}{xmmreg}{R_m}:punpckldq {Mod}{R_m},{xmmreg}
71100001111,01100010,{MOD}{mmxreg}{R_M}:punpckldq {MOD}{R_M},{mmxreg}
71201100110,00001111,01100011,{Mod}{xmmreg}{R_m}:packsswb {Mod}{R_m},{xmmreg}
71300001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg}
71401100110,00001111,01100100,{Mod}{xmmreg}{R_m}:pcmpgtb {Mod}{R_m},{xmmreg}
71500001111,01100100,{MOD}{mmxreg}{R_M}:pcmpgtb {MOD}{R_M},{mmxreg}
71601100110,00001111,01100101,{Mod}{xmmreg}{R_m}:pcmpgtw {Mod}{R_m},{xmmreg}
71700001111,01100101,{MOD}{mmxreg}{R_M}:pcmpgtw {MOD}{R_M},{mmxreg}
71801100110,00001111,01100110,{Mod}{xmmreg}{R_m}:pcmpgtd {Mod}{R_m},{xmmreg}
71900001111,01100110,{MOD}{mmxreg}{R_M}:pcmpgtd {MOD}{R_M},{mmxreg}
72001100110,00001111,01100111,{Mod}{xmmreg}{R_m}:packuswb {Mod}{R_m},{xmmreg}
72100001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg}
72201100110,00001111,01101000,{Mod}{xmmreg}{R_m}:punpckhbw {Mod}{R_m},{xmmreg}
72300001111,01101000,{MOD}{mmxreg}{R_M}:punpckhbw {MOD}{R_M},{mmxreg}
72401100110,00001111,01101001,{Mod}{xmmreg}{R_m}:punpckhwd {Mod}{R_m},{xmmreg}
72500001111,01101001,{MOD}{mmxreg}{R_M}:punpckhwd {MOD}{R_M},{mmxreg}
72601100110,00001111,01101010,{Mod}{xmmreg}{R_m}:punpckhdq {Mod}{R_m},{xmmreg}
72700001111,01101010,{MOD}{mmxreg}{R_M}:punpckhdq {MOD}{R_M},{mmxreg}
72801100110,00001111,01101011,{Mod}{xmmreg}{R_m}:packssdw {Mod}{R_m},{xmmreg}
72900001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg}
73001100110,00001111,01101100,{Mod}{xmmreg}{R_m}:punpcklqdq {Mod}{R_m},{xmmreg}
73101100110,00001111,01101101,{Mod}{xmmreg}{R_m}:punpckhqdq {Mod}{R_m},{xmmreg}
73201100110,00001111,01101110,{mod}{xmmreg}{r_m}:movd {mod}{r_m},{xmmreg}
73300001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg}
73401100110,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqa {Mod}{R_m},{xmmreg}
73511110011,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqu {Mod}{R_m},{xmmreg}
73600001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg}
73701100110,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufd {imm8},{Mod}{R_m},{xmmreg}
73811110010,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshuflw {imm8},{Mod}{R_m},{xmmreg}
73911110011,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufhw {imm8},{Mod}{R_m},{xmmreg}
74000001111,01110000,{MOD}{mmxreg}{R_M},{imm8}:pshufw {imm8},{MOD}{R_M},{mmxreg}
74101100110,00001111,01110100,{Mod}{xmmreg}{R_m}:pcmpeqb {Mod}{R_m},{xmmreg}
74200001111,01110100,{MOD}{mmxreg}{R_M}:pcmpeqb {MOD}{R_M},{mmxreg}
74301100110,00001111,01110101,{Mod}{xmmreg}{R_m}:pcmpeqw {Mod}{R_m},{xmmreg}
74400001111,01110101,{MOD}{mmxreg}{R_M}:pcmpeqw {MOD}{R_M},{mmxreg}
74501100110,00001111,01110110,{Mod}{xmmreg}{R_m}:pcmpeqd {Mod}{R_m},{xmmreg}
74600001111,01110110,{MOD}{mmxreg}{R_M}:pcmpeqd {MOD}{R_M},{mmxreg}
74701100110,00001111,01111100,{Mod}{xmmreg}{R_m}:haddpd {Mod}{R_m},{xmmreg}
74811110010,00001111,01111100,{Mod}{xmmreg}{R_m}:haddps {Mod}{R_m},{xmmreg}
74901100110,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubpd {Mod}{R_m},{xmmreg}
75011110010,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubps {Mod}{R_m},{xmmreg}
75101100110,00001111,01111110,{mod}{xmmreg}{r_m}:movd {xmmreg},{mod}{r_m}
75211110011,00001111,01111110,{Mod}{xmmreg}{R_m}:movq {Mod}{R_m},{xmmreg}
75300001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m}
75401100110,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqa {xmmreg},{Mod}{R_m}
75511110011,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqu {xmmreg},{Mod}{R_m}
75600001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M}
Ulrich Drepper9e6925d2008-01-04 21:42:14 +0000[diff] [blame]75700001111,11000011,{mod}{reg}{r_m}:movnti {reg},{mod}{r_m}
75801100110,00001111,11000100,{mod}{xmmreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{xmmreg}
75900001111,11000100,{mod}{mmxreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{mmxreg}
76001100110,00001111,11000101,11{reg}{xmmreg},{imm8}:pextrw {imm8},{xmmreg},{reg}
76100001111,11000101,11{reg}{mmxreg},{imm8}:pextrw {imm8},{mmxreg},{reg}
76201100110,00001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufpd {imm8},{Mod}{R_m},{xmmreg}
76300001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufps {imm8},{Mod}{R_m},{xmmreg}
76401100110,00001111,11010001,{Mod}{xmmreg}{R_m}:psrlw {Mod}{R_m},{xmmreg}
76500001111,11010001,{MOD}{mmxreg}{R_M}:psrlw {MOD}{R_M},{mmxreg}
76601100110,00001111,11010010,{Mod}{xmmreg}{R_m}:psrld {Mod}{R_m},{xmmreg}
76700001111,11010010,{MOD}{mmxreg}{R_M}:psrld {MOD}{R_M},{mmxreg}
76801100110,00001111,11010011,{Mod}{xmmreg}{R_m}:psrlq {Mod}{R_m},{xmmreg}
76900001111,11010011,{MOD}{mmxreg}{R_M}:psrlq {MOD}{R_M},{mmxreg}
77001100110,00001111,11010100,{Mod}{xmmreg}{R_m}:paddq {Mod}{R_m},{xmmreg}
77100001111,11010100,{MOD}{mmxreg}{R_M}:paddq {MOD}{R_M},{mmxreg}
77201100110,00001111,11010101,{Mod}{xmmreg}{R_m}:pmullw {Mod}{R_m},{xmmreg}
77300001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg}
77401100110,00001111,11010110,{Mod}{xmmreg}{R_m}:movq {xmmreg},{Mod}{R_m}
77511110010,00001111,11010110,11{mmxreg}{xmmreg}:movdq2q {xmmreg},{mmxreg}
77611110011,00001111,11010110,11{xmmreg}{mmxreg}:movq2dq {mmxreg},{xmmreg}
77701100110,00001111,11010111,11{reg}{xmmreg}:pmovmskb {xmmreg},{reg}
77800001111,11010111,11{reg}{mmxreg}:pmovmskb {mmxreg},{reg}
77901100110,00001111,11011000,{Mod}{xmmreg}{R_m}:psubusb {Mod}{R_m},{xmmreg}
78000001111,11011000,{MOD}{mmxreg}{R_M}:psubusb {MOD}{R_M},{mmxreg}
78101100110,00001111,11011001,{Mod}{xmmreg}{R_m}:psubusw {Mod}{R_m},{xmmreg}
78200001111,11011001,{MOD}{mmxreg}{R_M}:psubusw {MOD}{R_M},{mmxreg}
78301100110,00001111,11011010,{Mod}{xmmreg}{R_m}:pminub {Mod}{R_m},{xmmreg}
78400001111,11011010,{MOD}{mmxreg}{R_M}:pminub {MOD}{R_M},{mmxreg}
78501100110,00001111,11011100,{Mod}{xmmreg}{R_m}:paddusb {Mod}{R_m},{xmmreg}
78600001111,11011100,{MOD}{mmxreg}{R_M}:paddusb {MOD}{R_M},{mmxreg}
78701100110,00001111,11011101,{Mod}{xmmreg}{R_m}:paddusw {Mod}{R_m},{xmmreg}
78800001111,11011101,{MOD}{mmxreg}{R_M}:paddusw {MOD}{R_M},{mmxreg}
78901100110,00001111,11011110,{Mod}{xmmreg}{R_m}:pmaxub {Mod}{R_m},{xmmreg}
79000001111,11011110,{MOD}{mmxreg}{R_M}:pmaxub {MOD}{R_M},{mmxreg}
79101100110,00001111,11100000,{Mod}{xmmreg}{R_m}:pavgb {Mod}{R_m},{xmmreg}
79200001111,11100000,{MOD}{mmxreg}{R_M}:pavgb {MOD}{R_M},{mmxreg}
79301100110,00001111,11100001,{Mod}{xmmreg}{R_m}:psraw {Mod}{R_m},{xmmreg}
79400001111,11100001,{MOD}{mmxreg}{R_M}:psraw {MOD}{R_M},{mmxreg}
79501100110,00001111,11100010,{Mod}{xmmreg}{R_m}:psrad {Mod}{R_m},{xmmreg}
79600001111,11100010,{MOD}{mmxreg}{R_M}:psrad {MOD}{R_M},{mmxreg}
79701100110,00001111,11100011,{Mod}{xmmreg}{R_m}:pavgw {Mod}{R_m},{xmmreg}
79800001111,11100011,{MOD}{mmxreg}{R_M}:pavgw {MOD}{R_M},{mmxreg}
79901100110,00001111,11100100,{Mod}{xmmreg}{R_m}:pmulhuw {Mod}{R_m},{xmmreg}
80000001111,11100100,{MOD}{mmxreg}{R_M}:pmulhuw {MOD}{R_M},{mmxreg}
80101100110,00001111,11100101,{Mod}{xmmreg}{R_m}:pmulhw {Mod}{R_m},{xmmreg}
80200001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg}
80301100110,00001111,11100111,{Mod}{xmmreg}{R_m}:movntdq {xmmreg},{Mod}{R_m}
80400001111,11100111,{MOD}{mmxreg}{R_M}:movntq {mmxreg},{MOD}{R_M}
80501100110,00001111,11101000,{Mod}{xmmreg}{R_m}:psubsb {Mod}{R_m},{xmmreg}
80600001111,11101000,{MOD}{mmxreg}{R_M}:psubsb {MOD}{R_M},{mmxreg}
80701100110,00001111,11101001,{Mod}{xmmreg}{R_m}:psubsw {Mod}{R_m},{xmmreg}
80800001111,11101001,{MOD}{mmxreg}{R_M}:psubsw {MOD}{R_M},{mmxreg}
80901100110,00001111,11101010,{Mod}{xmmreg}{R_m}:pminsw {Mod}{R_m},{xmmreg}
81000001111,11101010,{MOD}{mmxreg}{R_M}:pminsw {MOD}{R_M},{mmxreg}
81101100110,00001111,11101100,{Mod}{xmmreg}{R_m}:paddsb {Mod}{R_m},{xmmreg}
81200001111,11101100,{MOD}{mmxreg}{R_M}:paddsb {MOD}{R_M},{mmxreg}
81301100110,00001111,11101101,{Mod}{xmmreg}{R_m}:paddsw {Mod}{R_m},{xmmreg}
81400001111,11101101,{MOD}{mmxreg}{R_M}:paddsw {MOD}{R_M},{mmxreg}
81501100110,00001111,11101110,{Mod}{xmmreg}{R_m}:pmaxsw {Mod}{R_m},{xmmreg}
81600001111,11101110,{MOD}{mmxreg}{R_M}:pmaxsw {MOD}{R_M},{mmxreg}
81711110010,00001111,11110000,{mod}{xmmreg}{r_m}:lddqu {mod}{r_m},{xmmreg}
81801100110,00001111,11110001,{Mod}{xmmreg}{R_m}:psllw {Mod}{R_m},{xmmreg}
81900001111,11110001,{MOD}{mmxreg}{R_M}:psllw {MOD}{R_M},{mmxreg}
82001100110,00001111,11110010,{Mod}{xmmreg}{R_m}:pslld {Mod}{R_m},{xmmreg}
82100001111,11110010,{MOD}{mmxreg}{R_M}:pslld {MOD}{R_M},{mmxreg}
82201100110,00001111,11110011,{Mod}{xmmreg}{R_m}:psllq {Mod}{R_m},{xmmreg}
82300001111,11110011,{MOD}{mmxreg}{R_M}:psllq {MOD}{R_M},{mmxreg}
82401100110,00001111,11110100,{Mod}{xmmreg}{R_m}:pmuludq {Mod}{R_m},{xmmreg}
82500001111,11110100,{MOD}{mmxreg}{R_M}:pmuludq {MOD}{R_M},{mmxreg}
82601100110,00001111,11110110,{Mod}{xmmreg}{R_m}:psadbw {Mod}{R_m},{xmmreg}
82700001111,11110110,{MOD}{mmxreg}{R_M}:psadbw {MOD}{R_M},{mmxreg}
82801100110,00001111,11110111,11{xmmreg1}{xmmreg2}:maskmovdqu {xmmreg2},{xmmreg1}
82900001111,11110111,11{mmxreg1}{mmxreg2}:maskmovq {mmxreg2},{mmxreg1}
83001100110,00001111,11111000,{Mod}{xmmreg}{R_m}:psubb {Mod}{R_m},{xmmreg}
83100001111,11111000,{MOD}{mmxreg}{R_M}:psubb {MOD}{R_M},{mmxreg}
83201100110,00001111,11111001,{Mod}{xmmreg}{R_m}:psubw {Mod}{R_m},{xmmreg}
83300001111,11111001,{MOD}{mmxreg}{R_M}:psubw {MOD}{R_M},{mmxreg}
83401100110,00001111,11111010,{Mod}{xmmreg}{R_m}:psubd {Mod}{R_m},{xmmreg}
83500001111,11111010,{MOD}{mmxreg}{R_M}:psubd {MOD}{R_M},{mmxreg}
83601100110,00001111,11111011,{Mod}{xmmreg}{R_m}:psubq {Mod}{R_m},{xmmreg}
83700001111,11111011,{MOD}{mmxreg}{R_M}:psubq {MOD}{R_M},{mmxreg}
83801100110,00001111,11111100,{Mod}{xmmreg}{R_m}:paddb {Mod}{R_m},{xmmreg}
83900001111,11111100,{MOD}{mmxreg}{R_M}:paddb {MOD}{R_M},{mmxreg}
84001100110,00001111,11111101,{Mod}{xmmreg}{R_m}:paddw {Mod}{R_m},{xmmreg}
84100001111,11111101,{MOD}{mmxreg}{R_M}:paddw {MOD}{R_M},{mmxreg}
84201100110,00001111,11111110,{Mod}{xmmreg}{R_m}:paddd {Mod}{R_m},{xmmreg}
84300001111,11111110,{MOD}{mmxreg}{R_M}:paddd {MOD}{R_M},{mmxreg}
84401100110,00001111,00111000,00000000,{Mod}{xmmreg}{R_m}:pshufb {Mod}{R_m},{xmmreg}
84500001111,00111000,00000000,{MOD}{mmxreg}{R_M}:pshufb {MOD}{R_M},{mmxreg}
84601100110,00001111,00111000,00000001,{Mod}{xmmreg}{R_m}:phaddw {Mod}{R_m},{xmmreg}
84700001111,00111000,00000001,{MOD}{mmxreg}{R_M}:phaddw {MOD}{R_M},{mmxreg}
84801100110,00001111,00111000,00000010,{Mod}{xmmreg}{R_m}:phaddd {Mod}{R_m},{xmmreg}
84900001111,00111000,00000010,{MOD}{mmxreg}{R_M}:phaddd {MOD}{R_M},{mmxreg}
85001100110,00001111,00111000,00000011,{Mod}{xmmreg}{R_m}:phaddsw {Mod}{R_m},{xmmreg}
85100001111,00111000,00000011,{MOD}{mmxreg}{R_M}:phaddsw {MOD}{R_M},{mmxreg}
85201100110,00001111,00111000,00000100,{Mod}{xmmreg}{R_m}:pmaddubsw {Mod}{R_m},{xmmreg}
85300001111,00111000,00000100,{MOD}{mmxreg}{R_M}:pmaddubsw {MOD}{R_M},{mmxreg}
85401100110,00001111,00111000,00000101,{Mod}{xmmreg}{R_m}:phsubw {Mod}{R_m},{xmmreg}
85500001111,00111000,00000101,{MOD}{mmxreg}{R_M}:phsubw {MOD}{R_M},{mmxreg}
85601100110,00001111,00111000,00000110,{Mod}{xmmreg}{R_m}:phsubd {Mod}{R_m},{xmmreg}
85700001111,00111000,00000110,{MOD}{mmxreg}{R_M}:phsubd {MOD}{R_M},{mmxreg}
85801100110,00001111,00111000,00000111,{Mod}{xmmreg}{R_m}:phsubsw {Mod}{R_m},{xmmreg}
85900001111,00111000,00000111,{MOD}{mmxreg}{R_M}:phsubsw {MOD}{R_M},{mmxreg}
86001100110,00001111,00111000,00001000,{Mod}{xmmreg}{R_m}:psignb {Mod}{R_m},{xmmreg}
86100001111,00111000,00001000,{MOD}{mmxreg}{R_M}:psignb {MOD}{R_M},{mmxreg}
86201100110,00001111,00111000,00001001,{Mod}{xmmreg}{R_m}:psignw {Mod}{R_m},{xmmreg}
86300001111,00111000,00001001,{MOD}{mmxreg}{R_M}:psignw {MOD}{R_M},{mmxreg}
86401100110,00001111,00111000,00001010,{Mod}{xmmreg}{R_m}:psignd {Mod}{R_m},{xmmreg}
86500001111,00111000,00001010,{MOD}{mmxreg}{R_M}:psignd {MOD}{R_M},{mmxreg}
86601100110,00001111,00111000,00001011,{Mod}{xmmreg}{R_m}:pmulhrsw {Mod}{R_m},{xmmreg}
86700001111,00111000,00001011,{MOD}{mmxreg}{R_M}:pmulhrsw {MOD}{R_M},{mmxreg}
86801100110,00001111,00111000,00011100,{Mod}{xmmreg}{R_m}:pabsb {Mod}{R_m},{xmmreg}
86900001111,00111000,00011100,{MOD}{mmxreg}{R_M}:pabsb {MOD}{R_M},{mmxreg}
87001100110,00001111,00111000,00011101,{Mod}{xmmreg}{R_m}:pabsw {Mod}{R_m},{xmmreg}
87100001111,00111000,00011101,{MOD}{mmxreg}{R_M}:pabsw {MOD}{R_M},{mmxreg}
87201100110,00001111,00111000,00011110,{Mod}{xmmreg}{R_m}:pabsd {Mod}{R_m},{xmmreg}
87300001111,00111000,00011110,{MOD}{mmxreg}{R_M}:pabsd {MOD}{R_M},{mmxreg}
87401100110,00001111,00111010,00001111,{Mod}{xmmreg}{R_m},{imm8}:palignr {imm8},{Mod}{R_m},{xmmreg}
87500001111,00111010,00001111,{MOD}{mmxreg}{R_M},{imm8}:palignr {imm8},{MOD}{R_M},{mmxreg}
87601100110,00001111,11000111,{mod}110{r_m}:vmclear {mod}{r_m}
87711110011,00001111,11000111,{mod}110{r_m}:vmxon {mod}{r_m}
87800001111,11000111,{mod}110{r_m}:vmptrld {mod}{r_m}
87900001111,11000111,{mod}111{r_m}:vmptrst {mod}{r_m}
88001100110,00001111,01110001,11010{xmmreg},{imm8}:psrlw {imm8},{xmmreg}
88100001111,01110001,11010{mmxreg},{imm8}:psrlw {imm8},{mmxreg}
88201100110,00001111,01110001,11100{xmmreg},{imm8}:psraw {imm8},{xmmreg}
88300001111,01110001,11100{mmxreg},{imm8}:psraw {imm8},{mmxreg}
88401100110,00001111,01110001,11110{xmmreg},{imm8}:psllw {imm8},{xmmreg}
88500001111,01110001,11110{mmxreg},{imm8}:psllw {imm8},{mmxreg}
88601100110,00001111,01110010,11010{xmmreg},{imm8}:psrld {imm8},{xmmreg}
88700001111,01110010,11010{mmxreg},{imm8}:psrld {imm8},{mmxreg}
88801100110,00001111,01110010,11100{xmmreg},{imm8}:psrad {imm8},{xmmreg}
88900001111,01110010,11100{mmxreg},{imm8}:psrad {imm8},{mmxreg}
89001100110,00001111,01110010,11110{xmmreg},{imm8}:pslld {imm8},{xmmreg}
89100001111,01110010,11110{mmxreg},{imm8}:pslld {imm8},{mmxreg}
89201100110,00001111,01110011,11010{xmmreg},{imm8}:psrlq {imm8},{xmmreg}
89300001111,01110011,11010{mmxreg},{imm8}:psrlq {imm8},{mmxreg}
89401100110,00001111,01110011,11011{xmmreg},{imm8}:psrldq {imm8},{xmmreg}
89501100110,00001111,01110011,11110{xmmreg},{imm8}:psllq {imm8},{xmmreg}
89600001111,01110011,11110{mmxreg},{imm8}:psllq {imm8},{mmxreg}
89701100110,00001111,01110011,11111{xmmreg},{imm8}:pslldq {imm8},{xmmreg}
89800001111,10101110,11101000:lfence
89900001111,10101110,11110000:mfence
90000001111,10101110,11111000:sfence
90100001111,10101110,{mod}111{r_m}:clflush {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]902# ORDER:
903dnl Many previous entries depend on this being last.
904000{sreg2}111:pop {sreg2}
905# ORDER END: