| commit | 5a5be91d76879ddfc84a1a18f85a7e0099ee84ba | [log] [tgz] |
|---|---|---|
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | Wed Jun 07 10:01:25 2017 +0100 |
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | Thu Jun 08 09:03:06 2017 +0100 |
| tree | 5502cad256ced0db9bcd8a792e6ae607425e62d9 | |
| parent | 65173e1aaa909ddef37321170dfb33a2992ba6f4 [diff] |
gem_wsim: Add some randomness to the 17i7 workload It was the only one with no randomness. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>