blob: 75ea5f237f0d46538ce121868b4fdcb33f8a073b [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
115 [2] = "Reserved",
116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800145 [2] = "reserved",
146 [3] = "x4 mode",
147 [4 ... 7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800148};
149
Wu Fengguang12861a92011-11-12 11:12:47 +0800150static char *bits_per_sample[] = {
151 [0] = "reserved",
152 [1] = "16 bits",
153 [2] = "24 bits",
154 [3] = "32 bits",
155 [4] = "20 bits",
156 [5] = "reserved",
157};
158
159
Wu Fengguang020abdb2010-04-19 13:13:06 +0800160static void do_self_tests(void)
161{
162 if (BIT(1, 0) != 1)
163 exit(1);
164 if (BIT(0x80000000, 31) != 1)
165 exit(2);
166 if (BITS(0xc0000000, 31, 30) != 3)
167 exit(3);
168}
169
170/*
171 * EagleLake registers
172 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800173#define AUD_CONFIG 0x62000
174#define AUD_DEBUG 0x62010
175#define AUD_VID_DID 0x62020
176#define AUD_RID 0x62024
177#define AUD_SUBN_CNT 0x62028
178#define AUD_FUNC_GRP 0x62040
179#define AUD_SUBN_CNT2 0x62044
180#define AUD_GRP_CAP 0x62048
181#define AUD_PWRST 0x6204c
182#define AUD_SUPPWR 0x62050
183#define AUD_SID 0x62054
184#define AUD_OUT_CWCAP 0x62070
185#define AUD_OUT_PCMSIZE 0x62074
186#define AUD_OUT_STR 0x62078
187#define AUD_OUT_DIG_CNVT 0x6207c
188#define AUD_OUT_CH_STR 0x62080
189#define AUD_OUT_STR_DESC 0x62084
190#define AUD_PINW_CAP 0x620a0
191#define AUD_PIN_CAP 0x620a4
192#define AUD_PINW_CONNLNG 0x620a8
193#define AUD_PINW_CONNLST 0x620ac
194#define AUD_PINW_CNTR 0x620b0
195#define AUD_PINW_UNSOLRESP 0x620b8
196#define AUD_CNTL_ST 0x620b4
197#define AUD_PINW_CONFIG 0x620bc
198#define AUD_HDMIW_STATUS 0x620d4
199#define AUD_HDMIW_HDMIEDID 0x6210c
200#define AUD_HDMIW_INFOFR 0x62118
201#define AUD_CONV_CHCNT 0x62120
202#define AUD_CTS_ENABLE 0x62128
203
204#define VIDEO_DIP_CTL 0x61170
205#define VIDEO_DIP_ENABLE (1<<31)
206#define VIDEO_DIP_ENABLE_AVI (1<<21)
207#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
208#define VIDEO_DIP_ENABLE_SPD (1<<24)
209#define VIDEO_DIP_BUF_AVI (0<<19)
210#define VIDEO_DIP_BUF_VENDOR (1<<19)
211#define VIDEO_DIP_BUF_SPD (3<<19)
212#define VIDEO_DIP_TRANS_ONCE (0<<16)
213#define VIDEO_DIP_TRANS_1 (1<<16)
214#define VIDEO_DIP_TRANS_2 (2<<16)
215
216#define AUDIO_HOTPLUG_EN (1<<24)
217
218
Wu Fengguang020abdb2010-04-19 13:13:06 +0800219static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800220{
221 uint32_t dword;
222 int i;
223
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800224 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
225
226 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
227 dump_reg(SDVOB, "Digital Display Port B Control Register");
228 dump_reg(SDVOC, "Digital Display Port C Control Register");
229 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
230
231 dump_reg(AUD_CONFIG, "Audio Configuration");
232 dump_reg(AUD_DEBUG, "Audio Debug");
233 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
234 dump_reg(AUD_RID, "Audio Revision ID");
235 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
236 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
237 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
238 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
239 dump_reg(AUD_PWRST, "Audio Power State");
240 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
241 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
242 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
243 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
244 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
245 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
246 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
247 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
248 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
249 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
250 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
251 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
252 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
253 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
254 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
255 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
256 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
257 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
258 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
259 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
260 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
261
262 printf("\nDetails:\n\n");
263
264 dword = INREG(AUD_VID_DID);
265 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
266 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
267
268 dword = INREG(AUD_RID);
269 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
270 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
271 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
272 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
273
274 dword = INREG(SDVOB);
275 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
276 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
277 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
278 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
279 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
280
281 dword = INREG(SDVOC);
282 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
283 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
284 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
285 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
286 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
287
288 dword = INREG(PORT_HOTPLUG_EN);
289 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
290 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
291 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
292 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
293 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
294 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
295 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
296 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
297
298 dword = INREG(VIDEO_DIP_CTL);
299 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
300 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
301 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
302 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
303 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
304 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
305 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
306 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
307 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
308 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
309 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
310 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
311 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
312
313 dword = INREG(AUD_CONFIG);
314 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
315 OPNAME(pixel_clock, BITS(dword, 19, 16)));
316 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
317 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
318 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
319
320 dword = INREG(AUD_DEBUG);
321 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
322
323 dword = INREG(AUD_SUBN_CNT);
324 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
325 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
326
327 dword = INREG(AUD_SUBN_CNT2);
328 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
329 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
330
331 dword = INREG(AUD_FUNC_GRP);
332 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
333 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
334
335 dword = INREG(AUD_GRP_CAP);
336 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
337 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
338 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
339
340 dword = INREG(AUD_PWRST);
341 printf("AUD_PWRST device power state\t\t%s\n",
342 power_state[BITS(dword, 5, 4)]);
343 printf("AUD_PWRST device power state setting\t%s\n",
344 power_state[BITS(dword, 1, 0)]);
345
346 dword = INREG(AUD_SUPPWR);
347 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
348 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
349 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
350 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
351
352 dword = INREG(AUD_OUT_CWCAP);
353 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
354 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
355 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
356 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
357 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
358 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
359 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
360 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
361 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
362 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
363 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
364 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
365 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
366 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
367
368 dword = INREG(AUD_OUT_DIG_CNVT);
369 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
370 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
371 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
372 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
373 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
374 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
375 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
376 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
377 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
378
379 dword = INREG(AUD_OUT_CH_STR);
380 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
Wu Fengguang5032f682011-11-12 11:12:41 +0800381 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800382
383 dword = INREG(AUD_OUT_STR_DESC);
Wu Fengguang5032f682011-11-12 11:12:41 +0800384 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800385 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
386 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800387
388 dword = INREG(AUD_PINW_CAP);
389 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
390 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
Wu Fengguang5032f682011-11-12 11:12:41 +0800391 printf("AUD_PINW_CAP channel count\t\t%lu\n",
392 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800393 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
394 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
395 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
396 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
397 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
398 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
399 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
400 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
401 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
402 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
403 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
404
405
406 dword = INREG(AUD_PIN_CAP);
407 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
408 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
409 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
410 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
411
412 dword = INREG(AUD_PINW_CNTR);
413 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
414 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
415 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
416 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
417 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
418 BITS(dword, 2, 0),
419 OPNAME(stream_type, BITS(dword, 2, 0)));
420
421 dword = INREG(AUD_PINW_UNSOLRESP);
422 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
423
424 dword = INREG(AUD_CNTL_ST);
425 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
426 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
427 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
428 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
429 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
430 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
431 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
432 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
433 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
434 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
435 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
436 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
437 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
438 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
439 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
440
441 dword = INREG(AUD_HDMIW_STATUS);
442 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
443 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
444 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
445 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
446
447 dword = INREG(AUD_CONV_CHCNT);
448 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
449 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
450
451 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
452 for (i = 0; i < 8; i++) {
453 OUTREG(AUD_CONV_CHCNT, i);
454 dword = INREG(AUD_CONV_CHCNT);
455 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
456 }
457
Wu Fengguangf32aecb2011-11-12 11:12:50 +0800458 printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t");
459 dword = INREG(AUD_CNTL_ST);
460 dword &= ~BITMASK(8, 5);
461 OUTREG(AUD_CNTL_ST, dword);
462 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
463 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID)));
464 printf("\n");
465
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800466 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
467 dword = INREG(AUD_CNTL_ST);
468 dword &= ~BITMASK(20, 18);
469 dword &= ~BITMASK(3, 0);
470 OUTREG(AUD_CNTL_ST, dword);
471 for (i = 0; i < 8; i++)
472 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
473 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800474}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800475
Wu Fengguang020abdb2010-04-19 13:13:06 +0800476#undef AUD_RID
477#undef AUD_VID_DID
478#undef AUD_PWRST
479#undef AUD_OUT_CH_STR
480#undef AUD_HDMIW_STATUS
481
482/*
483 * IronLake registers
484 */
485#define AUD_CONFIG_A 0xE2000
486#define AUD_CONFIG_B 0xE2100
487#define AUD_CTS_ENABLE_A 0xE2028
488#define AUD_CTS_ENABLE_B 0xE2128
489#define AUD_MISC_CTRL_A 0xE2010
490#define AUD_MISC_CTRL_B 0xE2110
491#define AUD_VID_DID 0xE2020
492#define AUD_RID 0xE2024
493#define AUD_PWRST 0xE204C
494#define AUD_PORT_EN_HD_CFG 0xE207C
495#define AUD_OUT_DIG_CNVT_A 0xE2080
496#define AUD_OUT_DIG_CNVT_B 0xE2180
497#define AUD_OUT_CH_STR 0xE2088
498#define AUD_OUT_STR_DESC_A 0xE2084
499#define AUD_OUT_STR_DESC_B 0xE2184
500#define AUD_PINW_CONNLNG_LIST 0xE20A8
501#define AUD_PINW_CONNLNG_SEL 0xE20AC
502#define AUD_CNTL_ST_A 0xE20B4
503#define AUD_CNTL_ST_B 0xE21B4
504#define AUD_CNTL_ST2 0xE20C0
505#define AUD_HDMIW_STATUS 0xE20D4
506#define AUD_HDMIW_HDMIEDID_A 0xE2050
507#define AUD_HDMIW_HDMIEDID_B 0xE2150
508#define AUD_HDMIW_INFOFR_A 0xE2054
509#define AUD_HDMIW_INFOFR_B 0xE2154
510
511static void dump_ironlake(void)
512{
513 uint32_t dword;
514 int i;
515
516 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
517 dump_reg(HDMIC, "HDMI Port C Control");
518 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800519 dump_reg(PCH_DP_B, "DisplayPort B Control Register");
520 dump_reg(PCH_DP_C, "DisplayPort C Control Register");
521 dump_reg(PCH_DP_D, "DisplayPort D Control Register");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800522 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
523 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
524 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
525 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800526 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
527 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
528 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
529 dump_reg(AUD_RID, "Audio Revision ID");
530 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
531 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800532 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
533 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800534 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800535 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
536 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800537 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
538 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800539 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
540 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800541 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
542 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800543 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
544 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
545 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
546 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800547
548 printf("\nDetails:\n\n");
549
550 dword = INREG(AUD_VID_DID);
551 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
552 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
553
554 dword = INREG(AUD_RID);
555 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
556 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
557 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
558 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
559
560 dword = INREG(HDMIB);
561 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
562 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
563 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800564 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800565 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
566 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
567
568 dword = INREG(HDMIC);
569 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
570 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
571 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang305443c2011-11-12 11:12:43 +0800572 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800573 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
574 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
575
576 dword = INREG(HDMID);
577 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
578 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
579 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
580 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
581 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
582 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
583
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800584 dword = INREG(PCH_DP_B);
585 printf("PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
586 printf("PCH_DP_B Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
587 printf("PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
588 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
589 printf("PCH_DP_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
590 printf("PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
591 printf("PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
592
593 dword = INREG(PCH_DP_C);
594 printf("PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
595 printf("PCH_DP_C Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
596 printf("PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
597 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
598 printf("PCH_DP_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
599 printf("PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
600 printf("PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
601
602 dword = INREG(PCH_DP_D);
603 printf("PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
604 printf("PCH_DP_D Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
605 printf("PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
606 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
607 printf("PCH_DP_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
608 printf("PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
609 printf("PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
610
Wu Fengguang020abdb2010-04-19 13:13:06 +0800611 dword = INREG(AUD_CONFIG_A);
612 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
613 OPNAME(pixel_clock, BITS(dword, 19, 16)));
614 dword = INREG(AUD_CONFIG_B);
615 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
616 OPNAME(pixel_clock, BITS(dword, 19, 16)));
617
618 dword = INREG(AUD_CTS_ENABLE_A);
619 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
620 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
621 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
622 dword = INREG(AUD_CTS_ENABLE_B);
623 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
624 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
625 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
626
627 dword = INREG(AUD_MISC_CTRL_A);
628 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
629 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
630 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
631 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
632 dword = INREG(AUD_MISC_CTRL_B);
633 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
634 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
635 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
636 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
637
638 dword = INREG(AUD_PWRST);
639 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
640 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
641 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
642 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
643 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
644 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
645 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
646 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
647 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
648 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
649 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
650 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
651
652 dword = INREG(AUD_PORT_EN_HD_CFG);
653 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
654 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
655 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
656 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
657 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
658 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
659 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
660 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
661 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
662 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
663
664 dword = INREG(AUD_OUT_DIG_CNVT_A);
665 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
666 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
667 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
668 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800669 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800670 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
671 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
672 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
673 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800674 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800675
676 dword = INREG(AUD_OUT_DIG_CNVT_B);
677 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
678 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
679 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
680 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +0800681 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800682 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
683 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
684 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
685 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
Wu Fengguangd6bdaf02011-11-12 11:12:42 +0800686 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800687
688 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
689 for (i = 0; i < 8; i++) {
690 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
691 dword = INREG(AUD_OUT_CH_STR);
692 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
693 1 + BITS(dword, 3, 0),
694 1 + BITS(dword, 7, 4),
695 1 + BITS(dword, 15, 12),
696 1 + BITS(dword, 23, 20));
697 }
698
699 dword = INREG(AUD_OUT_STR_DESC_A);
700 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800701 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800702 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
703 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800704 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
705
706 dword = INREG(AUD_OUT_STR_DESC_B);
707 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +0800708 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +0800709 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
710 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800711 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
712
713 dword = INREG(AUD_PINW_CONNLNG_SEL);
714 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
715 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
716 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
717
718 dword = INREG(AUD_CNTL_ST_A);
719 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
720 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
721 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800722 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800723 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
724 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
725 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
726 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
727 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800728 printf("AUD_CNTL_ST_A ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800729
730 dword = INREG(AUD_CNTL_ST_B);
731 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
732 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
733 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
Wu Fengguangd6e38ff2011-11-12 11:12:39 +0800734 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800735 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
736 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
737 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
738 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
739 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguangc0635c32011-11-12 11:12:51 +0800740 printf("AUD_CNTL_ST_B ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800741
742 dword = INREG(AUD_CNTL_ST2);
743 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
744 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
745 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
746 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
747 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
748 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
749
750 dword = INREG(AUD_HDMIW_STATUS);
751 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
752 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
753 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
754 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
755 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
756 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
757
758 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
759 dword = INREG(AUD_CNTL_ST_A);
760 dword &= ~BITMASK(9, 5);
761 OUTREG(AUD_CNTL_ST_A, dword);
762 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
763 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
764 printf("\n");
765
766 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
767 dword = INREG(AUD_CNTL_ST_B);
768 dword &= ~BITMASK(9, 5);
769 OUTREG(AUD_CNTL_ST_B, dword);
770 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
771 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
772 printf("\n");
773
774 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
775 dword = INREG(AUD_CNTL_ST_A);
776 dword &= ~BITMASK(20, 18);
777 dword &= ~BITMASK(3, 0);
778 OUTREG(AUD_CNTL_ST_A, dword);
779 for (i = 0; i < 8; i++)
780 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
781 printf("\n");
782
783 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
784 dword = INREG(AUD_CNTL_ST_B);
785 dword &= ~BITMASK(20, 18);
786 dword &= ~BITMASK(3, 0);
787 OUTREG(AUD_CNTL_ST_B, dword);
788 for (i = 0; i < 8; i++)
789 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
790 printf("\n");
791
792}
793
794
795#undef AUD_CONFIG_A
796#undef AUD_MISC_CTRL_A
797#undef AUD_VID_DID
798#undef AUD_RID
799#undef AUD_CTS_ENABLE_A
800#undef AUD_PWRST
801#undef AUD_HDMIW_HDMIEDID_A
802#undef AUD_HDMIW_INFOFR_A
803#undef AUD_PORT_EN_HD_CFG
804#undef AUD_OUT_DIG_CNVT_A
805#undef AUD_OUT_STR_DESC_A
806#undef AUD_OUT_CH_STR
807#undef AUD_PINW_CONNLNG_LIST
808#undef AUD_CNTL_ST_A
809#undef AUD_HDMIW_STATUS
810#undef AUD_CONFIG_B
811#undef AUD_MISC_CTRL_B
812#undef AUD_CTS_ENABLE_B
813#undef AUD_HDMIW_HDMIEDID_B
814#undef AUD_HDMIW_INFOFR_B
815#undef AUD_OUT_DIG_CNVT_B
816#undef AUD_OUT_STR_DESC_B
817#undef AUD_CNTL_ST_B
818
819/*
820 * CougarPoint registers
821 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800822#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800823#define DP_CTL_C 0xE4200
824#define DP_AUX_CTL_C 0xE4210
825#define DP_AUX_TST_C 0xE4228
826#define SPORT_DDI_CRC_C 0xE4250
827#define SPORT_DDI_CRC_R 0xE4264
828#define DP_CTL_D 0xE4300
829#define DP_AUX_CTL_D 0xE4310
830#define DP_AUX_TST_D 0xE4328
831#define SPORT_DDI_CRC_CTL_D 0xE4350
832#define AUD_CONFIG_A 0xE5000
833#define AUD_MISC_CTRL_A 0xE5010
834#define AUD_VID_DID 0xE5020
835#define AUD_RID 0xE5024
836#define AUD_CTS_ENABLE_A 0xE5028
837#define AUD_PWRST 0xE504C
838#define AUD_HDMIW_HDMIEDID_A 0xE5050
839#define AUD_HDMIW_INFOFR_A 0xE5054
840#define AUD_PORT_EN_HD_CFG 0xE507C
841#define AUD_OUT_DIG_CNVT_A 0xE5080
842#define AUD_OUT_STR_DESC_A 0xE5084
843#define AUD_OUT_CH_STR 0xE5088
844#define AUD_PINW_CONNLNG_LIST 0xE50A8
845#define AUD_PINW_CONNLNG_SELA 0xE50AC
846#define AUD_CNTL_ST_A 0xE50B4
847#define AUD_CNTRL_ST2 0xE50C0
848#define AUD_CNTRL_ST3 0xE50C4
849#define AUD_HDMIW_STATUS 0xE50D4
850#define AUD_CONFIG_B 0xE5100
851#define AUD_MISC_CTRL_B 0xE5110
852#define AUD_CTS_ENABLE_B 0xE5128
853#define AUD_HDMIW_HDMIEDID_B 0xE5150
854#define AUD_HDMIW_INFOFR_B 0xE5154
855#define AUD_OUT_DIG_CNVT_B 0xE5180
856#define AUD_OUT_STR_DESC_B 0xE5184
857#define AUD_CNTL_ST_B 0xE51B4
858#define AUD_CONFIG_C 0xE5200
859#define AUD_MISC_CTRL_C 0xE5210
860#define AUD_CTS_ENABLE_C 0xE5228
861#define AUD_HDMIW_HDMIEDID_C 0xE5250
862#define AUD_HDMIW_INFOFR_C 0xE5254
863#define AUD_OUT_DIG_CNVT_C 0xE5280
864#define AUD_OUT_STR_DESC_C 0xE5284
865#define AUD_CNTL_ST_C 0xE52B4
866#define AUD_CONFIG_D 0xE5300
867#define AUD_MISC_CTRL_D 0xE5310
868#define AUD_CTS_ENABLE_D 0xE5328
869#define AUD_HDMIW_HDMIEDID_D 0xE5350
870#define AUD_HDMIW_INFOFR_D 0xE5354
871#define AUD_OUT_DIG_CNVT_D 0xE5380
872#define AUD_OUT_STR_DESC_D 0xE5384
873#define AUD_CNTL_ST_D 0xE53B4
874
Wu Fengguange321f132011-11-12 11:12:52 +0800875#define VIDEO_DIP_CTL_A 0xE0200
876#define VIDEO_DIP_CTL_B 0xE1200
877#define VIDEO_DIP_CTL_C 0xE2200
878#define VIDEO_DIP_CTL_D 0xE3200
879
Wu Fengguang020abdb2010-04-19 13:13:06 +0800880
881static void dump_cpt(void)
882{
883 uint32_t dword;
884 int i;
885
886 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
887 dump_reg(HDMIC, "HDMI Port C Control");
888 dump_reg(HDMID, "HDMI Port D Control");
Wu Fengguang97d20312011-11-12 11:12:45 +0800889 dump_reg(DP_CTL_B, "DisplayPort B Control");
890 dump_reg(DP_CTL_C, "DisplayPort C Control");
891 dump_reg(DP_CTL_D, "DisplayPort D Control");
892 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
893 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
894 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800895 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
896 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
897 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
898 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
899 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
900 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800901 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
902 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
903 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
904 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
905 dump_reg(AUD_RID, "Audio Revision ID");
906 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
907 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800908 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
909 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
910 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800911 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800912 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
913 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
914 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800915 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
916 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800917 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
918 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
919 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800920 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
921 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
922 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
Wu Fengguangea3815c2011-11-12 11:12:38 +0800923 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
924 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
925 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
926 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
927 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
928 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800929
930 printf("\nDetails:\n\n");
931
Wu Fengguange321f132011-11-12 11:12:52 +0800932 dword = INREG(VIDEO_DIP_CTL_A);
933 printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
934 printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
935 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
936 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
937 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
938 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
939 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
940 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
941 printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n",
942 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
943 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
944 printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
945
946 dword = INREG(VIDEO_DIP_CTL_B);
947 printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
948 printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
949 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
950 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
951 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
952 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
953 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
954 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
955 printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n",
956 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
957 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
958 printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
959
960 dword = INREG(VIDEO_DIP_CTL_C);
961 printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
962 printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
963 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
964 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
965 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
966 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
967 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
968 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
969 printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n",
970 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
971 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
972 printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
973
Wu Fengguang020abdb2010-04-19 13:13:06 +0800974 dword = INREG(AUD_VID_DID);
975 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
976 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
977
978 dword = INREG(AUD_RID);
979 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
980 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
981 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
982 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
983
984 dword = INREG(HDMIB);
985 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
986 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
987 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
988 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
989 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
990 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
991 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
992 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
993
994 dword = INREG(HDMIC);
995 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
996 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
997 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
998 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
999 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
1000 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1001 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1002 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1003
1004 dword = INREG(HDMID);
1005 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1006 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1007 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1008 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1009 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
1010 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1011 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1012 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
1013
Wu Fengguang97d20312011-11-12 11:12:45 +08001014 dword = INREG(DP_CTL_B);
1015 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1016 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001017 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001018 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1019 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1020 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001021
Wu Fengguang97d20312011-11-12 11:12:45 +08001022 dword = INREG(DP_CTL_C);
1023 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1024 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001025 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001026 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1027 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1028 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001029
Wu Fengguang97d20312011-11-12 11:12:45 +08001030 dword = INREG(DP_CTL_D);
1031 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1032 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
Wu Fengguang020abdb2010-04-19 13:13:06 +08001033 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
Wu Fengguang97d20312011-11-12 11:12:45 +08001034 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1035 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1036 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001037
1038 dword = INREG(AUD_CONFIG_A);
1039 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1040 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1041 dword = INREG(AUD_CONFIG_B);
1042 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1043 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1044 dword = INREG(AUD_CONFIG_C);
1045 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1046 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1047
1048 dword = INREG(AUD_CTS_ENABLE_A);
1049 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1050 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1051 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1052 dword = INREG(AUD_CTS_ENABLE_B);
1053 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1054 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1055 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1056 dword = INREG(AUD_CTS_ENABLE_C);
1057 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1058 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1059 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1060
1061 dword = INREG(AUD_MISC_CTRL_A);
1062 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1063 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1064 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1065 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1066 dword = INREG(AUD_MISC_CTRL_B);
1067 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1068 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1069 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1070 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1071 dword = INREG(AUD_MISC_CTRL_C);
1072 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1073 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1074 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1075 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1076
1077 dword = INREG(AUD_PWRST);
1078 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1079 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1080 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1081 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1082 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1083 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1084 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1085 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1086 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1087 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1088 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1089 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1090 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1091 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
1092
1093 dword = INREG(AUD_PORT_EN_HD_CFG);
1094 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1095 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1096 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1097 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1098 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1099 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1100 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1101 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1102 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1103 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1104 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1105 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
1106
1107 dword = INREG(AUD_OUT_DIG_CNVT_A);
1108 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1109 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1110 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1111 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001112 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001113 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1114 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1115 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1116 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1117 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1118
1119 dword = INREG(AUD_OUT_DIG_CNVT_B);
1120 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1121 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1122 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1123 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001124 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001125 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1126 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1127 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1128 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1129 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1130
1131 dword = INREG(AUD_OUT_DIG_CNVT_C);
1132 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1133 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1134 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1135 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001136 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001137 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1138 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1139 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1140 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1141 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1142
1143 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1144 for (i = 0; i < 8; i++) {
1145 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1146 dword = INREG(AUD_OUT_CH_STR);
1147 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1148 1 + BITS(dword, 3, 0),
1149 1 + BITS(dword, 7, 4),
1150 1 + BITS(dword, 15, 12),
1151 1 + BITS(dword, 23, 20));
1152 }
1153
1154 dword = INREG(AUD_OUT_STR_DESC_A);
1155 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001156 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001157 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1158 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001159 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1160
1161 dword = INREG(AUD_OUT_STR_DESC_B);
1162 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001163 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001164 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1165 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001166 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1167
1168 dword = INREG(AUD_OUT_STR_DESC_C);
1169 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
Wu Fengguang5032f682011-11-12 11:12:41 +08001170 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
Wu Fengguang12861a92011-11-12 11:12:47 +08001171 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1172 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001173 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1174
1175 dword = INREG(AUD_PINW_CONNLNG_SEL);
Wu Fengguang1c6a7ca2011-11-12 11:12:40 +08001176 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1177 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1178 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001179
1180 dword = INREG(AUD_CNTL_ST_A);
1181 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1182 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001183 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1184 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001185 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1186 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1187 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1188 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1189 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1190
1191 dword = INREG(AUD_CNTL_ST_B);
1192 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1193 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001194 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1195 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001196 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1197 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1198 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1199 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1200 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1201
1202 dword = INREG(AUD_CNTL_ST_C);
1203 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1204 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wu Fengguangd6e38ff2011-11-12 11:12:39 +08001205 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n", BIT(dword, 21));
1206 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001207 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1208 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1209 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1210 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1211 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1212
1213 dword = INREG(AUD_CNTRL_ST2);
1214 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1215 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1216 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1217 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1218 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1219 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1220
1221 dword = INREG(AUD_CNTRL_ST3);
1222 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1223 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1224 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1225 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1226 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1227 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1228 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1229 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1230 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1231
1232 dword = INREG(AUD_HDMIW_STATUS);
1233 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1234 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1235 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1236 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1237 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1238 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1239 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1240 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1241
1242 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1243 dword = INREG(AUD_CNTL_ST_A);
1244 dword &= ~BITMASK(9, 5);
1245 OUTREG(AUD_CNTL_ST_A, dword);
1246 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1247 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1248 printf("\n");
1249
1250 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1251 dword = INREG(AUD_CNTL_ST_B);
1252 dword &= ~BITMASK(9, 5);
1253 OUTREG(AUD_CNTL_ST_B, dword);
1254 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1255 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1256 printf("\n");
1257
1258 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1259 dword = INREG(AUD_CNTL_ST_C);
1260 dword &= ~BITMASK(9, 5);
1261 OUTREG(AUD_CNTL_ST_C, dword);
1262 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1263 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1264 printf("\n");
1265
1266 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1267 dword = INREG(AUD_CNTL_ST_A);
1268 dword &= ~BITMASK(20, 18);
1269 dword &= ~BITMASK(3, 0);
1270 OUTREG(AUD_CNTL_ST_A, dword);
1271 for (i = 0; i < 8; i++)
1272 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1273 printf("\n");
1274
1275 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1276 dword = INREG(AUD_CNTL_ST_B);
1277 dword &= ~BITMASK(20, 18);
1278 dword &= ~BITMASK(3, 0);
1279 OUTREG(AUD_CNTL_ST_B, dword);
1280 for (i = 0; i < 8; i++)
1281 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1282 printf("\n");
1283
1284 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1285 dword = INREG(AUD_CNTL_ST_C);
1286 dword &= ~BITMASK(20, 18);
1287 dword &= ~BITMASK(3, 0);
1288 OUTREG(AUD_CNTL_ST_C, dword);
1289 for (i = 0; i < 8; i++)
1290 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1291 printf("\n");
1292
1293}
1294
1295int main(int argc, char **argv)
1296{
1297 struct pci_device *pci_dev;
1298
1299 pci_dev = intel_get_pci_device();
1300 devid = pci_dev->device_id; /* XXX not true when mapping! */
1301
1302 do_self_tests();
1303
1304 if (argc == 2)
1305 intel_map_file(argv[1]);
1306 else
1307 intel_get_mmio(pci_dev);
1308
Wu Fengguang63e3c372011-11-12 11:12:44 +08001309 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001310 printf("%s audio registers:\n\n",
1311 IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001312 intel_check_pch();
1313 dump_cpt();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001314 } else if (IS_GEN5(devid)) {
1315 printf("Ironlake audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001316 dump_ironlake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001317 } else if (IS_G4X(devid)) {
1318 printf("G45 audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001319 dump_eaglelake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001320 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001321
1322 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001323}