Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 1 | #include <unistd.h> |
| 2 | #include <stdlib.h> |
| 3 | #include <stdio.h> |
| 4 | #include <err.h> |
| 5 | #include <errno.h> |
Daniel Vetter | 71ac5de | 2014-08-26 15:13:06 +0200 | [diff] [blame] | 6 | |
Daniel Vetter | c03c6ce | 2014-03-22 21:34:29 +0100 | [diff] [blame] | 7 | #include "intel_io.h" |
Daniel Vetter | 6cfcd71 | 2014-03-22 20:07:35 +0100 | [diff] [blame] | 8 | #include "intel_reg.h" |
Daniel Vetter | 71ac5de | 2014-08-26 15:13:06 +0200 | [diff] [blame] | 9 | #include "igt_core.h" |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 10 | |
| 11 | #define TIMEOUT_US 500000 |
| 12 | |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 13 | /* Standard MMIO read, non-posted */ |
| 14 | #define SB_MRD_NP 0x00 |
| 15 | /* Standard MMIO write, non-posted */ |
| 16 | #define SB_MWR_NP 0x01 |
| 17 | /* Private register read, double-word addressing, non-posted */ |
| 18 | #define SB_CRRDDA_NP 0x06 |
| 19 | /* Private register write, double-word addressing, non-posted */ |
| 20 | #define SB_CRWRDA_NP 0x07 |
| 21 | |
Jesse Barnes | 5e21b43 | 2014-01-28 14:17:30 -0800 | [diff] [blame] | 22 | static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr, |
Jesse Barnes | 8109530 | 2014-01-28 13:46:38 -0800 | [diff] [blame] | 23 | uint32_t *val) |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 24 | { |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 25 | int timeout = 0; |
| 26 | uint32_t cmd, devfn, be, bar; |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 27 | int is_read = (opcode == SB_CRRDDA_NP || opcode == SB_MRD_NP); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 28 | |
| 29 | bar = 0; |
| 30 | be = 0xf; |
Ville Syrjälä | 0a3ef58 | 2015-02-05 16:12:11 +0200 | [diff] [blame] | 31 | devfn = 0; |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 32 | |
| 33 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
| 34 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
| 35 | (bar << IOSF_BAR_SHIFT); |
| 36 | |
Jesse Barnes | 5e21b43 | 2014-01-28 14:17:30 -0800 | [diff] [blame] | 37 | if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { |
Daniel Vetter | 71ac5de | 2014-08-26 15:13:06 +0200 | [diff] [blame] | 38 | igt_warn("warning: pcode (%s) mailbox access failed\n", is_read ? "read" : "write"); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 39 | return -EAGAIN; |
| 40 | } |
| 41 | |
Jesse Barnes | 5e21b43 | 2014-01-28 14:17:30 -0800 | [diff] [blame] | 42 | intel_register_write(VLV_IOSF_ADDR, addr); |
| 43 | if (!is_read) |
| 44 | intel_register_write(VLV_IOSF_DATA, *val); |
| 45 | |
| 46 | intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd); |
| 47 | |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 48 | do { |
| 49 | usleep(1); |
| 50 | timeout++; |
Jesse Barnes | 5e21b43 | 2014-01-28 14:17:30 -0800 | [diff] [blame] | 51 | } while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY && |
| 52 | timeout < TIMEOUT_US); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 53 | |
| 54 | if (timeout >= TIMEOUT_US) { |
Daniel Vetter | 71ac5de | 2014-08-26 15:13:06 +0200 | [diff] [blame] | 55 | igt_warn("timeout waiting for pcode %s (%d) to finish\n", is_read ? "read" : "write", addr); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 56 | return -ETIMEDOUT; |
| 57 | } |
| 58 | |
Jesse Barnes | 5e21b43 | 2014-01-28 14:17:30 -0800 | [diff] [blame] | 59 | if (is_read) |
| 60 | *val = intel_register_read(VLV_IOSF_DATA); |
| 61 | intel_register_write(VLV_IOSF_DATA, 0); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 66 | /** |
| 67 | * intel_punit_read: |
| 68 | * @addr: register offset |
Thomas Wood | d01ebbd | 2015-06-29 16:47:14 +0100 | [diff] [blame] | 69 | * @val: pointer to store the read result |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 70 | * |
| 71 | * 32-bit read of the register at @offset through the P-Unit sideband port. |
| 72 | * |
| 73 | * Returns: |
| 74 | * 0 when the register access succeeded, negative errno code on failure. |
| 75 | */ |
Ville Syrjälä | ac28ece | 2015-03-16 13:36:50 +0200 | [diff] [blame] | 76 | int intel_punit_read(uint32_t addr, uint32_t *val) |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 77 | { |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 78 | return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 79 | } |
| 80 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 81 | /** |
| 82 | * intel_punit_write: |
| 83 | * @addr: register offset |
| 84 | * @val: value to write |
| 85 | * |
| 86 | * 32-bit write of the register at @offset through the P-Unit sideband port. |
| 87 | * |
| 88 | * Returns: |
| 89 | * 0 when the register access succeeded, negative errno code on failure. |
| 90 | */ |
Ville Syrjälä | ac28ece | 2015-03-16 13:36:50 +0200 | [diff] [blame] | 91 | int intel_punit_write(uint32_t addr, uint32_t val) |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 92 | { |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 93 | return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 94 | } |
| 95 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 96 | /** |
| 97 | * intel_nc_read: |
| 98 | * @addr: register offset |
| 99 | * @val: pointer to starge for the read result |
| 100 | * |
| 101 | * 32-bit read of the register at @offset through the NC sideband port. |
| 102 | * |
| 103 | * Returns: |
| 104 | * 0 when the register access succeeded, negative errno code on failure. |
| 105 | */ |
Ville Syrjälä | ac28ece | 2015-03-16 13:36:50 +0200 | [diff] [blame] | 106 | int intel_nc_read(uint32_t addr, uint32_t *val) |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 107 | { |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 108 | return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 111 | /** |
| 112 | * intel_nc_write: |
| 113 | * @addr: register offset |
| 114 | * @val: value to write |
| 115 | * |
| 116 | * 32-bit write of the register at @offset through the NC sideband port. |
| 117 | * |
| 118 | * Returns: |
| 119 | * 0 when the register access succeeded, negative errno code on failure. |
| 120 | */ |
Ville Syrjälä | ac28ece | 2015-03-16 13:36:50 +0200 | [diff] [blame] | 121 | int intel_nc_write(uint32_t addr, uint32_t val) |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 122 | { |
Imre Deak | ad08999 | 2014-05-19 13:26:35 +0300 | [diff] [blame] | 123 | return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val); |
Jesse Barnes | 8109530 | 2014-01-28 13:46:38 -0800 | [diff] [blame] | 124 | } |
| 125 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 126 | /** |
| 127 | * intel_dpio_reg_read: |
| 128 | * @reg: register offset |
| 129 | * @phy: DPIO PHY to use |
| 130 | * |
| 131 | * 32-bit read of the register at @offset through the DPIO sideband port. |
| 132 | * |
| 133 | * Returns: |
| 134 | * The value read from the register. |
| 135 | */ |
Jesse Barnes | 8109530 | 2014-01-28 13:46:38 -0800 | [diff] [blame] | 136 | uint32_t intel_dpio_reg_read(uint32_t reg, int phy) |
| 137 | { |
| 138 | uint32_t val; |
| 139 | |
Ville Syrjälä | 0f90608 | 2014-05-28 18:26:39 +0300 | [diff] [blame] | 140 | if (phy == 0) |
| 141 | vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val); |
| 142 | else |
| 143 | vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val); |
Jesse Barnes | 8109530 | 2014-01-28 13:46:38 -0800 | [diff] [blame] | 144 | return val; |
| 145 | } |
| 146 | |
Daniel Vetter | 95e89f0 | 2014-03-22 22:41:28 +0100 | [diff] [blame] | 147 | /** |
| 148 | * intel_dpio_reg_write: |
| 149 | * @reg: register offset |
| 150 | * @val: value to write |
| 151 | * @phy: dpio PHY to use |
| 152 | * |
| 153 | * 32-bit write of the register at @offset through the DPIO sideband port. |
| 154 | */ |
Jesse Barnes | 8109530 | 2014-01-28 13:46:38 -0800 | [diff] [blame] | 155 | void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy) |
| 156 | { |
Ville Syrjälä | 0f90608 | 2014-05-28 18:26:39 +0300 | [diff] [blame] | 157 | if (phy == 0) |
| 158 | vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); |
| 159 | else |
| 160 | vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val); |
Jesse Barnes | 2533959 | 2013-04-16 13:14:58 -0700 | [diff] [blame] | 161 | } |
Imre Deak | a6eaa29 | 2014-05-18 23:37:56 +0300 | [diff] [blame] | 162 | |
| 163 | uint32_t intel_flisdsi_reg_read(uint32_t reg) |
| 164 | { |
| 165 | uint32_t val = 0; |
| 166 | |
| 167 | vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val); |
| 168 | |
| 169 | return val; |
| 170 | } |
| 171 | |
| 172 | void intel_flisdsi_reg_write(uint32_t reg, uint32_t val) |
| 173 | { |
| 174 | vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val); |
| 175 | } |
Ville Syrjälä | 71874f4 | 2014-06-10 21:28:10 +0300 | [diff] [blame] | 176 | |
| 177 | uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg) |
| 178 | { |
| 179 | uint32_t val; |
| 180 | |
| 181 | vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val); |
| 182 | |
| 183 | return val; |
| 184 | } |
| 185 | |
| 186 | void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val) |
| 187 | { |
| 188 | vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val); |
| 189 | } |