- 95b1208 assembler: Add a check for when ExecSize and width are 1 by Damien Lespiau · 12 years ago
- d70e9f8 assembler: Add a check for when width is 1 and hstride is not 0 by Damien Lespiau · 12 years ago
- e9172aa assembler: Add error() and warn() shorthands and use them in set_src[01] by Damien Lespiau · 12 years ago
- d94e8a6 assembler: Add location support by Damien Lespiau · 12 years ago
- 574a249 assembler: Don't warn if identical declared registers are redefined by Damien Lespiau · 12 years ago
- 9c72beb assembler: Store immediate values in reg.dw1.ud by Damien Lespiau · 12 years ago
- c0592b2 assembler: Factor out the source register validation by Damien Lespiau · 12 years ago
- 9fcc1bd assembler: Use brw_set_dest() to encode the destination by Damien Lespiau · 12 years ago
- 5e0da9f assembler: Factor out the destination register validation by Damien Lespiau · 12 years ago
- 9d5a87a assembler: Use brw_reg in the source operand by Damien Lespiau · 12 years ago
- c13613e assembler: Get rid of src operand's swizzle_set by Damien Lespiau · 12 years ago
- a82722b assembler: Consolidate the swizzling configuration on 8 bits by Damien Lespiau · 12 years ago
- 0375073 assembler: Replace struct dst_operand by struct brw_reg by Damien Lespiau · 12 years ago
- 801b4eb assembler: Unify the direct and indirect register type by Damien Lespiau · 12 years ago
- 36f8f65 assembler: Replace struct indirect_reg by struct brw_reg by Damien Lespiau · 12 years ago
- b33b881 assembler: Replace struct direct_reg by struct brw_reg by Damien Lespiau · 12 years ago
- cce4fc2 assembler: Make struct declared_register use struct brw_reg by Damien Lespiau · 12 years ago
- 79c62f1 assembler: Don't change the size of opcodes! by Damien Lespiau · 12 years ago
- a45a471 assembler: Make explicit that labels are part of the instructions list by Damien Lespiau · 12 years ago
- 73d58ed assembler: Refactor the code adding instructions and labels by Damien Lespiau · 12 years ago
- c716e2b assembler: Simplify get_subreg_address() by Damien Lespiau · 12 years ago
- 8322802 assembler: Use subreg_nr to store the address register subreg by Damien Lespiau · 12 years ago
- 02019d4 assembler: Remove the writemask_set field of struct dest_operand by Damien Lespiau · 12 years ago
- db6f5e0 assembler: Use BRW_WRITEMASK_XYZW instead of the 0xf constant by Damien Lespiau · 12 years ago
- 4431869 assembler: Rename BRW_ACCWRCTRL_ACCWRCTRL by Damien Lespiau · 12 years ago
- 5e7e3f4 assembler: Adopt enum brw_message_target from mesa by Damien Lespiau · 12 years ago
- 0fde3dd assembler: Rename gen5 DP pixel_scoreboard_clear to last_render_target by Damien Lespiau · 12 years ago
- fe0bd37 assembler: Remove struct dp_write_gen6 and struct use gen6_dp by Damien Lespiau · 12 years ago
- 8fa561d assembler: Rename dp_gen7 to gen7_dp and sync it with Mesa's by Damien Lespiau · 12 years ago
- 1f1ad59 assembler: Rename dp_gen6 to gen6_dp and sync with Mesa's by Damien Lespiau · 12 years ago
- 668e0df assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cache by Damien Lespiau · 12 years ago
- 31259c5 assembler: Rename three_src_gen6 to da3src by Damien Lespiau · 12 years ago
- e71f1d2 assembler: Sync brw_instruction's header with mesa's by Damien Lespiau · 12 years ago
- 191c859 build: Integrate the merged gen assembler in the build system by Damien Lespiau · 12 years ago[Renamed from assembler/src/gram.y]
- 5d72789 Fix typo. "donesn't" -> "doesn't" by Homer Hsing · 12 years ago
- 93f2a4f Add the CRE enginee for HSW+ by Zhao Yakui · 12 years ago
- 8aa9528 Add initial support for Haswell. by Gwenole Beauchesne · 12 years ago
- e221b0a Fix sub-register number of an address register encoding by Homer Hsing · 12 years ago
- 599d7d2 Fix symbol register subreg number calculation rule symbol_reg_p by Homer Hsing · 12 years ago
- e8cb195 Support Gen6 WHILE instruction by Homer Hsing · 12 years ago
- 2ad18c1 Make sure Gen6 IF works by Homer Hsing · 12 years ago
- c56d786 Make sure Gen6 ENDIF work by Homer Hsing · 12 years ago
- c91bd8c Fix Gen6 ELSE instructions code logic according to bspec. by Homer Hsing · 12 years ago
- ce55552 Make sure BREAK/CONT/HALT work on Gen6. by Homer Hsing · 12 years ago
- 3de439e Support Gen6 RET instruction. by Homer Hsing · 12 years ago
- 7529682 Support Gen6 CALL instruction. by Homer Hsing · 12 years ago
- b899aba Replace variable init code in WAIT by src_null_reg by Homer Hsing · 12 years ago
- 7e2461b Let ip_dst and ip_src become local const variable, so as to reduce replicated code. by Homer Hsing · 12 years ago
- 45ab3cf Support Gen6 three-source-operand instructions. by Homer Hsing · 12 years ago
- 72a3c19 Compile ELSE and WHILE in Gen5 as same way as in Gen4 by Homer Hsing · 12 years ago
- 4bf84ec Fully support Gen7 branching instructions by Homer Hsing · 12 years ago
- 88dfdf3 Supporting multi-branch instructios BRD & BRC by Homer Hsing · 12 years ago
- 5d589db Use right-recursing in parser rule inst_option_list by Homer Hsing · 12 years ago
- a7b1c09 Support subroutine instructions, CALL & RET by Homer Hsing · 12 years ago
- c0ebde2 Merge replicative code in gram.y by Homer Hsing · 12 years ago
- b0b540f Reduce replicative code in gram.y by reloc_target field in src_operand by Homer Hsing · 12 years ago
- 1f9a4d7 Restrict type of relativelocation2 to int by Homer Hsing · 12 years ago
- 751838e Add second_reloc_target in the data structure. by Homer Hsing · 12 years ago
- 2ab4c0d Fix memory leaking in the parser by Homer Hsing · 12 years ago
- bebe817 According to BSPEC, put PLN & BFI1 to binaryop, put SUBB to binaryaccop by Homer Hsing · 12 years ago
- 74383f4 Explain the difference between binaryinstruction and binaryaccinstruction by Homer Hsing · 12 years ago
- e6d61ac Merge same if branches in declare_pragma section in gram.y by Homer Hsing · 12 years ago
- 81859af Replace bzero by memset. by Homer Hsing · 12 years ago
- b1ef3bc Supporting integer subtraction with borrow by Homer Hsing · 12 years ago
- 9e711a4 Supporting find first bit instructions by Homer Hsing · 12 years ago
- b094cd8 Supporting half precision to single precision float convertion by Homer Hsing · 12 years ago
- 4285d9c Supporting count bit set instruction by Homer Hsing · 12 years ago
- d4f48a7 Supporting instruction "reverse bits" by Homer Hsing · 12 years ago
- 4d6337d Supporting instruction Bit Field Insert 1 by Homer Hsing · 12 years ago
- c3f1e0a Supporting addc instruction by Homer Hsing · 12 years ago
- 8ca5568 Supporting bit field extract and bit field insert 2 by Homer Hsing · 12 years ago
- 210510c Supporting LRP: dest = src0 * src1 + (1-src0) * src2 by Homer Hsing · 12 years ago
- a034bcb Support trinary source instruction "multiply add". by Homer Hsing · 12 years ago
- 4d75db5 Waring if both predication and conditional modifier are enabled but use different flag registers by Xiang, Haihao · 12 years ago
- 3ffbe96 Add support for flag register f1 on Ivy bridge by Xiang, Haihao · 12 years ago
- 2f772dd s/flag_reg_nr/flag_subreg_nr for an instruction by Xiang, Haihao · 12 years ago
- f3f6ba2 Change the rule for flag register by Xiang, Haihao · 12 years ago
- 128053f Accept symbol register as the leading register of the request by Xiang, Haihao · 12 years ago
- 0b5f7fa A new syntax of SEND intruction on Ivybridge by Xiang, Haihao · 13 years ago
- 86f8ca6 Support VME on Ivybridge by Xiang, Haihao · 13 years ago
- 2705039 Support DP for sampler/render/constant/data cache by Xiang, Haihao · 13 years ago
- e97f0bc sampler/render/constant cache unit since Sandybridge by Xiang, Haihao · 13 years ago
- 6a3a9e7 fix an error in commit cf76278 by Xiang, Haihao · 13 years ago
- 46ffdd5 SEND uses GRFs instead of MRFs on Ivybridge by Xiang, Haihao · 13 years ago
- 67d4ed6 Add support for sample (00000) on Ivybridge by Xiang, Haihao · 13 years ago
- c8d6bf3 Add support for data port read/write on Ivybridge by Xiang, Haihao · 13 years ago
- 37d6810 Send instruction on PRE-ILK by Feng, Boqun · 13 years ago
- 5239986 Add VME support in SEND by Zhou Chang · 13 years ago
- e7f4dc6 fix the parameters of register region by Xiang, Haihao · 13 years ago
- 85da7b9 send instruction on GEN6 by Xiang, Haihao · 13 years ago
- 852216d fix notification count register by Xiang, Haihao · 13 years ago
- 27b4303 Support instructions which strictly follow the documents. by Xiang, Haihao · 14 years ago
- 66649d7 1. fix DOT 2. rule for instrseq by Chen, Yangyang · 14 years ago
- 14c0bd0 Support for headerless write by Xiang, Haihao · 14 years ago
- 5405532 add support for math instruction on Sandybridge by Xiang, Haihao · 14 years ago
- f1f5208 add support for plane instruction (pln) by Xiang, Haihao · 14 years ago
- dcdde53 Send on Sandybridge uses a message register as operand src0 by Xiang, Haihao · 14 years ago
- c2382ca no compression flag on Sandybridge by Xiang, Haihao · 14 years ago
- 718cd6c print error message when using math function on Sandybridge. by Xiang, Haihao · 14 years ago
- 9d2be25 sampler, urb write, null and gateway on Sandybridge are same as Ironlake. by Xiang, Haihao · 14 years ago