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Christopher Ferrise0845012014-07-09 14:58:51 -07001/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/include/uapi/asm/kvm.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef __ARM_KVM_H__
23#define __ARM_KVM_H__
24
25#define KVM_SPSR_EL1 0
26#define KVM_SPSR_SVC KVM_SPSR_EL1
27#define KVM_SPSR_ABT 1
28#define KVM_SPSR_UND 2
29#define KVM_SPSR_IRQ 3
30#define KVM_SPSR_FIQ 4
31#define KVM_NR_SPSR 5
32
33#ifndef __ASSEMBLY__
Christopher Ferris31475242014-09-02 17:43:51 -070034#include <linux/psci.h>
Christopher Ferris12e1f282016-02-04 12:35:07 -080035#include <linux/types.h>
Christopher Ferrise0845012014-07-09 14:58:51 -070036#include <asm/ptrace.h>
37
38#define __KVM_HAVE_GUEST_DEBUG
39#define __KVM_HAVE_IRQ_LINE
Christopher Ferris7c0b6392015-01-23 15:34:26 -080040#define __KVM_HAVE_READONLY_MEM
Christopher Ferrise0845012014-07-09 14:58:51 -070041
42#define KVM_REG_SIZE(id) \
43 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
44
45struct kvm_regs {
46 struct user_pt_regs regs; /* sp = sp_el0 */
47
48 __u64 sp_el1;
49 __u64 elr_el1;
50
51 __u64 spsr[KVM_NR_SPSR];
52
53 struct user_fpsimd_state fp_regs;
54};
55
Christopher Ferris12e1f282016-02-04 12:35:07 -080056/*
57 * Supported CPU Targets - Adding a new target type is not recommended,
58 * unless there are some special registers not supported by the
59 * genericv8 syreg table.
60 */
Christopher Ferrise0845012014-07-09 14:58:51 -070061#define KVM_ARM_TARGET_AEM_V8 0
62#define KVM_ARM_TARGET_FOUNDATION_V8 1
63#define KVM_ARM_TARGET_CORTEX_A57 2
64#define KVM_ARM_TARGET_XGENE_POTENZA 3
Christopher Ferris31475242014-09-02 17:43:51 -070065#define KVM_ARM_TARGET_CORTEX_A53 4
Christopher Ferris12e1f282016-02-04 12:35:07 -080066/* Generic ARM v8 target */
67#define KVM_ARM_TARGET_GENERIC_V8 5
Christopher Ferrise0845012014-07-09 14:58:51 -070068
Christopher Ferris12e1f282016-02-04 12:35:07 -080069#define KVM_ARM_NUM_TARGETS 6
Christopher Ferrise0845012014-07-09 14:58:51 -070070
71/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
72#define KVM_ARM_DEVICE_TYPE_SHIFT 0
73#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
74#define KVM_ARM_DEVICE_ID_SHIFT 16
75#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
76
77/* Supported device IDs */
78#define KVM_ARM_DEVICE_VGIC_V2 0
79
80/* Supported VGIC address types */
81#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
82#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
83
84#define KVM_VGIC_V2_DIST_SIZE 0x1000
85#define KVM_VGIC_V2_CPU_SIZE 0x2000
86
Christopher Ferris12e1f282016-02-04 12:35:07 -080087/* Supported VGICv3 address types */
88#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
89#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
90
91#define KVM_VGIC_V3_DIST_SIZE SZ_64K
92#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
93
Christopher Ferrise0845012014-07-09 14:58:51 -070094#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
95#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
Christopher Ferris31475242014-09-02 17:43:51 -070096#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
Christopher Ferrise0845012014-07-09 14:58:51 -070097
98struct kvm_vcpu_init {
99 __u32 target;
100 __u32 features[7];
101};
102
103struct kvm_sregs {
104};
105
106struct kvm_fpu {
107};
108
Christopher Ferris12e1f282016-02-04 12:35:07 -0800109/*
110 * See v8 ARM ARM D7.3: Debug Registers
111 *
112 * The architectural limit is 16 debug registers of each type although
113 * in practice there are usually less (see ID_AA64DFR0_EL1).
114 *
115 * Although the control registers are architecturally defined as 32
116 * bits wide we use a 64 bit structure here to keep parity with
117 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
118 * 64 bit values. It also allows for the possibility of the
119 * architecture expanding the control registers without having to
120 * change the userspace ABI.
121 */
122#define KVM_ARM_MAX_DBG_REGS 16
Christopher Ferrise0845012014-07-09 14:58:51 -0700123struct kvm_guest_debug_arch {
Christopher Ferris12e1f282016-02-04 12:35:07 -0800124 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
125 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
126 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
127 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
Christopher Ferrise0845012014-07-09 14:58:51 -0700128};
129
130struct kvm_debug_exit_arch {
Christopher Ferris12e1f282016-02-04 12:35:07 -0800131 __u32 hsr;
132 __u64 far; /* used for watchpoints */
Christopher Ferrise0845012014-07-09 14:58:51 -0700133};
134
Christopher Ferris12e1f282016-02-04 12:35:07 -0800135/*
136 * Architecture specific defines for kvm_guest_debug->control
137 */
138
139#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
140#define KVM_GUESTDBG_USE_HW (1 << 17)
141
Christopher Ferrise0845012014-07-09 14:58:51 -0700142struct kvm_sync_regs {
143};
144
145struct kvm_arch_memory_slot {
146};
147
148/* If you need to interpret the index values, here is the key: */
149#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
150#define KVM_REG_ARM_COPROC_SHIFT 16
151
152/* Normal registers are mapped as coprocessor 16. */
153#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
154#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
155
156/* Some registers need more space to represent values. */
157#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
158#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
159#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
160#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
161#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
162#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
163
164/* AArch64 system registers */
165#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
166#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
167#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
168#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
169#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
170#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
171#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
172#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
173#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
174#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
175#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
176
177#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
178 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
179 KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
180
181#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
182 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
183 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
184 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
185 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
186 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
187 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
188
189#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
190
191#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
192#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
193#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
194
195/* Device Control API: ARM VGIC */
196#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
197#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
198#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
199#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
200#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
201#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
202#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
Christopher Ferris7c0b6392015-01-23 15:34:26 -0800203#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
Christopher Ferris12e1f282016-02-04 12:35:07 -0800204#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
205#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
Christopher Ferrise0845012014-07-09 14:58:51 -0700206
207/* KVM_IRQ_LINE irq field index values */
208#define KVM_ARM_IRQ_TYPE_SHIFT 24
209#define KVM_ARM_IRQ_TYPE_MASK 0xff
210#define KVM_ARM_IRQ_VCPU_SHIFT 16
211#define KVM_ARM_IRQ_VCPU_MASK 0xff
212#define KVM_ARM_IRQ_NUM_SHIFT 0
213#define KVM_ARM_IRQ_NUM_MASK 0xffff
214
215/* irq_type field */
216#define KVM_ARM_IRQ_TYPE_CPU 0
217#define KVM_ARM_IRQ_TYPE_SPI 1
218#define KVM_ARM_IRQ_TYPE_PPI 2
219
220/* out-of-kernel GIC cpu interrupt injection irq_number field */
221#define KVM_ARM_IRQ_CPU_IRQ 0
222#define KVM_ARM_IRQ_CPU_FIQ 1
223
Christopher Ferris91fbf752015-07-13 17:18:51 -0700224/*
225 * This used to hold the highest supported SPI, but it is now obsolete
226 * and only here to provide source code level compatibility with older
227 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
228 */
229#ifndef __KERNEL__
Christopher Ferrise0845012014-07-09 14:58:51 -0700230#define KVM_ARM_IRQ_GIC_MAX 127
Christopher Ferris91fbf752015-07-13 17:18:51 -0700231#endif
Christopher Ferrise0845012014-07-09 14:58:51 -0700232
Christopher Ferris12e1f282016-02-04 12:35:07 -0800233/* One single KVM irqchip, ie. the VGIC */
234#define KVM_NR_IRQCHIPS 1
235
Christopher Ferrise0845012014-07-09 14:58:51 -0700236/* PSCI interface */
237#define KVM_PSCI_FN_BASE 0x95c1ba5e
238#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
239
240#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
241#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
242#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
243#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
244
Christopher Ferris31475242014-09-02 17:43:51 -0700245#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
246#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
247#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
248#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
Christopher Ferrise0845012014-07-09 14:58:51 -0700249
250#endif
251
252#endif /* __ARM_KVM_H__ */