Cleanup gen2 tiling confusion
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index f5ab0a6..4f4de92 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -762,13 +762,12 @@
aligned_y = y;
height_alignment = 2;
- if (tiling == I915_TILING_X)
+ if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
+ height_alignment = 16;
+ else if (tiling == I915_TILING_X)
height_alignment = 8;
else if (tiling == I915_TILING_Y)
height_alignment = 32;
- /* i8xx has a interleaved 2-row tile layout */
- if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
- height_alignment *= 2;
aligned_y = ALIGN(y, height_alignment);
stride = x * cpp;