amdgpu: implement amdgpu_cs_query_reset_state
v2: also return the number of hangs
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 0997bd7..c48af92 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -98,26 +98,6 @@
};
/**
- * Enum describing possible context reset states
- *
- * \sa amdgpu_cs_query_reset_state()
- *
-*/
-enum amdgpu_cs_ctx_reset_state {
- /** No reset was detected */
- amdgpu_cs_reset_no_error = 0,
-
- /** Reset/TDR was detected and context caused */
- amdgpu_cs_reset_guilty = 1,
-
- /** Reset/TDR was detected caused by other context */
- amdgpu_cs_reset_innocent = 2,
-
- /** Reset TDR was detected by cause of it unknown */
- amdgpu_cs_reset_unknown = 3
-};
-
-/**
* For performance reasons and to simplify logic libdrm_amdgpu will handle
* IBs only some pre-defined sizes.
*
@@ -920,7 +900,8 @@
* Query reset state for the specific GPU Context
*
* \param context - \c [in] GPU Context handle
- * \param state - \c [out] Reset state status
+ * \param state - \c [out] One of AMDGPU_CTX_*_RESET
+ * \param hangs - \c [out] Number of hangs caused by the context.
*
* \return 0 on success\n
* >0 - AMD specific error code\n
@@ -930,7 +911,7 @@
*
*/
int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
- enum amdgpu_cs_ctx_reset_state *state);
+ uint32_t *state, uint32_t *hangs);
/*
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index ef3e403..c8101b8 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -611,6 +611,27 @@
return r;
}
+int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
+ uint32_t *state, uint32_t *hangs)
+{
+ union drm_amdgpu_ctx args;
+ int r;
+
+ if (!context)
+ return -EINVAL;
+
+ memset(&args, 0, sizeof(args));
+ args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
+ args.in.ctx_id = context->id;
+ r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
+ &args, sizeof(args));
+ if (!r) {
+ *state = args.out.state.reset_status;
+ *hangs = args.out.state.hangs;
+ }
+ return r;
+}
+
static uint32_t amdgpu_cs_fence_index(unsigned ip, unsigned ring)
{
return ip * AMDGPU_CS_MAX_RINGS + ring;