Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | /** |
| 25 | * \file amdgpu.h |
| 26 | * |
| 27 | * Declare public libdrm_amdgpu API |
| 28 | * |
| 29 | * This file define API exposed by libdrm_amdgpu library. |
| 30 | * User wanted to use libdrm_amdgpu functionality must include |
| 31 | * this file. |
| 32 | * |
| 33 | */ |
| 34 | #ifndef _AMDGPU_H_ |
| 35 | #define _AMDGPU_H_ |
| 36 | |
| 37 | #include <stdint.h> |
| 38 | #include <stdbool.h> |
| 39 | |
| 40 | struct drm_amdgpu_info_hw_ip; |
| 41 | |
| 42 | /*--------------------------------------------------------------------------*/ |
| 43 | /* --------------------------- Defines ------------------------------------ */ |
| 44 | /*--------------------------------------------------------------------------*/ |
| 45 | |
| 46 | /** |
| 47 | * Define max. number of Command Buffers (IB) which could be sent to the single |
| 48 | * hardware IP to accommodate CE/DE requirements |
| 49 | * |
| 50 | * \sa amdgpu_cs_ib_info |
| 51 | */ |
| 52 | #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 |
| 53 | |
| 54 | /** |
| 55 | * |
| 56 | */ |
| 57 | #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull |
| 58 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 59 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 60 | /*--------------------------------------------------------------------------*/ |
| 61 | /* ----------------------------- Enums ------------------------------------ */ |
| 62 | /*--------------------------------------------------------------------------*/ |
| 63 | |
| 64 | /** |
| 65 | * Enum describing possible handle types |
| 66 | * |
| 67 | * \sa amdgpu_bo_import, amdgpu_bo_export |
| 68 | * |
| 69 | */ |
| 70 | enum amdgpu_bo_handle_type { |
| 71 | /** GEM flink name (needs DRM authentication, used by DRI2) */ |
| 72 | amdgpu_bo_handle_type_gem_flink_name = 0, |
| 73 | |
| 74 | /** KMS handle which is used by all driver ioctls */ |
| 75 | amdgpu_bo_handle_type_kms = 1, |
| 76 | |
| 77 | /** DMA-buf fd handle */ |
| 78 | amdgpu_bo_handle_type_dma_buf_fd = 2 |
| 79 | }; |
| 80 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 81 | |
| 82 | /*--------------------------------------------------------------------------*/ |
| 83 | /* -------------------------- Datatypes ----------------------------------- */ |
| 84 | /*--------------------------------------------------------------------------*/ |
| 85 | |
| 86 | /** |
| 87 | * Define opaque pointer to context associated with fd. |
| 88 | * This context will be returned as the result of |
| 89 | * "initialize" function and should be pass as the first |
| 90 | * parameter to any API call |
| 91 | */ |
| 92 | typedef struct amdgpu_device *amdgpu_device_handle; |
| 93 | |
| 94 | /** |
| 95 | * Define GPU Context type as pointer to opaque structure |
| 96 | * Example of GPU Context is the "rendering" context associated |
| 97 | * with OpenGL context (glCreateContext) |
| 98 | */ |
| 99 | typedef struct amdgpu_context *amdgpu_context_handle; |
| 100 | |
| 101 | /** |
| 102 | * Define handle for amdgpu resources: buffer, GDS, etc. |
| 103 | */ |
| 104 | typedef struct amdgpu_bo *amdgpu_bo_handle; |
| 105 | |
| 106 | /** |
Christian König | 6dc2eaf | 2015-04-22 14:52:34 +0200 | [diff] [blame] | 107 | * Define handle for list of BOs |
| 108 | */ |
| 109 | typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; |
| 110 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 111 | |
| 112 | /*--------------------------------------------------------------------------*/ |
| 113 | /* -------------------------- Structures ---------------------------------- */ |
| 114 | /*--------------------------------------------------------------------------*/ |
| 115 | |
| 116 | /** |
| 117 | * Structure describing memory allocation request |
| 118 | * |
| 119 | * \sa amdgpu_bo_alloc() |
| 120 | * |
| 121 | */ |
| 122 | struct amdgpu_bo_alloc_request { |
| 123 | /** Allocation request. It must be aligned correctly. */ |
| 124 | uint64_t alloc_size; |
| 125 | |
| 126 | /** |
| 127 | * It may be required to have some specific alignment requirements |
| 128 | * for physical back-up storage (e.g. for displayable surface). |
| 129 | * If 0 there is no special alignment requirement |
| 130 | */ |
| 131 | uint64_t phys_alignment; |
| 132 | |
| 133 | /** |
| 134 | * UMD should specify where to allocate memory and how it |
| 135 | * will be accessed by the CPU. |
| 136 | */ |
| 137 | uint32_t preferred_heap; |
| 138 | |
| 139 | /** Additional flags passed on allocation */ |
| 140 | uint64_t flags; |
| 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * Structure describing memory allocation request |
| 145 | * |
| 146 | * \sa amdgpu_bo_alloc() |
| 147 | */ |
| 148 | struct amdgpu_bo_alloc_result { |
| 149 | /** Assigned virtual MC Base Address */ |
| 150 | uint64_t virtual_mc_base_address; |
| 151 | |
| 152 | /** Handle of allocated memory to be used by the given process only. */ |
| 153 | amdgpu_bo_handle buf_handle; |
| 154 | }; |
| 155 | |
| 156 | /** |
| 157 | * Special UMD specific information associated with buffer. |
| 158 | * |
| 159 | * It may be need to pass some buffer charactersitic as part |
| 160 | * of buffer sharing. Such information are defined UMD and |
| 161 | * opaque for libdrm_amdgpu as well for kernel driver. |
| 162 | * |
| 163 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, |
| 164 | * amdgpu_bo_import(), amdgpu_bo_export |
| 165 | * |
| 166 | */ |
| 167 | struct amdgpu_bo_metadata { |
| 168 | /** Special flag associated with surface */ |
| 169 | uint64_t flags; |
| 170 | |
| 171 | /** |
| 172 | * ASIC-specific tiling information (also used by DCE). |
| 173 | * The encoding is defined by the AMDGPU_TILING_* definitions. |
| 174 | */ |
| 175 | uint64_t tiling_info; |
| 176 | |
| 177 | /** Size of metadata associated with the buffer, in bytes. */ |
| 178 | uint32_t size_metadata; |
| 179 | |
| 180 | /** UMD specific metadata. Opaque for kernel */ |
| 181 | uint32_t umd_metadata[64]; |
| 182 | }; |
| 183 | |
| 184 | /** |
| 185 | * Structure describing allocated buffer. Client may need |
| 186 | * to query such information as part of 'sharing' buffers mechanism |
| 187 | * |
| 188 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), |
| 189 | * amdgpu_bo_import(), amdgpu_bo_export() |
| 190 | */ |
| 191 | struct amdgpu_bo_info { |
| 192 | /** Allocated memory size */ |
| 193 | uint64_t alloc_size; |
| 194 | |
| 195 | /** |
| 196 | * It may be required to have some specific alignment requirements |
| 197 | * for physical back-up storage. |
| 198 | */ |
| 199 | uint64_t phys_alignment; |
| 200 | |
| 201 | /** |
| 202 | * Assigned virtual MC Base Address. |
| 203 | * \note This information will be returned only if this buffer was |
| 204 | * allocated in the same process otherwise 0 will be returned. |
| 205 | */ |
| 206 | uint64_t virtual_mc_base_address; |
| 207 | |
| 208 | /** Heap where to allocate memory. */ |
| 209 | uint32_t preferred_heap; |
| 210 | |
| 211 | /** Additional allocation flags. */ |
| 212 | uint64_t alloc_flags; |
| 213 | |
| 214 | /** Metadata associated with buffer if any. */ |
| 215 | struct amdgpu_bo_metadata metadata; |
| 216 | }; |
| 217 | |
| 218 | /** |
| 219 | * Structure with information about "imported" buffer |
| 220 | * |
| 221 | * \sa amdgpu_bo_import() |
| 222 | * |
| 223 | */ |
| 224 | struct amdgpu_bo_import_result { |
| 225 | /** Handle of memory/buffer to use */ |
| 226 | amdgpu_bo_handle buf_handle; |
| 227 | |
| 228 | /** Buffer size */ |
| 229 | uint64_t alloc_size; |
| 230 | |
| 231 | /** Assigned virtual MC Base Address */ |
| 232 | uint64_t virtual_mc_base_address; |
| 233 | }; |
| 234 | |
| 235 | |
| 236 | /** |
| 237 | * |
| 238 | * Structure to describe GDS partitioning information. |
| 239 | * \note OA and GWS resources are asscoiated with GDS partition |
| 240 | * |
| 241 | * \sa amdgpu_gpu_resource_query_gds_info |
| 242 | * |
| 243 | */ |
| 244 | struct amdgpu_gds_resource_info { |
| 245 | uint32_t gds_gfx_partition_size; |
| 246 | uint32_t compute_partition_size; |
| 247 | uint32_t gds_total_size; |
| 248 | uint32_t gws_per_gfx_partition; |
| 249 | uint32_t gws_per_compute_partition; |
| 250 | uint32_t oa_per_gfx_partition; |
| 251 | uint32_t oa_per_compute_partition; |
| 252 | }; |
| 253 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 254 | /** |
Christian König | 0f37bc9 | 2015-06-24 14:17:57 +0200 | [diff] [blame^] | 255 | * Structure describing CS dependency |
| 256 | * |
| 257 | * \sa amdgpu_cs_request, amdgpu_cs_submit() |
| 258 | * |
| 259 | */ |
| 260 | struct amdgpu_cs_dep_info { |
| 261 | /** Context to which the fence belongs */ |
| 262 | amdgpu_context_handle context; |
| 263 | |
| 264 | /** To which HW IP type the fence belongs */ |
| 265 | uint32_t ip_type; |
| 266 | |
| 267 | /** IP instance index if there are several IPs of the same type. */ |
| 268 | uint32_t ip_instance; |
| 269 | |
| 270 | /** Ring index of the HW IP */ |
| 271 | uint32_t ring; |
| 272 | |
| 273 | /** Specify fence for which we need to check |
| 274 | * submission status.*/ |
| 275 | uint64_t fence; |
| 276 | }; |
| 277 | |
| 278 | /** |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 279 | * Structure describing IB |
| 280 | * |
| 281 | * \sa amdgpu_cs_request, amdgpu_cs_submit() |
| 282 | * |
| 283 | */ |
| 284 | struct amdgpu_cs_ib_info { |
| 285 | /** Special flags */ |
| 286 | uint64_t flags; |
| 287 | |
Marek Olšák | 76af5c2 | 2015-06-02 13:05:41 +0200 | [diff] [blame] | 288 | /** Virtual MC address of the command buffer */ |
| 289 | uint64_t ib_mc_address; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 290 | |
| 291 | /** |
| 292 | * Size of Command Buffer to be submitted. |
| 293 | * - The size is in units of dwords (4 bytes). |
| 294 | * - Must be less or equal to the size of allocated IB |
| 295 | * - Could be 0 |
| 296 | */ |
| 297 | uint32_t size; |
| 298 | }; |
| 299 | |
| 300 | /** |
| 301 | * Structure describing submission request |
| 302 | * |
| 303 | * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx |
| 304 | * |
| 305 | * \sa amdgpu_cs_submit() |
| 306 | */ |
| 307 | struct amdgpu_cs_request { |
| 308 | /** Specify flags with additional information */ |
| 309 | uint64_t flags; |
| 310 | |
| 311 | /** Specify HW IP block type to which to send the IB. */ |
| 312 | unsigned ip_type; |
| 313 | |
| 314 | /** IP instance index if there are several IPs of the same type. */ |
| 315 | unsigned ip_instance; |
| 316 | |
| 317 | /** |
| 318 | * Specify ring index of the IP. We could have several rings |
| 319 | * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. |
| 320 | */ |
| 321 | uint32_t ring; |
| 322 | |
| 323 | /** |
Christian König | 6dc2eaf | 2015-04-22 14:52:34 +0200 | [diff] [blame] | 324 | * List handle with resources used by this request. |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 325 | */ |
Christian König | 6dc2eaf | 2015-04-22 14:52:34 +0200 | [diff] [blame] | 326 | amdgpu_bo_list_handle resources; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 327 | |
Christian König | 0f37bc9 | 2015-06-24 14:17:57 +0200 | [diff] [blame^] | 328 | /** |
| 329 | * Number of dependencies this Command submission needs to |
| 330 | * wait for before starting execution. |
| 331 | */ |
| 332 | uint32_t number_of_dependencies; |
| 333 | |
| 334 | /** |
| 335 | * Array of dependencies which need to be met before |
| 336 | * execution can start. |
| 337 | */ |
| 338 | struct amdgpu_cs_dep_info *dependencies; |
| 339 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 340 | /** Number of IBs to submit in the field ibs. */ |
| 341 | uint32_t number_of_ibs; |
| 342 | |
| 343 | /** |
| 344 | * IBs to submit. Those IBs will be submit together as single entity |
| 345 | */ |
| 346 | struct amdgpu_cs_ib_info *ibs; |
| 347 | }; |
| 348 | |
| 349 | /** |
| 350 | * Structure describing request to check submission state using fence |
| 351 | * |
| 352 | * \sa amdgpu_cs_query_fence_status() |
| 353 | * |
| 354 | */ |
| 355 | struct amdgpu_cs_query_fence { |
| 356 | |
| 357 | /** In which context IB was sent to execution */ |
| 358 | amdgpu_context_handle context; |
| 359 | |
| 360 | /** Timeout in nanoseconds. */ |
| 361 | uint64_t timeout_ns; |
| 362 | |
| 363 | /** To which HW IP type the fence belongs */ |
| 364 | unsigned ip_type; |
| 365 | |
| 366 | /** IP instance index if there are several IPs of the same type. */ |
| 367 | unsigned ip_instance; |
| 368 | |
| 369 | /** Ring index of the HW IP */ |
| 370 | uint32_t ring; |
| 371 | |
| 372 | /** Flags */ |
| 373 | uint64_t flags; |
| 374 | |
| 375 | /** Specify fence for which we need to check |
| 376 | * submission status.*/ |
| 377 | uint64_t fence; |
| 378 | }; |
| 379 | |
| 380 | /** |
| 381 | * Structure which provide information about GPU VM MC Address space |
| 382 | * alignments requirements |
| 383 | * |
| 384 | * \sa amdgpu_query_buffer_size_alignment |
| 385 | */ |
| 386 | struct amdgpu_buffer_size_alignments { |
| 387 | /** Size alignment requirement for allocation in |
| 388 | * local memory */ |
| 389 | uint64_t size_local; |
| 390 | |
| 391 | /** |
| 392 | * Size alignment requirement for allocation in remote memory |
| 393 | */ |
| 394 | uint64_t size_remote; |
| 395 | }; |
| 396 | |
| 397 | |
| 398 | /** |
| 399 | * Structure which provide information about heap |
| 400 | * |
| 401 | * \sa amdgpu_query_heap_info() |
| 402 | * |
| 403 | */ |
| 404 | struct amdgpu_heap_info { |
| 405 | /** Theoretical max. available memory in the given heap */ |
| 406 | uint64_t heap_size; |
| 407 | |
| 408 | /** |
| 409 | * Number of bytes allocated in the heap. This includes all processes |
| 410 | * and private allocations in the kernel. It changes when new buffers |
| 411 | * are allocated, freed, and moved. It cannot be larger than |
| 412 | * heap_size. |
| 413 | */ |
| 414 | uint64_t heap_usage; |
| 415 | |
| 416 | /** |
| 417 | * Theoretical possible max. size of buffer which |
| 418 | * could be allocated in the given heap |
| 419 | */ |
| 420 | uint64_t max_allocation; |
| 421 | }; |
| 422 | |
| 423 | |
| 424 | |
| 425 | /** |
| 426 | * Describe GPU h/w info needed for UMD correct initialization |
| 427 | * |
| 428 | * \sa amdgpu_query_gpu_info() |
| 429 | */ |
| 430 | struct amdgpu_gpu_info { |
| 431 | /** Asic id */ |
| 432 | uint32_t asic_id; |
| 433 | /**< Chip revision */ |
| 434 | uint32_t chip_rev; |
| 435 | /** Chip external revision */ |
| 436 | uint32_t chip_external_rev; |
| 437 | /** Family ID */ |
| 438 | uint32_t family_id; |
| 439 | /** Special flags */ |
| 440 | uint64_t ids_flags; |
| 441 | /** max engine clock*/ |
| 442 | uint64_t max_engine_clk; |
Ken Wang | fc9fc7d | 2015-06-03 17:07:44 +0800 | [diff] [blame] | 443 | /** max memory clock */ |
| 444 | uint64_t max_memory_clk; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 445 | /** number of shader engines */ |
| 446 | uint32_t num_shader_engines; |
| 447 | /** number of shader arrays per engine */ |
| 448 | uint32_t num_shader_arrays_per_engine; |
| 449 | /** Number of available good shader pipes */ |
| 450 | uint32_t avail_quad_shader_pipes; |
| 451 | /** Max. number of shader pipes.(including good and bad pipes */ |
| 452 | uint32_t max_quad_shader_pipes; |
| 453 | /** Number of parameter cache entries per shader quad pipe */ |
| 454 | uint32_t cache_entries_per_quad_pipe; |
| 455 | /** Number of available graphics context */ |
| 456 | uint32_t num_hw_gfx_contexts; |
| 457 | /** Number of render backend pipes */ |
| 458 | uint32_t rb_pipes; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 459 | /** Enabled render backend pipe mask */ |
| 460 | uint32_t enabled_rb_pipes_mask; |
| 461 | /** Frequency of GPU Counter */ |
| 462 | uint32_t gpu_counter_freq; |
| 463 | /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ |
| 464 | uint32_t backend_disable[4]; |
| 465 | /** Value of MC_ARB_RAMCFG register*/ |
| 466 | uint32_t mc_arb_ramcfg; |
| 467 | /** Value of GB_ADDR_CONFIG */ |
| 468 | uint32_t gb_addr_cfg; |
| 469 | /** Values of the GB_TILE_MODE0..31 registers */ |
| 470 | uint32_t gb_tile_mode[32]; |
| 471 | /** Values of GB_MACROTILE_MODE0..15 registers */ |
| 472 | uint32_t gb_macro_tile_mode[16]; |
| 473 | /** Value of PA_SC_RASTER_CONFIG register per SE */ |
| 474 | uint32_t pa_sc_raster_cfg[4]; |
| 475 | /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ |
| 476 | uint32_t pa_sc_raster_cfg1[4]; |
| 477 | /* CU info */ |
| 478 | uint32_t cu_active_number; |
| 479 | uint32_t cu_ao_mask; |
| 480 | uint32_t cu_bitmap[4][4]; |
Ken Wang | 4bf2941 | 2015-06-03 17:15:29 +0800 | [diff] [blame] | 481 | /* video memory type info*/ |
| 482 | uint32_t vram_type; |
| 483 | /* video memory bit width*/ |
| 484 | uint32_t vram_bit_width; |
Ken Wang | cdd1edc | 2015-06-03 17:21:27 +0800 | [diff] [blame] | 485 | /** constant engine ram size*/ |
| 486 | uint32_t ce_ram_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | |
| 490 | /*--------------------------------------------------------------------------*/ |
| 491 | /*------------------------- Functions --------------------------------------*/ |
| 492 | /*--------------------------------------------------------------------------*/ |
| 493 | |
| 494 | /* |
| 495 | * Initialization / Cleanup |
| 496 | * |
| 497 | */ |
| 498 | |
| 499 | |
| 500 | /** |
| 501 | * |
| 502 | * \param fd - \c [in] File descriptor for AMD GPU device |
| 503 | * received previously as the result of |
| 504 | * e.g. drmOpen() call. |
| 505 | * For legacy fd type, the DRI2/DRI3 authentication |
| 506 | * should be done before calling this function. |
| 507 | * \param major_version - \c [out] Major version of library. It is assumed |
| 508 | * that adding new functionality will cause |
| 509 | * increase in major version |
| 510 | * \param minor_version - \c [out] Minor version of library |
| 511 | * \param device_handle - \c [out] Pointer to opaque context which should |
| 512 | * be passed as the first parameter on each |
| 513 | * API call |
| 514 | * |
| 515 | * |
| 516 | * \return 0 on success\n |
| 517 | * >0 - AMD specific error code\n |
| 518 | * <0 - Negative POSIX Error code |
| 519 | * |
| 520 | * |
| 521 | * \sa amdgpu_device_deinitialize() |
| 522 | */ |
| 523 | int amdgpu_device_initialize(int fd, |
| 524 | uint32_t *major_version, |
| 525 | uint32_t *minor_version, |
| 526 | amdgpu_device_handle *device_handle); |
| 527 | |
| 528 | |
| 529 | |
| 530 | /** |
| 531 | * |
| 532 | * When access to such library does not needed any more the special |
| 533 | * function must be call giving opportunity to clean up any |
| 534 | * resources if needed. |
| 535 | * |
| 536 | * \param device_handle - \c [in] Context associated with file |
| 537 | * descriptor for AMD GPU device |
| 538 | * received previously as the |
| 539 | * result e.g. of drmOpen() call. |
| 540 | * |
| 541 | * \return 0 on success\n |
| 542 | * >0 - AMD specific error code\n |
| 543 | * <0 - Negative POSIX Error code |
| 544 | * |
| 545 | * \sa amdgpu_device_initialize() |
| 546 | * |
| 547 | */ |
| 548 | int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); |
| 549 | |
| 550 | |
| 551 | /* |
| 552 | * Memory Management |
| 553 | * |
| 554 | */ |
| 555 | |
| 556 | /** |
| 557 | * Allocate memory to be used by UMD for GPU related operations |
| 558 | * |
| 559 | * \param dev - \c [in] Device handle. |
| 560 | * See #amdgpu_device_initialize() |
| 561 | * \param alloc_buffer - \c [in] Pointer to the structure describing an |
| 562 | * allocation request |
| 563 | * \param info - \c [out] Pointer to structure which return |
| 564 | * information about allocated memory |
| 565 | * |
| 566 | * \return 0 on success\n |
| 567 | * >0 - AMD specific error code\n |
| 568 | * <0 - Negative POSIX Error code |
| 569 | * |
| 570 | * \sa amdgpu_bo_free() |
| 571 | */ |
| 572 | int amdgpu_bo_alloc(amdgpu_device_handle dev, |
| 573 | struct amdgpu_bo_alloc_request *alloc_buffer, |
| 574 | struct amdgpu_bo_alloc_result *info); |
| 575 | |
| 576 | /** |
| 577 | * Associate opaque data with buffer to be queried by another UMD |
| 578 | * |
| 579 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 580 | * \param buf_handle - \c [in] Buffer handle |
| 581 | * \param info - \c [in] Metadata to associated with buffer |
| 582 | * |
| 583 | * \return 0 on success\n |
| 584 | * >0 - AMD specific error code\n |
| 585 | * <0 - Negative POSIX Error code |
| 586 | */ |
| 587 | int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, |
| 588 | struct amdgpu_bo_metadata *info); |
| 589 | |
| 590 | /** |
| 591 | * Query buffer information including metadata previusly associated with |
| 592 | * buffer. |
| 593 | * |
| 594 | * \param dev - \c [in] Device handle. |
| 595 | * See #amdgpu_device_initialize() |
| 596 | * \param buf_handle - \c [in] Buffer handle |
| 597 | * \param info - \c [out] Structure describing buffer |
| 598 | * |
| 599 | * \return 0 on success\n |
| 600 | * >0 - AMD specific error code\n |
| 601 | * <0 - Negative POSIX Error code |
| 602 | * |
| 603 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() |
| 604 | */ |
| 605 | int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, |
| 606 | struct amdgpu_bo_info *info); |
| 607 | |
| 608 | /** |
| 609 | * Allow others to get access to buffer |
| 610 | * |
| 611 | * \param dev - \c [in] Device handle. |
| 612 | * See #amdgpu_device_initialize() |
| 613 | * \param buf_handle - \c [in] Buffer handle |
| 614 | * \param type - \c [in] Type of handle requested |
| 615 | * \param shared_handle - \c [out] Special "shared" handle |
| 616 | * |
| 617 | * \return 0 on success\n |
| 618 | * >0 - AMD specific error code\n |
| 619 | * <0 - Negative POSIX Error code |
| 620 | * |
| 621 | * \sa amdgpu_bo_import() |
| 622 | * |
| 623 | */ |
| 624 | int amdgpu_bo_export(amdgpu_bo_handle buf_handle, |
| 625 | enum amdgpu_bo_handle_type type, |
| 626 | uint32_t *shared_handle); |
| 627 | |
| 628 | /** |
| 629 | * Request access to "shared" buffer |
| 630 | * |
| 631 | * \param dev - \c [in] Device handle. |
| 632 | * See #amdgpu_device_initialize() |
| 633 | * \param type - \c [in] Type of handle requested |
| 634 | * \param shared_handle - \c [in] Shared handle received as result "import" |
| 635 | * operation |
| 636 | * \param output - \c [out] Pointer to structure with information |
| 637 | * about imported buffer |
| 638 | * |
| 639 | * \return 0 on success\n |
| 640 | * >0 - AMD specific error code\n |
| 641 | * <0 - Negative POSIX Error code |
| 642 | * |
| 643 | * \note Buffer must be "imported" only using new "fd" (different from |
| 644 | * one used by "exporter"). |
| 645 | * |
| 646 | * \sa amdgpu_bo_export() |
| 647 | * |
| 648 | */ |
| 649 | int amdgpu_bo_import(amdgpu_device_handle dev, |
| 650 | enum amdgpu_bo_handle_type type, |
| 651 | uint32_t shared_handle, |
| 652 | struct amdgpu_bo_import_result *output); |
| 653 | |
| 654 | /** |
| 655 | * Free previosuly allocated memory |
| 656 | * |
| 657 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 658 | * \param buf_handle - \c [in] Buffer handle to free |
| 659 | * |
| 660 | * \return 0 on success\n |
| 661 | * >0 - AMD specific error code\n |
| 662 | * <0 - Negative POSIX Error code |
| 663 | * |
| 664 | * \note In the case of memory shared between different applications all |
| 665 | * resources will be “physically” freed only all such applications |
| 666 | * will be terminated |
| 667 | * \note If is UMD responsibility to ‘free’ buffer only when there is no |
| 668 | * more GPU access |
| 669 | * |
| 670 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() |
| 671 | * |
| 672 | */ |
| 673 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle); |
| 674 | |
| 675 | /** |
| 676 | * Request CPU access to GPU accessable memory |
| 677 | * |
| 678 | * \param buf_handle - \c [in] Buffer handle |
| 679 | * \param cpu - \c [out] CPU address to be used for access |
| 680 | * |
| 681 | * \return 0 on success\n |
| 682 | * >0 - AMD specific error code\n |
| 683 | * <0 - Negative POSIX Error code |
| 684 | * |
| 685 | * \sa amdgpu_bo_cpu_unmap() |
| 686 | * |
| 687 | */ |
| 688 | int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); |
| 689 | |
| 690 | /** |
| 691 | * Release CPU access to GPU memory |
| 692 | * |
| 693 | * \param buf_handle - \c [in] Buffer handle |
| 694 | * |
| 695 | * \return 0 on success\n |
| 696 | * >0 - AMD specific error code\n |
| 697 | * <0 - Negative POSIX Error code |
| 698 | * |
| 699 | * \sa amdgpu_bo_cpu_map() |
| 700 | * |
| 701 | */ |
| 702 | int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); |
| 703 | |
| 704 | |
| 705 | /** |
| 706 | * Wait until a buffer is not used by the device. |
| 707 | * |
| 708 | * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize() |
| 709 | * \param buf_handle - \c [in] Buffer handle. |
| 710 | * \param timeout_ns - Timeout in nanoseconds. |
| 711 | * \param buffer_busy - 0 if buffer is idle, all GPU access was completed |
| 712 | * and no GPU access is scheduled. |
| 713 | * 1 GPU access is in fly or scheduled |
| 714 | * |
| 715 | * \return 0 - on success |
| 716 | * <0 - AMD specific error code |
| 717 | */ |
| 718 | int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, |
| 719 | uint64_t timeout_ns, |
| 720 | bool *buffer_busy); |
| 721 | |
Christian König | 6dc2eaf | 2015-04-22 14:52:34 +0200 | [diff] [blame] | 722 | /** |
| 723 | * Creates a BO list handle for command submission. |
| 724 | * |
| 725 | * \param dev - \c [in] Device handle. |
| 726 | * See #amdgpu_device_initialize() |
| 727 | * \param number_of_resources - \c [in] Number of BOs in the list |
| 728 | * \param resources - \c [in] List of BO handles |
| 729 | * \param resource_prios - \c [in] Optional priority for each handle |
| 730 | * \param result - \c [out] Created BO list handle |
| 731 | * |
| 732 | * \return 0 on success\n |
| 733 | * >0 - AMD specific error code\n |
| 734 | * <0 - Negative POSIX Error code |
| 735 | * |
| 736 | * \sa amdgpu_bo_list_destroy() |
| 737 | */ |
| 738 | int amdgpu_bo_list_create(amdgpu_device_handle dev, |
| 739 | uint32_t number_of_resources, |
| 740 | amdgpu_bo_handle *resources, |
| 741 | uint8_t *resource_prios, |
| 742 | amdgpu_bo_list_handle *result); |
| 743 | |
| 744 | /** |
| 745 | * Destroys a BO list handle. |
| 746 | * |
| 747 | * \param handle - \c [in] BO list handle. |
| 748 | * |
| 749 | * \return 0 on success\n |
| 750 | * >0 - AMD specific error code\n |
| 751 | * <0 - Negative POSIX Error code |
| 752 | * |
| 753 | * \sa amdgpu_bo_list_create() |
| 754 | */ |
| 755 | int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 756 | |
Jammy Zhou | 7244698 | 2015-05-18 20:27:24 +0800 | [diff] [blame] | 757 | /** |
| 758 | * Update resources for existing BO list |
| 759 | * |
| 760 | * \param handle - \c [in] BO list handle |
| 761 | * \param number_of_resources - \c [in] Number of BOs in the list |
| 762 | * \param resources - \c [in] List of BO handles |
| 763 | * \param resource_prios - \c [in] Optional priority for each handle |
| 764 | * |
| 765 | * \return 0 on success\n |
| 766 | * >0 - AMD specific error code\n |
| 767 | * <0 - Negative POSIX Error code |
| 768 | * |
| 769 | * \sa amdgpu_bo_list_update() |
| 770 | */ |
| 771 | int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, |
| 772 | uint32_t number_of_resources, |
| 773 | amdgpu_bo_handle *resources, |
| 774 | uint8_t *resource_prios); |
| 775 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 776 | /* |
| 777 | * Special GPU Resources |
| 778 | * |
| 779 | */ |
| 780 | |
| 781 | |
| 782 | |
| 783 | /** |
| 784 | * Query information about GDS |
| 785 | * |
| 786 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 787 | * \param gds_info - \c [out] Pointer to structure to get GDS information |
| 788 | * |
| 789 | * \return 0 on success\n |
| 790 | * >0 - AMD specific error code\n |
| 791 | * <0 - Negative POSIX Error code |
| 792 | * |
| 793 | */ |
Jammy Zhou | 657245f | 2015-06-06 05:00:36 +0800 | [diff] [blame] | 794 | int amdgpu_query_gds_info(amdgpu_device_handle dev, |
| 795 | struct amdgpu_gds_resource_info *gds_info); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 796 | |
| 797 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 798 | /* |
| 799 | * GPU Execution context |
| 800 | * |
| 801 | */ |
| 802 | |
| 803 | /** |
| 804 | * Create GPU execution Context |
| 805 | * |
| 806 | * For the purpose of GPU Scheduler and GPU Robustness extensions it is |
| 807 | * necessary to have information/identify rendering/compute contexts. |
| 808 | * It also may be needed to associate some specific requirements with such |
| 809 | * contexts. Kernel driver will guarantee that submission from the same |
| 810 | * context will always be executed in order (first come, first serve). |
| 811 | * |
| 812 | * |
| 813 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 814 | * \param context - \c [out] GPU Context handle |
| 815 | * |
| 816 | * \return 0 on success\n |
| 817 | * >0 - AMD specific error code\n |
| 818 | * <0 - Negative POSIX Error code |
| 819 | * |
| 820 | * \sa amdgpu_cs_ctx_free() |
| 821 | * |
| 822 | */ |
| 823 | int amdgpu_cs_ctx_create(amdgpu_device_handle dev, |
| 824 | amdgpu_context_handle *context); |
| 825 | |
| 826 | /** |
| 827 | * |
| 828 | * Destroy GPU execution context when not needed any more |
| 829 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 830 | * \param context - \c [in] GPU Context handle |
| 831 | * |
| 832 | * \return 0 on success\n |
| 833 | * >0 - AMD specific error code\n |
| 834 | * <0 - Negative POSIX Error code |
| 835 | * |
| 836 | * \sa amdgpu_cs_ctx_create() |
| 837 | * |
| 838 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame] | 839 | int amdgpu_cs_ctx_free(amdgpu_context_handle context); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 840 | |
| 841 | /** |
| 842 | * Query reset state for the specific GPU Context |
| 843 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 844 | * \param context - \c [in] GPU Context handle |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 845 | * \param state - \c [out] One of AMDGPU_CTX_*_RESET |
| 846 | * \param hangs - \c [out] Number of hangs caused by the context. |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 847 | * |
| 848 | * \return 0 on success\n |
| 849 | * >0 - AMD specific error code\n |
| 850 | * <0 - Negative POSIX Error code |
| 851 | * |
| 852 | * \sa amdgpu_cs_ctx_create() |
| 853 | * |
| 854 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame] | 855 | int amdgpu_cs_query_reset_state(amdgpu_context_handle context, |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 856 | uint32_t *state, uint32_t *hangs); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 857 | |
| 858 | |
| 859 | /* |
| 860 | * Command Buffers Management |
| 861 | * |
| 862 | */ |
| 863 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 864 | /** |
| 865 | * Send request to submit command buffers to hardware. |
| 866 | * |
| 867 | * Kernel driver could use GPU Scheduler to make decision when physically |
| 868 | * sent this request to the hardware. Accordingly this request could be put |
| 869 | * in queue and sent for execution later. The only guarantee is that request |
| 870 | * from the same GPU context to the same ip:ip_instance:ring will be executed in |
| 871 | * order. |
| 872 | * |
| 873 | * |
| 874 | * \param dev - \c [in] Device handle. |
| 875 | * See #amdgpu_device_initialize() |
| 876 | * \param context - \c [in] GPU Context |
| 877 | * \param flags - \c [in] Global submission flags |
| 878 | * \param ibs_request - \c [in] Pointer to submission requests. |
| 879 | * We could submit to the several |
| 880 | * engines/rings simulteniously as |
| 881 | * 'atomic' operation |
| 882 | * \param number_of_requests - \c [in] Number of submission requests |
| 883 | * \param fences - \c [out] Pointer to array of data to get |
| 884 | * fences to identify submission |
| 885 | * requests. Timestamps are valid |
| 886 | * in this GPU context and could be used |
| 887 | * to identify/detect completion of |
| 888 | * submission request |
| 889 | * |
| 890 | * \return 0 on success\n |
| 891 | * >0 - AMD specific error code\n |
| 892 | * <0 - Negative POSIX Error code |
| 893 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 894 | * \note It is required to pass correct resource list with buffer handles |
| 895 | * which will be accessible by command buffers from submission |
| 896 | * This will allow kernel driver to correctly implement "paging". |
| 897 | * Failure to do so will have unpredictable results. |
| 898 | * |
| 899 | * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), |
| 900 | * amdgpu_cs_query_fence_status() |
| 901 | * |
| 902 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame] | 903 | int amdgpu_cs_submit(amdgpu_context_handle context, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 904 | uint64_t flags, |
| 905 | struct amdgpu_cs_request *ibs_request, |
| 906 | uint32_t number_of_requests, |
| 907 | uint64_t *fences); |
| 908 | |
| 909 | /** |
| 910 | * Query status of Command Buffer Submission |
| 911 | * |
| 912 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 913 | * \param fence - \c [in] Structure describing fence to query |
| 914 | * \param expired - \c [out] If fence expired or not.\n |
| 915 | * 0 – if fence is not expired\n |
| 916 | * !0 - otherwise |
| 917 | * |
| 918 | * \return 0 on success\n |
| 919 | * >0 - AMD specific error code\n |
| 920 | * <0 - Negative POSIX Error code |
| 921 | * |
| 922 | * \note If UMD wants only to check operation status and returned immediately |
| 923 | * then timeout value as 0 must be passed. In this case success will be |
| 924 | * returned in the case if submission was completed or timeout error |
| 925 | * code. |
| 926 | * |
| 927 | * \sa amdgpu_cs_submit() |
| 928 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame] | 929 | int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 930 | uint32_t *expired); |
| 931 | |
| 932 | |
| 933 | /* |
| 934 | * Query / Info API |
| 935 | * |
| 936 | */ |
| 937 | |
| 938 | |
| 939 | /** |
| 940 | * Query allocation size alignments |
| 941 | * |
| 942 | * UMD should query information about GPU VM MC size alignments requirements |
| 943 | * to be able correctly choose required allocation size and implement |
| 944 | * internal optimization if needed. |
| 945 | * |
| 946 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 947 | * \param info - \c [out] Pointer to structure to get size alignment |
| 948 | * requirements |
| 949 | * |
| 950 | * \return 0 on success\n |
| 951 | * >0 - AMD specific error code\n |
| 952 | * <0 - Negative POSIX Error code |
| 953 | * |
| 954 | */ |
| 955 | int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, |
| 956 | struct amdgpu_buffer_size_alignments |
| 957 | *info); |
| 958 | |
| 959 | |
| 960 | |
| 961 | /** |
| 962 | * Query firmware versions |
| 963 | * |
| 964 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 965 | * \param fw_type - \c [in] AMDGPU_INFO_FW_* |
| 966 | * \param ip_instance - \c [in] Index of the IP block of the same type. |
| 967 | * \param index - \c [in] Index of the engine. (for SDMA and MEC) |
| 968 | * \param version - \c [out] Pointer to to the "version" return value |
| 969 | * \param feature - \c [out] Pointer to to the "feature" return value |
| 970 | * |
| 971 | * \return 0 on success\n |
| 972 | * >0 - AMD specific error code\n |
| 973 | * <0 - Negative POSIX Error code |
| 974 | * |
| 975 | */ |
| 976 | int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, |
| 977 | unsigned ip_instance, unsigned index, |
| 978 | uint32_t *version, uint32_t *feature); |
| 979 | |
| 980 | |
| 981 | |
| 982 | /** |
| 983 | * Query the number of HW IP instances of a certain type. |
| 984 | * |
| 985 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 986 | * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* |
| 987 | * \param count - \c [out] Pointer to structure to get information |
| 988 | * |
| 989 | * \return 0 on success\n |
| 990 | * >0 - AMD specific error code\n |
| 991 | * <0 - Negative POSIX Error code |
| 992 | */ |
| 993 | int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, |
| 994 | uint32_t *count); |
| 995 | |
| 996 | |
| 997 | |
| 998 | /** |
| 999 | * Query engine information |
| 1000 | * |
| 1001 | * This query allows UMD to query information different engines and their |
| 1002 | * capabilities. |
| 1003 | * |
| 1004 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1005 | * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* |
| 1006 | * \param ip_instance - \c [in] Index of the IP block of the same type. |
| 1007 | * \param info - \c [out] Pointer to structure to get information |
| 1008 | * |
| 1009 | * \return 0 on success\n |
| 1010 | * >0 - AMD specific error code\n |
| 1011 | * <0 - Negative POSIX Error code |
| 1012 | */ |
| 1013 | int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, |
| 1014 | unsigned ip_instance, |
| 1015 | struct drm_amdgpu_info_hw_ip *info); |
| 1016 | |
| 1017 | |
| 1018 | |
| 1019 | |
| 1020 | /** |
| 1021 | * Query heap information |
| 1022 | * |
| 1023 | * This query allows UMD to query potentially available memory resources and |
| 1024 | * adjust their logic if necessary. |
| 1025 | * |
| 1026 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1027 | * \param heap - \c [in] Heap type |
| 1028 | * \param info - \c [in] Pointer to structure to get needed information |
| 1029 | * |
| 1030 | * \return 0 on success\n |
| 1031 | * >0 - AMD specific error code\n |
| 1032 | * <0 - Negative POSIX Error code |
| 1033 | * |
| 1034 | */ |
| 1035 | int amdgpu_query_heap_info(amdgpu_device_handle dev, |
| 1036 | uint32_t heap, |
| 1037 | uint32_t flags, |
| 1038 | struct amdgpu_heap_info *info); |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | /** |
| 1043 | * Get the CRTC ID from the mode object ID |
| 1044 | * |
| 1045 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1046 | * \param id - \c [in] Mode object ID |
| 1047 | * \param result - \c [in] Pointer to the CRTC ID |
| 1048 | * |
| 1049 | * \return 0 on success\n |
| 1050 | * >0 - AMD specific error code\n |
| 1051 | * <0 - Negative POSIX Error code |
| 1052 | * |
| 1053 | */ |
| 1054 | int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, |
| 1055 | int32_t *result); |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | /** |
| 1060 | * Query GPU H/w Info |
| 1061 | * |
| 1062 | * Query hardware specific information |
| 1063 | * |
| 1064 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1065 | * \param heap - \c [in] Heap type |
| 1066 | * \param info - \c [in] Pointer to structure to get needed information |
| 1067 | * |
| 1068 | * \return 0 on success\n |
| 1069 | * >0 - AMD specific error code\n |
| 1070 | * <0 - Negative POSIX Error code |
| 1071 | * |
| 1072 | */ |
| 1073 | int amdgpu_query_gpu_info(amdgpu_device_handle dev, |
| 1074 | struct amdgpu_gpu_info *info); |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | /** |
| 1079 | * Query hardware or driver information. |
| 1080 | * |
| 1081 | * The return size is query-specific and depends on the "info_id" parameter. |
| 1082 | * No more than "size" bytes is returned. |
| 1083 | * |
| 1084 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1085 | * \param info_id - \c [in] AMDGPU_INFO_* |
| 1086 | * \param size - \c [in] Size of the returned value. |
| 1087 | * \param value - \c [out] Pointer to the return value. |
| 1088 | * |
| 1089 | * \return 0 on success\n |
| 1090 | * >0 - AMD specific error code\n |
| 1091 | * <0 - Negative POSIX error code |
| 1092 | * |
| 1093 | */ |
| 1094 | int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, |
| 1095 | unsigned size, void *value); |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | /** |
| 1100 | * Read a set of consecutive memory-mapped registers. |
| 1101 | * Not all registers are allowed to be read by userspace. |
| 1102 | * |
| 1103 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( |
| 1104 | * \param dword_offset - \c [in] Register offset in dwords |
| 1105 | * \param count - \c [in] The number of registers to read starting |
| 1106 | * from the offset |
| 1107 | * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other |
| 1108 | * uses. Set it to 0xffffffff if unsure. |
| 1109 | * \param flags - \c [in] Flags with additional information. |
| 1110 | * \param values - \c [out] The pointer to return values. |
| 1111 | * |
| 1112 | * \return 0 on success\n |
| 1113 | * >0 - AMD specific error code\n |
| 1114 | * <0 - Negative POSIX error code |
| 1115 | * |
| 1116 | */ |
| 1117 | int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, |
| 1118 | unsigned count, uint32_t instance, uint32_t flags, |
| 1119 | uint32_t *values); |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | /** |
| 1124 | * Request GPU access to user allocated memory e.g. via "malloc" |
| 1125 | * |
| 1126 | * \param dev - [in] Device handle. See #amdgpu_device_initialize() |
| 1127 | * \param cpu - [in] CPU address of user allocated memory which we |
| 1128 | * want to map to GPU address space (make GPU accessible) |
| 1129 | * (This address must be correctly aligned). |
| 1130 | * \param size - [in] Size of allocation (must be correctly aligned) |
| 1131 | * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource |
| 1132 | * on submission and be used in other operations.(e.g. for VA submission) |
| 1133 | * ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. ) |
| 1134 | * |
| 1135 | * |
| 1136 | * \return 0 on success |
| 1137 | * >0 - AMD specific error code |
| 1138 | * <0 - Negative POSIX Error code |
| 1139 | * |
| 1140 | * |
| 1141 | * \note |
| 1142 | * This call doesn't guarantee that such memory will be persistently |
| 1143 | * "locked" / make non-pageable. The purpose of this call is to provide |
| 1144 | * opportunity for GPU get access to this resource during submission. |
| 1145 | * |
| 1146 | * The maximum amount of memory which could be mapped in this call depends |
| 1147 | * if overcommit is disabled or not. If overcommit is disabled than the max. |
| 1148 | * amount of memory to be pinned will be limited by left "free" size in total |
| 1149 | * amount of memory which could be locked simultaneously ("GART" size). |
| 1150 | * |
| 1151 | * Supported (theoretical) max. size of mapping is restricted only by |
| 1152 | * "GART" size. |
| 1153 | * |
| 1154 | * It is responsibility of caller to correctly specify access rights |
| 1155 | * on VA assignment. |
| 1156 | */ |
| 1157 | int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, |
| 1158 | void *cpu, |
| 1159 | uint64_t size, |
| 1160 | struct amdgpu_bo_alloc_result *info); |
| 1161 | |
| 1162 | |
| 1163 | #endif /* #ifdef _AMDGPU_H_ */ |