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Eric Anholtc4857422008-06-03 10:20:49 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/**
29 * @file intel_bufmgr.h
30 *
31 * Public definitions of Intel-specific bufmgr functions.
32 */
33
Eric Anholt738e36a2008-09-05 10:35:32 +010034#ifndef INTEL_BUFMGR_H
35#define INTEL_BUFMGR_H
Eric Anholtc4857422008-06-03 10:20:49 -070036
Eric Anholt738e36a2008-09-05 10:35:32 +010037#include <stdint.h>
Eric Anholtc4857422008-06-03 10:20:49 -070038
Eric Anholt4b982642008-10-30 09:33:07 -070039typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
40typedef struct _drm_intel_bo drm_intel_bo;
Eric Anholt738e36a2008-09-05 10:35:32 +010041
Eric Anholt4b982642008-10-30 09:33:07 -070042struct _drm_intel_bo {
Eric Anholtd70d6052009-10-06 12:40:42 -070043 /**
44 * Size in bytes of the buffer object.
45 *
46 * The size may be larger than the size originally requested for the
47 * allocation, such as being aligned to page size.
48 */
49 unsigned long size;
Jesse Barnes276c07d2008-11-13 13:52:04 -080050
Eric Anholtd70d6052009-10-06 12:40:42 -070051 /**
52 * Alignment requirement for object
53 *
54 * Used for GTT mapping & pinning the object.
55 */
56 unsigned long align;
Eric Anholt738e36a2008-09-05 10:35:32 +010057
Eric Anholtd70d6052009-10-06 12:40:42 -070058 /**
Eric Anholt02c775f2009-10-06 15:25:21 -070059 * Last seen card virtual address (offset from the beginning of the
60 * aperture) for the object. This should be used to fill relocation
61 * entries when calling drm_intel_bo_emit_reloc()
Eric Anholtd70d6052009-10-06 12:40:42 -070062 */
63 unsigned long offset;
Jesse Barnes731cd552008-12-17 10:09:49 -080064
Eric Anholtd70d6052009-10-06 12:40:42 -070065 /**
66 * Virtual address for accessing the buffer data. Only valid while
67 * mapped.
68 */
69 void *virtual;
70
71 /** Buffer manager context associated with this buffer object */
72 drm_intel_bufmgr *bufmgr;
73
74 /**
75 * MM-specific handle for accessing object
76 */
77 int handle;
Eric Anholtc4857422008-06-03 10:20:49 -070078};
79
Jesse Barnes3a7dfcd2009-10-06 14:34:06 -070080#define BO_ALLOC_FOR_RENDER (1<<0)
81
Eric Anholt4b982642008-10-30 09:33:07 -070082drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
83 unsigned long size, unsigned int alignment);
Eric Anholt72abe982009-02-18 13:06:35 -080084drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
85 const char *name,
86 unsigned long size,
87 unsigned int alignment);
Jesse Barnes3a7dfcd2009-10-06 14:34:06 -070088drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
89 const char *name,
90 int x, int y, int cpp,
91 uint32_t *tiling_mode,
92 unsigned long *pitch,
93 unsigned long flags);
Eric Anholt4b982642008-10-30 09:33:07 -070094void drm_intel_bo_reference(drm_intel_bo *bo);
95void drm_intel_bo_unreference(drm_intel_bo *bo);
96int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
97int drm_intel_bo_unmap(drm_intel_bo *bo);
Eric Anholt738e36a2008-09-05 10:35:32 +010098
Eric Anholt4b982642008-10-30 09:33:07 -070099int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
Eric Anholtd70d6052009-10-06 12:40:42 -0700100 unsigned long size, const void *data);
Eric Anholt4b982642008-10-30 09:33:07 -0700101int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
Eric Anholtd70d6052009-10-06 12:40:42 -0700102 unsigned long size, void *data);
Eric Anholt4b982642008-10-30 09:33:07 -0700103void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
Eric Anholt738e36a2008-09-05 10:35:32 +0100104
Eric Anholt4b982642008-10-30 09:33:07 -0700105void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
106void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
107int drm_intel_bo_exec(drm_intel_bo *bo, int used,
Eric Anholtd70d6052009-10-06 12:40:42 -0700108 drm_clip_rect_t * cliprects, int num_cliprects, int DR4);
109int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
Eric Anholt738e36a2008-09-05 10:35:32 +0100110
Eric Anholt4b982642008-10-30 09:33:07 -0700111int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
112 drm_intel_bo *target_bo, uint32_t target_offset,
113 uint32_t read_domains, uint32_t write_domain);
114int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
115int drm_intel_bo_unpin(drm_intel_bo *bo);
Eric Anholtd70d6052009-10-06 12:40:42 -0700116int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
Eric Anholt4b982642008-10-30 09:33:07 -0700117 uint32_t stride);
Eric Anholtd70d6052009-10-06 12:40:42 -0700118int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
119 uint32_t * swizzle_mode);
120int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
Eric Anholt8214a652009-08-27 18:32:07 -0700121int drm_intel_bo_busy(drm_intel_bo *bo);
Chris Wilson83a35b62009-11-11 13:04:38 +0000122int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
Eric Anholt738e36a2008-09-05 10:35:32 +0100123
Keith Packard5b5ce302009-05-11 13:42:12 -0700124int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
Eric Anholt769b1052009-10-01 19:09:26 -0700125int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
Keith Packard5b5ce302009-05-11 13:42:12 -0700126
Eric Anholt4b982642008-10-30 09:33:07 -0700127/* drm_intel_bufmgr_gem.c */
128drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
129drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
130 const char *name,
131 unsigned int handle);
132void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
Jesse Barnes276c07d2008-11-13 13:52:04 -0800133int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
Jesse Barnese2d7dfb2009-03-26 16:43:00 -0700134int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
Eric Anholt6fb1ad72008-11-13 11:44:22 -0800135void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
Eric Anholtc4857422008-06-03 10:20:49 -0700136
Carl Worthafd245d2009-04-29 14:43:55 -0700137int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
138
Eric Anholt4b982642008-10-30 09:33:07 -0700139/* drm_intel_bufmgr_fake.c */
140drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
141 unsigned long low_offset,
142 void *low_virtual,
143 unsigned long size,
Eric Anholtd70d6052009-10-06 12:40:42 -0700144 volatile unsigned int
145 *last_dispatch);
Eric Anholt4b982642008-10-30 09:33:07 -0700146void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700147 volatile unsigned int
148 *last_dispatch);
Eric Anholt4b982642008-10-30 09:33:07 -0700149void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700150 int (*exec) (drm_intel_bo *bo,
151 unsigned int used,
152 void *priv),
Eric Anholt4b982642008-10-30 09:33:07 -0700153 void *priv);
154void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700155 unsigned int (*emit) (void *priv),
156 void (*wait) (unsigned int fence,
157 void *priv),
Eric Anholt4b982642008-10-30 09:33:07 -0700158 void *priv);
159drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
160 const char *name,
Eric Anholtd70d6052009-10-06 12:40:42 -0700161 unsigned long offset,
162 unsigned long size, void *virtual);
Eric Anholt4b982642008-10-30 09:33:07 -0700163void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
Eric Anholtd70d6052009-10-06 12:40:42 -0700164 void (*invalidate_cb) (drm_intel_bo
165 * bo,
166 void *ptr),
Eric Anholt4b982642008-10-30 09:33:07 -0700167 void *ptr);
Eric Anholt738e36a2008-09-05 10:35:32 +0100168
Eric Anholt4b982642008-10-30 09:33:07 -0700169void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
170void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
171
172/** @{ Compatibility defines to keep old code building despite the symbol rename
173 * from dri_* to drm_intel_*
174 */
175#define dri_bo drm_intel_bo
176#define dri_bufmgr drm_intel_bufmgr
177#define dri_bo_alloc drm_intel_bo_alloc
178#define dri_bo_reference drm_intel_bo_reference
179#define dri_bo_unreference drm_intel_bo_unreference
180#define dri_bo_map drm_intel_bo_map
181#define dri_bo_unmap drm_intel_bo_unmap
182#define dri_bo_subdata drm_intel_bo_subdata
183#define dri_bo_get_subdata drm_intel_bo_get_subdata
184#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
185#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
186#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
187#define dri_bo_exec drm_intel_bo_exec
188#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
189#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
190 reloc_offset, target_bo) \
191 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
Eric Anholtd70d6052009-10-06 12:40:42 -0700192 target_bo, target_offset, \
193 read, write);
Eric Anholt4b982642008-10-30 09:33:07 -0700194#define dri_bo_pin drm_intel_bo_pin
195#define dri_bo_unpin drm_intel_bo_unpin
196#define dri_bo_get_tiling drm_intel_bo_get_tiling
197#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
198#define dri_bo_flink drm_intel_bo_flink
199#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
200#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
201#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
202#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
203#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
204#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
205#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
206#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
207#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
208#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
209#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
210
211/** @{ */
Eric Anholtc4857422008-06-03 10:20:49 -0700212
Eric Anholt738e36a2008-09-05 10:35:32 +0100213#endif /* INTEL_BUFMGR_H */