Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | /** |
| 25 | * \file amdgpu.h |
| 26 | * |
| 27 | * Declare public libdrm_amdgpu API |
| 28 | * |
| 29 | * This file define API exposed by libdrm_amdgpu library. |
| 30 | * User wanted to use libdrm_amdgpu functionality must include |
| 31 | * this file. |
| 32 | * |
| 33 | */ |
| 34 | #ifndef _AMDGPU_H_ |
| 35 | #define _AMDGPU_H_ |
| 36 | |
| 37 | #include <stdint.h> |
| 38 | #include <stdbool.h> |
| 39 | |
| 40 | struct drm_amdgpu_info_hw_ip; |
| 41 | |
| 42 | /*--------------------------------------------------------------------------*/ |
| 43 | /* --------------------------- Defines ------------------------------------ */ |
| 44 | /*--------------------------------------------------------------------------*/ |
| 45 | |
| 46 | /** |
| 47 | * Define max. number of Command Buffers (IB) which could be sent to the single |
| 48 | * hardware IP to accommodate CE/DE requirements |
| 49 | * |
| 50 | * \sa amdgpu_cs_ib_info |
| 51 | */ |
| 52 | #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 |
| 53 | |
| 54 | /** |
| 55 | * |
| 56 | */ |
| 57 | #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull |
| 58 | |
| 59 | /** |
| 60 | * The special flag for GFX submission to identify that this is CE IB |
| 61 | * \sa amdgpu_cs_ib_info |
| 62 | */ |
| 63 | #define AMDGPU_CS_GFX_IB_CE 0x1 |
| 64 | |
| 65 | /** |
| 66 | * The special flag to mark that this IB will re-used |
| 67 | * by client and should not be automatically return back |
| 68 | * to free pool by libdrm_amdgpu when submission is completed. |
| 69 | * |
| 70 | * \sa amdgpu_cs_ib_info |
| 71 | */ |
| 72 | #define AMDGPU_CS_REUSE_IB 0x2 |
| 73 | |
| 74 | /** |
| 75 | * The special resource flag for IB submission. |
| 76 | * When VRAM is full, some resources may be moved to GTT to make place |
| 77 | * for other resources which want to be in VRAM. This flag affects the order |
| 78 | * in which resources are moved back to VRAM until there is no space there. |
| 79 | * The resources with the highest priority will be moved first. |
| 80 | * The value can be between 0 and 15, inclusive. |
| 81 | */ |
| 82 | #define AMDGPU_IB_RESOURCE_PRIORITY(x) ((x) & 0xf) |
| 83 | |
| 84 | |
| 85 | /*--------------------------------------------------------------------------*/ |
| 86 | /* ----------------------------- Enums ------------------------------------ */ |
| 87 | /*--------------------------------------------------------------------------*/ |
| 88 | |
| 89 | /** |
| 90 | * Enum describing possible handle types |
| 91 | * |
| 92 | * \sa amdgpu_bo_import, amdgpu_bo_export |
| 93 | * |
| 94 | */ |
| 95 | enum amdgpu_bo_handle_type { |
| 96 | /** GEM flink name (needs DRM authentication, used by DRI2) */ |
| 97 | amdgpu_bo_handle_type_gem_flink_name = 0, |
| 98 | |
| 99 | /** KMS handle which is used by all driver ioctls */ |
| 100 | amdgpu_bo_handle_type_kms = 1, |
| 101 | |
| 102 | /** DMA-buf fd handle */ |
| 103 | amdgpu_bo_handle_type_dma_buf_fd = 2 |
| 104 | }; |
| 105 | |
| 106 | /** |
| 107 | * Enum describing possible context reset states |
| 108 | * |
| 109 | * \sa amdgpu_cs_query_reset_state() |
| 110 | * |
| 111 | */ |
| 112 | enum amdgpu_cs_ctx_reset_state { |
| 113 | /** No reset was detected */ |
| 114 | amdgpu_cs_reset_no_error = 0, |
| 115 | |
| 116 | /** Reset/TDR was detected and context caused */ |
| 117 | amdgpu_cs_reset_guilty = 1, |
| 118 | |
| 119 | /** Reset/TDR was detected caused by other context */ |
| 120 | amdgpu_cs_reset_innocent = 2, |
| 121 | |
| 122 | /** Reset TDR was detected by cause of it unknown */ |
| 123 | amdgpu_cs_reset_unknown = 3 |
| 124 | }; |
| 125 | |
| 126 | /** |
| 127 | * For performance reasons and to simplify logic libdrm_amdgpu will handle |
| 128 | * IBs only some pre-defined sizes. |
| 129 | * |
| 130 | * \sa amdgpu_cs_alloc_ib() |
| 131 | */ |
| 132 | enum amdgpu_cs_ib_size { |
| 133 | amdgpu_cs_ib_size_4K = 1, |
| 134 | amdgpu_cs_ib_size_16K = 2, |
| 135 | amdgpu_cs_ib_size_32K = 3, |
| 136 | amdgpu_cs_ib_size_64K = 4, |
| 137 | amdgpu_cs_ib_size_128K = 5 |
| 138 | }; |
| 139 | |
| 140 | /** The number of different IB sizes */ |
| 141 | #define AMDGPU_CS_IB_SIZE_NUM 6 |
| 142 | |
| 143 | |
| 144 | /*--------------------------------------------------------------------------*/ |
| 145 | /* -------------------------- Datatypes ----------------------------------- */ |
| 146 | /*--------------------------------------------------------------------------*/ |
| 147 | |
| 148 | /** |
| 149 | * Define opaque pointer to context associated with fd. |
| 150 | * This context will be returned as the result of |
| 151 | * "initialize" function and should be pass as the first |
| 152 | * parameter to any API call |
| 153 | */ |
| 154 | typedef struct amdgpu_device *amdgpu_device_handle; |
| 155 | |
| 156 | /** |
| 157 | * Define GPU Context type as pointer to opaque structure |
| 158 | * Example of GPU Context is the "rendering" context associated |
| 159 | * with OpenGL context (glCreateContext) |
| 160 | */ |
| 161 | typedef struct amdgpu_context *amdgpu_context_handle; |
| 162 | |
| 163 | /** |
| 164 | * Define handle for amdgpu resources: buffer, GDS, etc. |
| 165 | */ |
| 166 | typedef struct amdgpu_bo *amdgpu_bo_handle; |
| 167 | |
| 168 | /** |
| 169 | * Define handle to be used when dealing with command |
| 170 | * buffers (a.k.a. ibs) |
| 171 | * |
| 172 | */ |
| 173 | typedef struct amdgpu_ib *amdgpu_ib_handle; |
| 174 | |
| 175 | |
| 176 | /*--------------------------------------------------------------------------*/ |
| 177 | /* -------------------------- Structures ---------------------------------- */ |
| 178 | /*--------------------------------------------------------------------------*/ |
| 179 | |
| 180 | /** |
| 181 | * Structure describing memory allocation request |
| 182 | * |
| 183 | * \sa amdgpu_bo_alloc() |
| 184 | * |
| 185 | */ |
| 186 | struct amdgpu_bo_alloc_request { |
| 187 | /** Allocation request. It must be aligned correctly. */ |
| 188 | uint64_t alloc_size; |
| 189 | |
| 190 | /** |
| 191 | * It may be required to have some specific alignment requirements |
| 192 | * for physical back-up storage (e.g. for displayable surface). |
| 193 | * If 0 there is no special alignment requirement |
| 194 | */ |
| 195 | uint64_t phys_alignment; |
| 196 | |
| 197 | /** |
| 198 | * UMD should specify where to allocate memory and how it |
| 199 | * will be accessed by the CPU. |
| 200 | */ |
| 201 | uint32_t preferred_heap; |
| 202 | |
| 203 | /** Additional flags passed on allocation */ |
| 204 | uint64_t flags; |
| 205 | }; |
| 206 | |
| 207 | /** |
| 208 | * Structure describing memory allocation request |
| 209 | * |
| 210 | * \sa amdgpu_bo_alloc() |
| 211 | */ |
| 212 | struct amdgpu_bo_alloc_result { |
| 213 | /** Assigned virtual MC Base Address */ |
| 214 | uint64_t virtual_mc_base_address; |
| 215 | |
| 216 | /** Handle of allocated memory to be used by the given process only. */ |
| 217 | amdgpu_bo_handle buf_handle; |
| 218 | }; |
| 219 | |
| 220 | /** |
| 221 | * Special UMD specific information associated with buffer. |
| 222 | * |
| 223 | * It may be need to pass some buffer charactersitic as part |
| 224 | * of buffer sharing. Such information are defined UMD and |
| 225 | * opaque for libdrm_amdgpu as well for kernel driver. |
| 226 | * |
| 227 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, |
| 228 | * amdgpu_bo_import(), amdgpu_bo_export |
| 229 | * |
| 230 | */ |
| 231 | struct amdgpu_bo_metadata { |
| 232 | /** Special flag associated with surface */ |
| 233 | uint64_t flags; |
| 234 | |
| 235 | /** |
| 236 | * ASIC-specific tiling information (also used by DCE). |
| 237 | * The encoding is defined by the AMDGPU_TILING_* definitions. |
| 238 | */ |
| 239 | uint64_t tiling_info; |
| 240 | |
| 241 | /** Size of metadata associated with the buffer, in bytes. */ |
| 242 | uint32_t size_metadata; |
| 243 | |
| 244 | /** UMD specific metadata. Opaque for kernel */ |
| 245 | uint32_t umd_metadata[64]; |
| 246 | }; |
| 247 | |
| 248 | /** |
| 249 | * Structure describing allocated buffer. Client may need |
| 250 | * to query such information as part of 'sharing' buffers mechanism |
| 251 | * |
| 252 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), |
| 253 | * amdgpu_bo_import(), amdgpu_bo_export() |
| 254 | */ |
| 255 | struct amdgpu_bo_info { |
| 256 | /** Allocated memory size */ |
| 257 | uint64_t alloc_size; |
| 258 | |
| 259 | /** |
| 260 | * It may be required to have some specific alignment requirements |
| 261 | * for physical back-up storage. |
| 262 | */ |
| 263 | uint64_t phys_alignment; |
| 264 | |
| 265 | /** |
| 266 | * Assigned virtual MC Base Address. |
| 267 | * \note This information will be returned only if this buffer was |
| 268 | * allocated in the same process otherwise 0 will be returned. |
| 269 | */ |
| 270 | uint64_t virtual_mc_base_address; |
| 271 | |
| 272 | /** Heap where to allocate memory. */ |
| 273 | uint32_t preferred_heap; |
| 274 | |
| 275 | /** Additional allocation flags. */ |
| 276 | uint64_t alloc_flags; |
| 277 | |
| 278 | /** Metadata associated with buffer if any. */ |
| 279 | struct amdgpu_bo_metadata metadata; |
| 280 | }; |
| 281 | |
| 282 | /** |
| 283 | * Structure with information about "imported" buffer |
| 284 | * |
| 285 | * \sa amdgpu_bo_import() |
| 286 | * |
| 287 | */ |
| 288 | struct amdgpu_bo_import_result { |
| 289 | /** Handle of memory/buffer to use */ |
| 290 | amdgpu_bo_handle buf_handle; |
| 291 | |
| 292 | /** Buffer size */ |
| 293 | uint64_t alloc_size; |
| 294 | |
| 295 | /** Assigned virtual MC Base Address */ |
| 296 | uint64_t virtual_mc_base_address; |
| 297 | }; |
| 298 | |
| 299 | |
| 300 | /** |
| 301 | * |
| 302 | * Structure to describe GDS partitioning information. |
| 303 | * \note OA and GWS resources are asscoiated with GDS partition |
| 304 | * |
| 305 | * \sa amdgpu_gpu_resource_query_gds_info |
| 306 | * |
| 307 | */ |
| 308 | struct amdgpu_gds_resource_info { |
| 309 | uint32_t gds_gfx_partition_size; |
| 310 | uint32_t compute_partition_size; |
| 311 | uint32_t gds_total_size; |
| 312 | uint32_t gws_per_gfx_partition; |
| 313 | uint32_t gws_per_compute_partition; |
| 314 | uint32_t oa_per_gfx_partition; |
| 315 | uint32_t oa_per_compute_partition; |
| 316 | }; |
| 317 | |
| 318 | |
| 319 | |
| 320 | /** |
| 321 | * Structure describing result of request to allocate GDS |
| 322 | * |
| 323 | * \sa amdgpu_gpu_resource_gds_alloc |
| 324 | * |
| 325 | */ |
| 326 | struct amdgpu_gds_alloc_info { |
| 327 | /** Handle assigned to gds allocation */ |
| 328 | amdgpu_bo_handle resource_handle; |
| 329 | |
| 330 | /** How much was really allocated */ |
| 331 | uint32_t gds_memory_size; |
| 332 | |
| 333 | /** Number of GWS resources allocated */ |
| 334 | uint32_t gws; |
| 335 | |
| 336 | /** Number of OA resources allocated */ |
| 337 | uint32_t oa; |
| 338 | }; |
| 339 | |
| 340 | /** |
| 341 | * Structure to described allocated command buffer (a.k.a. IB) |
| 342 | * |
| 343 | * \sa amdgpu_cs_alloc_ib() |
| 344 | * |
| 345 | */ |
| 346 | struct amdgpu_cs_ib_alloc_result { |
| 347 | /** IB allocation handle */ |
| 348 | amdgpu_ib_handle handle; |
| 349 | |
| 350 | /** Assigned GPU VM MC Address of command buffer */ |
| 351 | uint64_t mc_address; |
| 352 | |
| 353 | /** Address to be used for CPU access */ |
| 354 | void *cpu; |
| 355 | }; |
| 356 | |
| 357 | /** |
| 358 | * Structure describing IB |
| 359 | * |
| 360 | * \sa amdgpu_cs_request, amdgpu_cs_submit() |
| 361 | * |
| 362 | */ |
| 363 | struct amdgpu_cs_ib_info { |
| 364 | /** Special flags */ |
| 365 | uint64_t flags; |
| 366 | |
| 367 | /** Handle of command buffer */ |
| 368 | amdgpu_ib_handle ib_handle; |
| 369 | |
| 370 | /** |
| 371 | * Size of Command Buffer to be submitted. |
| 372 | * - The size is in units of dwords (4 bytes). |
| 373 | * - Must be less or equal to the size of allocated IB |
| 374 | * - Could be 0 |
| 375 | */ |
| 376 | uint32_t size; |
| 377 | }; |
| 378 | |
| 379 | /** |
| 380 | * Structure describing submission request |
| 381 | * |
| 382 | * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx |
| 383 | * |
| 384 | * \sa amdgpu_cs_submit() |
| 385 | */ |
| 386 | struct amdgpu_cs_request { |
| 387 | /** Specify flags with additional information */ |
| 388 | uint64_t flags; |
| 389 | |
| 390 | /** Specify HW IP block type to which to send the IB. */ |
| 391 | unsigned ip_type; |
| 392 | |
| 393 | /** IP instance index if there are several IPs of the same type. */ |
| 394 | unsigned ip_instance; |
| 395 | |
| 396 | /** |
| 397 | * Specify ring index of the IP. We could have several rings |
| 398 | * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. |
| 399 | */ |
| 400 | uint32_t ring; |
| 401 | |
| 402 | /** |
| 403 | * Specify number of resource handles passed. |
| 404 | * Size of 'handles' array |
| 405 | * |
| 406 | */ |
| 407 | uint32_t number_of_resources; |
| 408 | |
| 409 | /** Array of resources used by submission. */ |
| 410 | amdgpu_bo_handle *resources; |
| 411 | |
| 412 | /** Array of resources flags. This is optional and can be NULL. */ |
| 413 | uint8_t *resource_flags; |
| 414 | |
| 415 | /** Number of IBs to submit in the field ibs. */ |
| 416 | uint32_t number_of_ibs; |
| 417 | |
| 418 | /** |
| 419 | * IBs to submit. Those IBs will be submit together as single entity |
| 420 | */ |
| 421 | struct amdgpu_cs_ib_info *ibs; |
| 422 | }; |
| 423 | |
| 424 | /** |
| 425 | * Structure describing request to check submission state using fence |
| 426 | * |
| 427 | * \sa amdgpu_cs_query_fence_status() |
| 428 | * |
| 429 | */ |
| 430 | struct amdgpu_cs_query_fence { |
| 431 | |
| 432 | /** In which context IB was sent to execution */ |
| 433 | amdgpu_context_handle context; |
| 434 | |
| 435 | /** Timeout in nanoseconds. */ |
| 436 | uint64_t timeout_ns; |
| 437 | |
| 438 | /** To which HW IP type the fence belongs */ |
| 439 | unsigned ip_type; |
| 440 | |
| 441 | /** IP instance index if there are several IPs of the same type. */ |
| 442 | unsigned ip_instance; |
| 443 | |
| 444 | /** Ring index of the HW IP */ |
| 445 | uint32_t ring; |
| 446 | |
| 447 | /** Flags */ |
| 448 | uint64_t flags; |
| 449 | |
| 450 | /** Specify fence for which we need to check |
| 451 | * submission status.*/ |
| 452 | uint64_t fence; |
| 453 | }; |
| 454 | |
| 455 | /** |
| 456 | * Structure which provide information about GPU VM MC Address space |
| 457 | * alignments requirements |
| 458 | * |
| 459 | * \sa amdgpu_query_buffer_size_alignment |
| 460 | */ |
| 461 | struct amdgpu_buffer_size_alignments { |
| 462 | /** Size alignment requirement for allocation in |
| 463 | * local memory */ |
| 464 | uint64_t size_local; |
| 465 | |
| 466 | /** |
| 467 | * Size alignment requirement for allocation in remote memory |
| 468 | */ |
| 469 | uint64_t size_remote; |
| 470 | }; |
| 471 | |
| 472 | |
| 473 | /** |
| 474 | * Structure which provide information about heap |
| 475 | * |
| 476 | * \sa amdgpu_query_heap_info() |
| 477 | * |
| 478 | */ |
| 479 | struct amdgpu_heap_info { |
| 480 | /** Theoretical max. available memory in the given heap */ |
| 481 | uint64_t heap_size; |
| 482 | |
| 483 | /** |
| 484 | * Number of bytes allocated in the heap. This includes all processes |
| 485 | * and private allocations in the kernel. It changes when new buffers |
| 486 | * are allocated, freed, and moved. It cannot be larger than |
| 487 | * heap_size. |
| 488 | */ |
| 489 | uint64_t heap_usage; |
| 490 | |
| 491 | /** |
| 492 | * Theoretical possible max. size of buffer which |
| 493 | * could be allocated in the given heap |
| 494 | */ |
| 495 | uint64_t max_allocation; |
| 496 | }; |
| 497 | |
| 498 | |
| 499 | |
| 500 | /** |
| 501 | * Describe GPU h/w info needed for UMD correct initialization |
| 502 | * |
| 503 | * \sa amdgpu_query_gpu_info() |
| 504 | */ |
| 505 | struct amdgpu_gpu_info { |
| 506 | /** Asic id */ |
| 507 | uint32_t asic_id; |
| 508 | /**< Chip revision */ |
| 509 | uint32_t chip_rev; |
| 510 | /** Chip external revision */ |
| 511 | uint32_t chip_external_rev; |
| 512 | /** Family ID */ |
| 513 | uint32_t family_id; |
| 514 | /** Special flags */ |
| 515 | uint64_t ids_flags; |
| 516 | /** max engine clock*/ |
| 517 | uint64_t max_engine_clk; |
| 518 | /** number of shader engines */ |
| 519 | uint32_t num_shader_engines; |
| 520 | /** number of shader arrays per engine */ |
| 521 | uint32_t num_shader_arrays_per_engine; |
| 522 | /** Number of available good shader pipes */ |
| 523 | uint32_t avail_quad_shader_pipes; |
| 524 | /** Max. number of shader pipes.(including good and bad pipes */ |
| 525 | uint32_t max_quad_shader_pipes; |
| 526 | /** Number of parameter cache entries per shader quad pipe */ |
| 527 | uint32_t cache_entries_per_quad_pipe; |
| 528 | /** Number of available graphics context */ |
| 529 | uint32_t num_hw_gfx_contexts; |
| 530 | /** Number of render backend pipes */ |
| 531 | uint32_t rb_pipes; |
| 532 | /** Active render backend pipe number */ |
| 533 | uint32_t active_rb_pipes; |
| 534 | /** Enabled render backend pipe mask */ |
| 535 | uint32_t enabled_rb_pipes_mask; |
| 536 | /** Frequency of GPU Counter */ |
| 537 | uint32_t gpu_counter_freq; |
| 538 | /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ |
| 539 | uint32_t backend_disable[4]; |
| 540 | /** Value of MC_ARB_RAMCFG register*/ |
| 541 | uint32_t mc_arb_ramcfg; |
| 542 | /** Value of GB_ADDR_CONFIG */ |
| 543 | uint32_t gb_addr_cfg; |
| 544 | /** Values of the GB_TILE_MODE0..31 registers */ |
| 545 | uint32_t gb_tile_mode[32]; |
| 546 | /** Values of GB_MACROTILE_MODE0..15 registers */ |
| 547 | uint32_t gb_macro_tile_mode[16]; |
| 548 | /** Value of PA_SC_RASTER_CONFIG register per SE */ |
| 549 | uint32_t pa_sc_raster_cfg[4]; |
| 550 | /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ |
| 551 | uint32_t pa_sc_raster_cfg1[4]; |
| 552 | /* CU info */ |
| 553 | uint32_t cu_active_number; |
| 554 | uint32_t cu_ao_mask; |
| 555 | uint32_t cu_bitmap[4][4]; |
| 556 | }; |
| 557 | |
| 558 | |
| 559 | /*--------------------------------------------------------------------------*/ |
| 560 | /*------------------------- Functions --------------------------------------*/ |
| 561 | /*--------------------------------------------------------------------------*/ |
| 562 | |
| 563 | /* |
| 564 | * Initialization / Cleanup |
| 565 | * |
| 566 | */ |
| 567 | |
| 568 | |
| 569 | /** |
| 570 | * |
| 571 | * \param fd - \c [in] File descriptor for AMD GPU device |
| 572 | * received previously as the result of |
| 573 | * e.g. drmOpen() call. |
| 574 | * For legacy fd type, the DRI2/DRI3 authentication |
| 575 | * should be done before calling this function. |
| 576 | * \param major_version - \c [out] Major version of library. It is assumed |
| 577 | * that adding new functionality will cause |
| 578 | * increase in major version |
| 579 | * \param minor_version - \c [out] Minor version of library |
| 580 | * \param device_handle - \c [out] Pointer to opaque context which should |
| 581 | * be passed as the first parameter on each |
| 582 | * API call |
| 583 | * |
| 584 | * |
| 585 | * \return 0 on success\n |
| 586 | * >0 - AMD specific error code\n |
| 587 | * <0 - Negative POSIX Error code |
| 588 | * |
| 589 | * |
| 590 | * \sa amdgpu_device_deinitialize() |
| 591 | */ |
| 592 | int amdgpu_device_initialize(int fd, |
| 593 | uint32_t *major_version, |
| 594 | uint32_t *minor_version, |
| 595 | amdgpu_device_handle *device_handle); |
| 596 | |
| 597 | |
| 598 | |
| 599 | /** |
| 600 | * |
| 601 | * When access to such library does not needed any more the special |
| 602 | * function must be call giving opportunity to clean up any |
| 603 | * resources if needed. |
| 604 | * |
| 605 | * \param device_handle - \c [in] Context associated with file |
| 606 | * descriptor for AMD GPU device |
| 607 | * received previously as the |
| 608 | * result e.g. of drmOpen() call. |
| 609 | * |
| 610 | * \return 0 on success\n |
| 611 | * >0 - AMD specific error code\n |
| 612 | * <0 - Negative POSIX Error code |
| 613 | * |
| 614 | * \sa amdgpu_device_initialize() |
| 615 | * |
| 616 | */ |
| 617 | int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); |
| 618 | |
| 619 | |
| 620 | /* |
| 621 | * Memory Management |
| 622 | * |
| 623 | */ |
| 624 | |
| 625 | /** |
| 626 | * Allocate memory to be used by UMD for GPU related operations |
| 627 | * |
| 628 | * \param dev - \c [in] Device handle. |
| 629 | * See #amdgpu_device_initialize() |
| 630 | * \param alloc_buffer - \c [in] Pointer to the structure describing an |
| 631 | * allocation request |
| 632 | * \param info - \c [out] Pointer to structure which return |
| 633 | * information about allocated memory |
| 634 | * |
| 635 | * \return 0 on success\n |
| 636 | * >0 - AMD specific error code\n |
| 637 | * <0 - Negative POSIX Error code |
| 638 | * |
| 639 | * \sa amdgpu_bo_free() |
| 640 | */ |
| 641 | int amdgpu_bo_alloc(amdgpu_device_handle dev, |
| 642 | struct amdgpu_bo_alloc_request *alloc_buffer, |
| 643 | struct amdgpu_bo_alloc_result *info); |
| 644 | |
| 645 | /** |
| 646 | * Associate opaque data with buffer to be queried by another UMD |
| 647 | * |
| 648 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 649 | * \param buf_handle - \c [in] Buffer handle |
| 650 | * \param info - \c [in] Metadata to associated with buffer |
| 651 | * |
| 652 | * \return 0 on success\n |
| 653 | * >0 - AMD specific error code\n |
| 654 | * <0 - Negative POSIX Error code |
| 655 | */ |
| 656 | int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, |
| 657 | struct amdgpu_bo_metadata *info); |
| 658 | |
| 659 | /** |
| 660 | * Query buffer information including metadata previusly associated with |
| 661 | * buffer. |
| 662 | * |
| 663 | * \param dev - \c [in] Device handle. |
| 664 | * See #amdgpu_device_initialize() |
| 665 | * \param buf_handle - \c [in] Buffer handle |
| 666 | * \param info - \c [out] Structure describing buffer |
| 667 | * |
| 668 | * \return 0 on success\n |
| 669 | * >0 - AMD specific error code\n |
| 670 | * <0 - Negative POSIX Error code |
| 671 | * |
| 672 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() |
| 673 | */ |
| 674 | int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, |
| 675 | struct amdgpu_bo_info *info); |
| 676 | |
| 677 | /** |
| 678 | * Allow others to get access to buffer |
| 679 | * |
| 680 | * \param dev - \c [in] Device handle. |
| 681 | * See #amdgpu_device_initialize() |
| 682 | * \param buf_handle - \c [in] Buffer handle |
| 683 | * \param type - \c [in] Type of handle requested |
| 684 | * \param shared_handle - \c [out] Special "shared" handle |
| 685 | * |
| 686 | * \return 0 on success\n |
| 687 | * >0 - AMD specific error code\n |
| 688 | * <0 - Negative POSIX Error code |
| 689 | * |
| 690 | * \sa amdgpu_bo_import() |
| 691 | * |
| 692 | */ |
| 693 | int amdgpu_bo_export(amdgpu_bo_handle buf_handle, |
| 694 | enum amdgpu_bo_handle_type type, |
| 695 | uint32_t *shared_handle); |
| 696 | |
| 697 | /** |
| 698 | * Request access to "shared" buffer |
| 699 | * |
| 700 | * \param dev - \c [in] Device handle. |
| 701 | * See #amdgpu_device_initialize() |
| 702 | * \param type - \c [in] Type of handle requested |
| 703 | * \param shared_handle - \c [in] Shared handle received as result "import" |
| 704 | * operation |
| 705 | * \param output - \c [out] Pointer to structure with information |
| 706 | * about imported buffer |
| 707 | * |
| 708 | * \return 0 on success\n |
| 709 | * >0 - AMD specific error code\n |
| 710 | * <0 - Negative POSIX Error code |
| 711 | * |
| 712 | * \note Buffer must be "imported" only using new "fd" (different from |
| 713 | * one used by "exporter"). |
| 714 | * |
| 715 | * \sa amdgpu_bo_export() |
| 716 | * |
| 717 | */ |
| 718 | int amdgpu_bo_import(amdgpu_device_handle dev, |
| 719 | enum amdgpu_bo_handle_type type, |
| 720 | uint32_t shared_handle, |
| 721 | struct amdgpu_bo_import_result *output); |
| 722 | |
| 723 | /** |
| 724 | * Free previosuly allocated memory |
| 725 | * |
| 726 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 727 | * \param buf_handle - \c [in] Buffer handle to free |
| 728 | * |
| 729 | * \return 0 on success\n |
| 730 | * >0 - AMD specific error code\n |
| 731 | * <0 - Negative POSIX Error code |
| 732 | * |
| 733 | * \note In the case of memory shared between different applications all |
| 734 | * resources will be “physically” freed only all such applications |
| 735 | * will be terminated |
| 736 | * \note If is UMD responsibility to ‘free’ buffer only when there is no |
| 737 | * more GPU access |
| 738 | * |
| 739 | * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() |
| 740 | * |
| 741 | */ |
| 742 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle); |
| 743 | |
| 744 | /** |
| 745 | * Request CPU access to GPU accessable memory |
| 746 | * |
| 747 | * \param buf_handle - \c [in] Buffer handle |
| 748 | * \param cpu - \c [out] CPU address to be used for access |
| 749 | * |
| 750 | * \return 0 on success\n |
| 751 | * >0 - AMD specific error code\n |
| 752 | * <0 - Negative POSIX Error code |
| 753 | * |
| 754 | * \sa amdgpu_bo_cpu_unmap() |
| 755 | * |
| 756 | */ |
| 757 | int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); |
| 758 | |
| 759 | /** |
| 760 | * Release CPU access to GPU memory |
| 761 | * |
| 762 | * \param buf_handle - \c [in] Buffer handle |
| 763 | * |
| 764 | * \return 0 on success\n |
| 765 | * >0 - AMD specific error code\n |
| 766 | * <0 - Negative POSIX Error code |
| 767 | * |
| 768 | * \sa amdgpu_bo_cpu_map() |
| 769 | * |
| 770 | */ |
| 771 | int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); |
| 772 | |
| 773 | |
| 774 | /** |
| 775 | * Wait until a buffer is not used by the device. |
| 776 | * |
| 777 | * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize() |
| 778 | * \param buf_handle - \c [in] Buffer handle. |
| 779 | * \param timeout_ns - Timeout in nanoseconds. |
| 780 | * \param buffer_busy - 0 if buffer is idle, all GPU access was completed |
| 781 | * and no GPU access is scheduled. |
| 782 | * 1 GPU access is in fly or scheduled |
| 783 | * |
| 784 | * \return 0 - on success |
| 785 | * <0 - AMD specific error code |
| 786 | */ |
| 787 | int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, |
| 788 | uint64_t timeout_ns, |
| 789 | bool *buffer_busy); |
| 790 | |
| 791 | |
| 792 | /* |
| 793 | * Special GPU Resources |
| 794 | * |
| 795 | */ |
| 796 | |
| 797 | |
| 798 | |
| 799 | /** |
| 800 | * Query information about GDS |
| 801 | * |
| 802 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 803 | * \param gds_info - \c [out] Pointer to structure to get GDS information |
| 804 | * |
| 805 | * \return 0 on success\n |
| 806 | * >0 - AMD specific error code\n |
| 807 | * <0 - Negative POSIX Error code |
| 808 | * |
| 809 | */ |
| 810 | int amdgpu_gpu_resource_query_gds_info(amdgpu_device_handle dev, |
| 811 | struct amdgpu_gds_resource_info * |
| 812 | gds_info); |
| 813 | |
| 814 | |
| 815 | /** |
| 816 | * Allocate GDS partitions |
| 817 | * |
| 818 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 819 | * \param gds_size - \c [in] Size of gds allocation. Must be aligned |
| 820 | * accordingly. |
| 821 | * \param alloc_info - \c [out] Pointer to structure to receive information |
| 822 | * about allocation |
| 823 | * |
| 824 | * \return 0 on success\n |
| 825 | * >0 - AMD specific error code\n |
| 826 | * <0 - Negative POSIX Error code |
| 827 | * |
| 828 | * |
| 829 | */ |
| 830 | int amdgpu_gpu_resource_gds_alloc(amdgpu_device_handle dev, |
| 831 | uint32_t gds_size, |
| 832 | struct amdgpu_gds_alloc_info *alloc_info); |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | /** |
| 838 | * Release GDS resource. When GDS and associated resources not needed any |
| 839 | * more UMD should free them |
| 840 | * |
| 841 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 842 | * \param handle - \c [in] Handle assigned to GDS allocation |
| 843 | * |
| 844 | * \return 0 on success\n |
| 845 | * >0 - AMD specific error code\n |
| 846 | * <0 - Negative POSIX Error code |
| 847 | * |
| 848 | */ |
| 849 | int amdgpu_gpu_resource_gds_free(amdgpu_bo_handle handle); |
| 850 | |
| 851 | |
| 852 | |
| 853 | /* |
| 854 | * GPU Execution context |
| 855 | * |
| 856 | */ |
| 857 | |
| 858 | /** |
| 859 | * Create GPU execution Context |
| 860 | * |
| 861 | * For the purpose of GPU Scheduler and GPU Robustness extensions it is |
| 862 | * necessary to have information/identify rendering/compute contexts. |
| 863 | * It also may be needed to associate some specific requirements with such |
| 864 | * contexts. Kernel driver will guarantee that submission from the same |
| 865 | * context will always be executed in order (first come, first serve). |
| 866 | * |
| 867 | * |
| 868 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 869 | * \param context - \c [out] GPU Context handle |
| 870 | * |
| 871 | * \return 0 on success\n |
| 872 | * >0 - AMD specific error code\n |
| 873 | * <0 - Negative POSIX Error code |
| 874 | * |
| 875 | * \sa amdgpu_cs_ctx_free() |
| 876 | * |
| 877 | */ |
| 878 | int amdgpu_cs_ctx_create(amdgpu_device_handle dev, |
| 879 | amdgpu_context_handle *context); |
| 880 | |
| 881 | /** |
| 882 | * |
| 883 | * Destroy GPU execution context when not needed any more |
| 884 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 885 | * \param context - \c [in] GPU Context handle |
| 886 | * |
| 887 | * \return 0 on success\n |
| 888 | * >0 - AMD specific error code\n |
| 889 | * <0 - Negative POSIX Error code |
| 890 | * |
| 891 | * \sa amdgpu_cs_ctx_create() |
| 892 | * |
| 893 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 894 | int amdgpu_cs_ctx_free(amdgpu_context_handle context); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 895 | |
| 896 | /** |
| 897 | * Query reset state for the specific GPU Context |
| 898 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 899 | * \param context - \c [in] GPU Context handle |
| 900 | * \param state - \c [out] Reset state status |
| 901 | * |
| 902 | * \return 0 on success\n |
| 903 | * >0 - AMD specific error code\n |
| 904 | * <0 - Negative POSIX Error code |
| 905 | * |
| 906 | * \sa amdgpu_cs_ctx_create() |
| 907 | * |
| 908 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 909 | int amdgpu_cs_query_reset_state(amdgpu_context_handle context, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 910 | enum amdgpu_cs_ctx_reset_state *state); |
| 911 | |
| 912 | |
| 913 | /* |
| 914 | * Command Buffers Management |
| 915 | * |
| 916 | */ |
| 917 | |
| 918 | |
| 919 | /** |
| 920 | * Allocate memory to be filled with PM4 packets and be served as the first |
| 921 | * entry point of execution (a.k.a. Indirect Buffer) |
| 922 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 923 | * \param context - \c [in] GPU Context which will use IB |
| 924 | * \param ib_size - \c [in] Size of allocation |
| 925 | * \param output - \c [out] Pointer to structure to get information about |
| 926 | * allocated IB |
| 927 | * |
| 928 | * \return 0 on success\n |
| 929 | * >0 - AMD specific error code\n |
| 930 | * <0 - Negative POSIX Error code |
| 931 | * |
| 932 | * \sa amdgpu_cs_free_ib() |
| 933 | * |
| 934 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 935 | int amdgpu_cs_alloc_ib(amdgpu_context_handle context, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 936 | enum amdgpu_cs_ib_size ib_size, |
| 937 | struct amdgpu_cs_ib_alloc_result *output); |
| 938 | |
| 939 | /** |
| 940 | * If UMD has allocates IBs which doesn’t need any more than those IBs must |
| 941 | * be explicitly freed |
| 942 | * |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 943 | * \param handle - \c [in] IB handle |
| 944 | * |
| 945 | * \return 0 on success\n |
| 946 | * >0 - AMD specific error code\n |
| 947 | * <0 - Negative POSIX Error code |
| 948 | * |
| 949 | * \note Libdrm_amdgpu will guarantee that it will correctly detect when it |
| 950 | * is safe to return IB to free pool |
| 951 | * |
| 952 | * \sa amdgpu_cs_alloc_ib() |
| 953 | * |
| 954 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 955 | int amdgpu_cs_free_ib(amdgpu_ib_handle handle); |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 956 | |
| 957 | /** |
| 958 | * Send request to submit command buffers to hardware. |
| 959 | * |
| 960 | * Kernel driver could use GPU Scheduler to make decision when physically |
| 961 | * sent this request to the hardware. Accordingly this request could be put |
| 962 | * in queue and sent for execution later. The only guarantee is that request |
| 963 | * from the same GPU context to the same ip:ip_instance:ring will be executed in |
| 964 | * order. |
| 965 | * |
| 966 | * |
| 967 | * \param dev - \c [in] Device handle. |
| 968 | * See #amdgpu_device_initialize() |
| 969 | * \param context - \c [in] GPU Context |
| 970 | * \param flags - \c [in] Global submission flags |
| 971 | * \param ibs_request - \c [in] Pointer to submission requests. |
| 972 | * We could submit to the several |
| 973 | * engines/rings simulteniously as |
| 974 | * 'atomic' operation |
| 975 | * \param number_of_requests - \c [in] Number of submission requests |
| 976 | * \param fences - \c [out] Pointer to array of data to get |
| 977 | * fences to identify submission |
| 978 | * requests. Timestamps are valid |
| 979 | * in this GPU context and could be used |
| 980 | * to identify/detect completion of |
| 981 | * submission request |
| 982 | * |
| 983 | * \return 0 on success\n |
| 984 | * >0 - AMD specific error code\n |
| 985 | * <0 - Negative POSIX Error code |
| 986 | * |
| 987 | * \note It is assumed that by default IB will be returned to free pool |
| 988 | * automatically by libdrm_amdgpu when submission will completed. |
| 989 | * It is possible for UMD to make decision to re-use the same IB in |
| 990 | * this case it should be explicitly freed.\n |
| 991 | * Accordingly, by default, after submission UMD should not touch passed |
| 992 | * IBs. If UMD needs to re-use IB then the special flag AMDGPU_CS_REUSE_IB |
| 993 | * must be passed. |
| 994 | * |
| 995 | * \note It is required to pass correct resource list with buffer handles |
| 996 | * which will be accessible by command buffers from submission |
| 997 | * This will allow kernel driver to correctly implement "paging". |
| 998 | * Failure to do so will have unpredictable results. |
| 999 | * |
| 1000 | * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), |
| 1001 | * amdgpu_cs_query_fence_status() |
| 1002 | * |
| 1003 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 1004 | int amdgpu_cs_submit(amdgpu_context_handle context, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 1005 | uint64_t flags, |
| 1006 | struct amdgpu_cs_request *ibs_request, |
| 1007 | uint32_t number_of_requests, |
| 1008 | uint64_t *fences); |
| 1009 | |
| 1010 | /** |
| 1011 | * Query status of Command Buffer Submission |
| 1012 | * |
| 1013 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1014 | * \param fence - \c [in] Structure describing fence to query |
| 1015 | * \param expired - \c [out] If fence expired or not.\n |
| 1016 | * 0 – if fence is not expired\n |
| 1017 | * !0 - otherwise |
| 1018 | * |
| 1019 | * \return 0 on success\n |
| 1020 | * >0 - AMD specific error code\n |
| 1021 | * <0 - Negative POSIX Error code |
| 1022 | * |
| 1023 | * \note If UMD wants only to check operation status and returned immediately |
| 1024 | * then timeout value as 0 must be passed. In this case success will be |
| 1025 | * returned in the case if submission was completed or timeout error |
| 1026 | * code. |
| 1027 | * |
| 1028 | * \sa amdgpu_cs_submit() |
| 1029 | */ |
Christian König | 9c2afff | 2015-04-22 12:21:13 +0200 | [diff] [blame^] | 1030 | int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 1031 | uint32_t *expired); |
| 1032 | |
| 1033 | |
| 1034 | /* |
| 1035 | * Query / Info API |
| 1036 | * |
| 1037 | */ |
| 1038 | |
| 1039 | |
| 1040 | /** |
| 1041 | * Query allocation size alignments |
| 1042 | * |
| 1043 | * UMD should query information about GPU VM MC size alignments requirements |
| 1044 | * to be able correctly choose required allocation size and implement |
| 1045 | * internal optimization if needed. |
| 1046 | * |
| 1047 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1048 | * \param info - \c [out] Pointer to structure to get size alignment |
| 1049 | * requirements |
| 1050 | * |
| 1051 | * \return 0 on success\n |
| 1052 | * >0 - AMD specific error code\n |
| 1053 | * <0 - Negative POSIX Error code |
| 1054 | * |
| 1055 | */ |
| 1056 | int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, |
| 1057 | struct amdgpu_buffer_size_alignments |
| 1058 | *info); |
| 1059 | |
| 1060 | |
| 1061 | |
| 1062 | /** |
| 1063 | * Query firmware versions |
| 1064 | * |
| 1065 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1066 | * \param fw_type - \c [in] AMDGPU_INFO_FW_* |
| 1067 | * \param ip_instance - \c [in] Index of the IP block of the same type. |
| 1068 | * \param index - \c [in] Index of the engine. (for SDMA and MEC) |
| 1069 | * \param version - \c [out] Pointer to to the "version" return value |
| 1070 | * \param feature - \c [out] Pointer to to the "feature" return value |
| 1071 | * |
| 1072 | * \return 0 on success\n |
| 1073 | * >0 - AMD specific error code\n |
| 1074 | * <0 - Negative POSIX Error code |
| 1075 | * |
| 1076 | */ |
| 1077 | int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, |
| 1078 | unsigned ip_instance, unsigned index, |
| 1079 | uint32_t *version, uint32_t *feature); |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | /** |
| 1084 | * Query the number of HW IP instances of a certain type. |
| 1085 | * |
| 1086 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1087 | * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* |
| 1088 | * \param count - \c [out] Pointer to structure to get information |
| 1089 | * |
| 1090 | * \return 0 on success\n |
| 1091 | * >0 - AMD specific error code\n |
| 1092 | * <0 - Negative POSIX Error code |
| 1093 | */ |
| 1094 | int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, |
| 1095 | uint32_t *count); |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | /** |
| 1100 | * Query engine information |
| 1101 | * |
| 1102 | * This query allows UMD to query information different engines and their |
| 1103 | * capabilities. |
| 1104 | * |
| 1105 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1106 | * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* |
| 1107 | * \param ip_instance - \c [in] Index of the IP block of the same type. |
| 1108 | * \param info - \c [out] Pointer to structure to get information |
| 1109 | * |
| 1110 | * \return 0 on success\n |
| 1111 | * >0 - AMD specific error code\n |
| 1112 | * <0 - Negative POSIX Error code |
| 1113 | */ |
| 1114 | int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, |
| 1115 | unsigned ip_instance, |
| 1116 | struct drm_amdgpu_info_hw_ip *info); |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | /** |
| 1122 | * Query heap information |
| 1123 | * |
| 1124 | * This query allows UMD to query potentially available memory resources and |
| 1125 | * adjust their logic if necessary. |
| 1126 | * |
| 1127 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1128 | * \param heap - \c [in] Heap type |
| 1129 | * \param info - \c [in] Pointer to structure to get needed information |
| 1130 | * |
| 1131 | * \return 0 on success\n |
| 1132 | * >0 - AMD specific error code\n |
| 1133 | * <0 - Negative POSIX Error code |
| 1134 | * |
| 1135 | */ |
| 1136 | int amdgpu_query_heap_info(amdgpu_device_handle dev, |
| 1137 | uint32_t heap, |
| 1138 | uint32_t flags, |
| 1139 | struct amdgpu_heap_info *info); |
| 1140 | |
| 1141 | |
| 1142 | |
| 1143 | /** |
| 1144 | * Get the CRTC ID from the mode object ID |
| 1145 | * |
| 1146 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1147 | * \param id - \c [in] Mode object ID |
| 1148 | * \param result - \c [in] Pointer to the CRTC ID |
| 1149 | * |
| 1150 | * \return 0 on success\n |
| 1151 | * >0 - AMD specific error code\n |
| 1152 | * <0 - Negative POSIX Error code |
| 1153 | * |
| 1154 | */ |
| 1155 | int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, |
| 1156 | int32_t *result); |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | /** |
| 1161 | * Query GPU H/w Info |
| 1162 | * |
| 1163 | * Query hardware specific information |
| 1164 | * |
| 1165 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1166 | * \param heap - \c [in] Heap type |
| 1167 | * \param info - \c [in] Pointer to structure to get needed information |
| 1168 | * |
| 1169 | * \return 0 on success\n |
| 1170 | * >0 - AMD specific error code\n |
| 1171 | * <0 - Negative POSIX Error code |
| 1172 | * |
| 1173 | */ |
| 1174 | int amdgpu_query_gpu_info(amdgpu_device_handle dev, |
| 1175 | struct amdgpu_gpu_info *info); |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | /** |
| 1180 | * Query hardware or driver information. |
| 1181 | * |
| 1182 | * The return size is query-specific and depends on the "info_id" parameter. |
| 1183 | * No more than "size" bytes is returned. |
| 1184 | * |
| 1185 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() |
| 1186 | * \param info_id - \c [in] AMDGPU_INFO_* |
| 1187 | * \param size - \c [in] Size of the returned value. |
| 1188 | * \param value - \c [out] Pointer to the return value. |
| 1189 | * |
| 1190 | * \return 0 on success\n |
| 1191 | * >0 - AMD specific error code\n |
| 1192 | * <0 - Negative POSIX error code |
| 1193 | * |
| 1194 | */ |
| 1195 | int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, |
| 1196 | unsigned size, void *value); |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | /** |
| 1201 | * Read a set of consecutive memory-mapped registers. |
| 1202 | * Not all registers are allowed to be read by userspace. |
| 1203 | * |
| 1204 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( |
| 1205 | * \param dword_offset - \c [in] Register offset in dwords |
| 1206 | * \param count - \c [in] The number of registers to read starting |
| 1207 | * from the offset |
| 1208 | * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other |
| 1209 | * uses. Set it to 0xffffffff if unsure. |
| 1210 | * \param flags - \c [in] Flags with additional information. |
| 1211 | * \param values - \c [out] The pointer to return values. |
| 1212 | * |
| 1213 | * \return 0 on success\n |
| 1214 | * >0 - AMD specific error code\n |
| 1215 | * <0 - Negative POSIX error code |
| 1216 | * |
| 1217 | */ |
| 1218 | int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, |
| 1219 | unsigned count, uint32_t instance, uint32_t flags, |
| 1220 | uint32_t *values); |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | /** |
| 1225 | * Request GPU access to user allocated memory e.g. via "malloc" |
| 1226 | * |
| 1227 | * \param dev - [in] Device handle. See #amdgpu_device_initialize() |
| 1228 | * \param cpu - [in] CPU address of user allocated memory which we |
| 1229 | * want to map to GPU address space (make GPU accessible) |
| 1230 | * (This address must be correctly aligned). |
| 1231 | * \param size - [in] Size of allocation (must be correctly aligned) |
| 1232 | * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource |
| 1233 | * on submission and be used in other operations.(e.g. for VA submission) |
| 1234 | * ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. ) |
| 1235 | * |
| 1236 | * |
| 1237 | * \return 0 on success |
| 1238 | * >0 - AMD specific error code |
| 1239 | * <0 - Negative POSIX Error code |
| 1240 | * |
| 1241 | * |
| 1242 | * \note |
| 1243 | * This call doesn't guarantee that such memory will be persistently |
| 1244 | * "locked" / make non-pageable. The purpose of this call is to provide |
| 1245 | * opportunity for GPU get access to this resource during submission. |
| 1246 | * |
| 1247 | * The maximum amount of memory which could be mapped in this call depends |
| 1248 | * if overcommit is disabled or not. If overcommit is disabled than the max. |
| 1249 | * amount of memory to be pinned will be limited by left "free" size in total |
| 1250 | * amount of memory which could be locked simultaneously ("GART" size). |
| 1251 | * |
| 1252 | * Supported (theoretical) max. size of mapping is restricted only by |
| 1253 | * "GART" size. |
| 1254 | * |
| 1255 | * It is responsibility of caller to correctly specify access rights |
| 1256 | * on VA assignment. |
| 1257 | */ |
| 1258 | int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, |
| 1259 | void *cpu, |
| 1260 | uint64_t size, |
| 1261 | struct amdgpu_bo_alloc_result *info); |
| 1262 | |
| 1263 | |
| 1264 | #endif /* #ifdef _AMDGPU_H_ */ |