commit 0efcc2be1f988603f8239310e88da2a9623347c8
author Felicia Lim <flim@google.com> Tue Nov 06 12:35:39 2018 -0800
committer Ray Essick <essick@google.com> Wed Nov 14 21:29:18 2018 +0000
tree 13c7c0f8e05918858ebaa13510d80f8369884b57
parent cf168b63a5c4766bcb663d9ddb16dadbc080e103

Upgrade Opus to v1.3

Bug: 63932386
Test: - verified builds for arm*/x86*
      - checked functionality using an emulator and stagefright

Change-Id: I10c4b267be1c846d8992e3c5f6d2576c2cb258a9
Signed-off-by: Felicia Lim <flim@google.com>

Android.bp

diff --git a/Android.bp b/Android.bp
index 82f6a7c..fc6ddd4 100644
--- a/Android.bp
+++ b/Android.bp
@@ -140,12 +140,15 @@
         "silk/fixed/schur_FIX.c",
 
         // OPUS_SOURCES
+        "src/mapping_matrix.c",
         "src/opus.c",
         "src/opus_decoder.c",
         "src/opus_encoder.c",
         "src/opus_multistream.c",
         "src/opus_multistream_encoder.c",
         "src/opus_multistream_decoder.c",
+        "src/opus_projection_encoder.c",
+        "src/opus_projection_decoder.c",
         "src/repacketizer.c",
 
         // OPUS_SOURCES_FLOAT
@@ -167,6 +170,7 @@
         "-DUSE_ALLOCA",
         "-DHAVE_LRINT",
         "-DHAVE_LRINTF",
+        "-DENABLE_HARDENING",
         "-O2",
         "-fno-math-errno",
         "-Wall",
@@ -261,19 +265,19 @@
             sse4_1: {
                 srcs: [
                     // CELT_SOURCES_SSE4_1
-                    "celt/x86/celt_lpc_sse.c",
+                    "celt/x86/celt_lpc_sse4_1.c",
                     "celt/x86/pitch_sse4_1.c",
 
                     // SILK_SOURCES_SSE4_1
-                    "silk/x86/NSQ_sse.c",
-                    "silk/x86/NSQ_del_dec_sse.c",
+                    "silk/x86/NSQ_sse4_1.c",
+                    "silk/x86/NSQ_del_dec_sse4_1.c",
                     "silk/x86/x86_silk_map.c",
-                    "silk/x86/VAD_sse.c",
-                    "silk/x86/VQ_WMat_EC_sse.c",
+                    "silk/x86/VAD_sse4_1.c",
+                    "silk/x86/VQ_WMat_EC_sse4_1.c",
 
                     // SILK_SOURCES_FIXED_SSE4_1
-                    "silk/fixed/x86/vector_ops_FIX_sse.c",
-                    "silk/fixed/x86/burg_modified_FIX_sse.c",
+                    "silk/fixed/x86/vector_ops_FIX_sse4_1.c",
+                    "silk/fixed/x86/burg_modified_FIX_sse4_1.c",
                 ],
 
                 cflags: [
@@ -293,6 +297,7 @@
 
                     // CELT_SOURCES_SSE2
                     "celt/x86/pitch_sse2.c",
+                    "celt/x86/vq_sse2.c",
                 ],
 
                 cflags: [
@@ -306,19 +311,19 @@
             sse4_1: {
                 srcs: [
                     // CELT_SOURCES_SSE4_1
-                    "celt/x86/celt_lpc_sse.c",
+                    "celt/x86/celt_lpc_sse4_1.c",
                     "celt/x86/pitch_sse4_1.c",
 
                     // SILK_SOURCES_SSE4_1
-                    "silk/x86/NSQ_sse.c",
-                    "silk/x86/NSQ_del_dec_sse.c",
+                    "silk/x86/NSQ_sse4_1.c",
+                    "silk/x86/NSQ_del_dec_sse4_1.c",
                     "silk/x86/x86_silk_map.c",
-                    "silk/x86/VAD_sse.c",
-                    "silk/x86/VQ_WMat_EC_sse.c",
+                    "silk/x86/VAD_sse4_1.c",
+                    "silk/x86/VQ_WMat_EC_sse4_1.c",
 
                     // SILK_SOURCES_FIXED_SSE4_1
-                    "silk/fixed/x86/vector_ops_FIX_sse.c",
-                    "silk/fixed/x86/burg_modified_FIX_sse.c",
+                    "silk/fixed/x86/vector_ops_FIX_sse4_1.c",
+                    "silk/fixed/x86/burg_modified_FIX_sse4_1.c",
                 ],
 
                 cflags: [