Use two opcode tables g_arm_opcodes and g_thumb_opcodes, instead of lumping arm and thumb opcodes together.
git-svn-id: https://llvm.org/svn/llvm-project/llvdb/trunk@124156 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
index 67f969b..8f84996 100644
--- a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
+++ b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
@@ -191,19 +191,24 @@
static ARMOpcode g_arm_opcodes[] =
{
- { 0x0000fe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, EmulateARMPushEncoding,
- "push<c> <registers>" },
- { 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, EmulateARMPushEncoding,
- "push<c>.w <registers> ; <registers> contains more than one register" },
- { 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, EmulateARMPushEncoding,
- "push<c>.w <registers> ; <registers> contains one register, <Rt>" },
{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, EmulateARMPushEncoding,
"push<c> <registers> ; <registers> contains more than one register" },
{ 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, EmulateARMPushEncoding,
"push<c> <registers> ; <registers> contains one register, <Rt>" }
};
+static ARMOpcode g_thumb_opcodes[] =
+{
+ { 0x0000fe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, EmulateARMPushEncoding,
+ "push<c> <registers>" },
+ { 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, EmulateARMPushEncoding,
+ "push<c>.w <registers> ; <registers> contains more than one register" },
+ { 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, EmulateARMPushEncoding,
+ "push<c>.w <registers> ; <registers> contains one register, <Rt>" }
+};
+
static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
+static const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode);
bool
EmulateInstructionARM::ReadInstruction ()