Add Encoding T2 & T3 entries of emulate_sub_sp_imm to the g_thumb_opcodes table.
Update emulate_sub_sp_imm to handle Encoding T2 & T3.
git-svn-id: https://llvm.org/svn/llvm-project/llvdb/trunk@124248 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/source/Plugins/Process/Utility/ARMUtils.h b/source/Plugins/Process/Utility/ARMUtils.h
index e0def3f..0762298 100644
--- a/source/Plugins/Process/Utility/ARMUtils.h
+++ b/source/Plugins/Process/Utility/ARMUtils.h
@@ -61,17 +61,63 @@
return bits(val, msbit, msbit);
}
-static inline uint32_t ARMExpandImm(uint32_t imm12)
+static uint32_t ror(uint32_t val, uint32_t N, uint32_t shift)
{
- uint32_t imm = bits(imm12, 7, 0); // immediate value
- uint32_t rot = 2 * bits(imm12, 11, 8); // rotate amount
+ uint32_t m = shift % N;
+ return (val >> m) | (val << (N - m));
+}
+
+static inline uint32_t ARMExpandImm(uint32_t val)
+{
+ uint32_t imm = bits(val, 7, 0); // immediate value
+ uint32_t rot = 2 * bits(val, 11, 8); // rotate amount
return (imm >> rot) | (imm << (32 - rot));
}
-// Convenience function for ARMExpandImm(imm12).
-static inline uint32_t ARMExpand(uint32_t val)
+static inline uint32_t ThumbExpandImm(uint32_t val)
{
- return ARMExpandImm(bits(val, 11, 0));
+ uint32_t imm32 = 0;
+ const uint32_t i = bit(val, 26);
+ const uint32_t imm3 = bits(val, 14, 12);
+ const uint32_t abcdefgh = bits(val, 7, 0);
+ const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh;
+
+ if (bits(imm12, 10, 11) == 0)
+ {
+ switch (bits(imm12, 8, 9)) {
+ case 0:
+ imm32 = abcdefgh;
+ break;
+
+ case 1:
+ imm32 = abcdefgh << 16 | abcdefgh;
+ break;
+
+ case 2:
+ imm32 = abcdefgh << 24 | abcdefgh << 8;
+ break;
+
+ case 3:
+ imm32 = abcdefgh << 24 | abcdefgh << 16 | abcdefgh << 8 | abcdefgh;
+ break;
+ }
+ }
+ else
+ {
+ const uint32_t unrotated_value = 0x80 | bits(imm12, 0, 6);
+ imm32 = ror(unrotated_value, 32, bits(imm12, 7, 11));
+ }
+ return imm32;
+}
+
+// imm32 = ZeroExtend(i:imm3:imm8, 32)
+static inline uint32_t ThumbImm12(uint32_t val)
+{
+ const uint32_t i = bit(val, 26);
+ const uint32_t imm3 = bits(val, 14, 12);
+ const uint32_t imm8 = bits(val, 7, 0);
+ const uint32_t imm12 = i << 11 | imm3 << 8 | imm8;
+ return imm12;
}
// This function performs the check for the register numbers 13 and 15 that are
diff --git a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
index 7c480ec..99edee3 100644
--- a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
+++ b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
@@ -28,7 +28,7 @@
#define ARMv6K (1u << 6)
#define ARMv6T2 (1u << 7)
#define ARMv7 (1u << 8)
-#define ARMv8 (1u << 8)
+#define ARMv8 (1u << 9)
#define ARMvAll (0xffffffffu)
typedef enum
@@ -225,8 +225,14 @@
return false;
uint32_t imm32;
switch (encoding) {
+ case eEncodingT2:
+ imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
+ break;
+ case eEncodingT3:
+ imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
+ break;
case eEncodingA1:
- imm32 = ARMExpand(opcode); // imm32 = ARMExpandImm(imm12)
+ imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
break;
default:
return false;
@@ -327,11 +333,11 @@
// adjust the stack pointer
{ 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, emulate_sub_sp_imm,
- "sub sp, sp, #n"},
+ "sub sp, sp, #<const>"},
// if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
{ 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, emulate_str_rt_sp,
- "str Rt, [sp, #-n]!" }
+ "str Rt, [sp, #-<imm12>]!" }
};
static ARMOpcode g_thumb_opcodes[] =
@@ -341,7 +347,14 @@
{ 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push,
"push.w <registers> ; <registers> contains more than one register" },
{ 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_push,
- "push.w <registers> ; <registers> contains one register, <Rt>" }
+ "push.w <registers> ; <registers> contains one register, <Rt>" },
+
+ // adjust the stack pointer
+ { 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_sub_sp_imm,
+ "sub{s}.w sp, sp, #<const>"},
+ // adjust the stack pointer
+ { 0xfbff8f00, 0xf2ad0d00, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_sub_sp_imm,
+ "subw sp, sp, #<imm12>"}
};
static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);