Got the EmulateInstruction CFI code a lot closer to producing CFI data.
Switch the EmulateInstruction to use the standard RegisterInfo structure
that is defined in the lldb private types intead of passing the reg kind and
reg num everywhere. EmulateInstruction subclasses also need to provide
RegisterInfo structs given a reg kind and reg num. This eliminates the need
for the GetRegisterName() virtual function and allows more complete information
to be passed around in the read/write register callbacks. Subclasses should
always provide RegiterInfo structs with the generic register info filled in as
well as at least one kind of register number in the RegisterInfo.kinds[] array.
git-svn-id: https://llvm.org/svn/llvm-project/llvdb/trunk@130256 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/lldb/Core/EmulateInstruction.h b/include/lldb/Core/EmulateInstruction.h
index a0ecdc9..a17b3a5 100644
--- a/include/lldb/Core/EmulateInstruction.h
+++ b/include/lldb/Core/EmulateInstruction.h
@@ -12,6 +12,7 @@
#include <string>
+#include "lldb/lldb-private.h"
#include "lldb/lldb-public.h"
#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/PluginInterface.h"
@@ -145,11 +146,7 @@
// Used when random bits are written to memory
eContextWriteMemoryRandomBits,
- eContextMultiplication,
-
- eContextAddition,
-
- eContextSubtraction,
+ eContextArithmetic,
eContextAdvancePC,
@@ -167,26 +164,12 @@
eInfoTypeImmediate,
eInfoTypeImmediateSigned,
eInfoTypeAddress,
- eInfoTypeModeAndImmediate,
- eInfoTypeModeAndImmediateSigned,
- eInfoTypeMode,
+ eInfoTypeISAAndImmediate,
+ eInfoTypeISAAndImmediateSigned,
+ eInfoTypeISA,
eInfoTypeNoArgs
} InfoType;
-
- struct Register
- {
- uint32_t kind;
- uint32_t num;
-
- void
- SetRegister (uint32_t reg_kind, uint32_t reg_num)
- {
- kind = reg_kind;
- num = reg_num;
- }
- };
-
struct Context
{
ContextType type;
@@ -195,64 +178,63 @@
{
struct RegisterPlusOffset
{
- Register reg; // base register
+ RegisterInfo reg; // base register
int64_t signed_offset; // signed offset added to base register
} RegisterPlusOffset;
struct RegisterPlusIndirectOffset
{
- Register base_reg; // base register number
- Register offset_reg; // offset register kind
+ RegisterInfo base_reg; // base register number
+ RegisterInfo offset_reg; // offset register kind
} RegisterPlusIndirectOffset;
struct RegisterToRegisterPlusOffset
{
- Register data_reg; // source/target register for data
- Register base_reg; // base register for address calculation
- int64_t offset; // offset for address calculation
+ RegisterInfo data_reg; // source/target register for data
+ RegisterInfo base_reg; // base register for address calculation
+ int64_t offset; // offset for address calculation
} RegisterToRegisterPlusOffset;
struct RegisterToRegisterPlusIndirectOffset
{
- Register base_reg; // base register for address calculation
- Register offset_reg; // offset register for address calculation
- Register data_reg; // source/target register for data
+ RegisterInfo base_reg; // base register for address calculation
+ RegisterInfo offset_reg; // offset register for address calculation
+ RegisterInfo data_reg; // source/target register for data
} RegisterToRegisterPlusIndirectOffset;
struct RegisterRegisterOperands
{
- Register operand1; // register containing first operand for binary op
- Register operand2; // register containing second operand for binary op
+ RegisterInfo operand1; // register containing first operand for binary op
+ RegisterInfo operand2; // register containing second operand for binary op
} RegisterRegisterOperands;
- int64_t signed_offset; // signed offset by which to adjust self (for registers only)
+ int64_t signed_offset; // signed offset by which to adjust self (for registers only)
- Register reg; // plain register
+ RegisterInfo reg; // plain register
- uint64_t immediate; // immediate value
+ uint64_t unsigned_immediate;// unsigned immediate value
+ int64_t signed_immediate; // signed immediate value
- int64_t signed_immediate; // signed immediate value
+ lldb::addr_t address; // direct address
- lldb::addr_t address; // direct address
-
- struct ModeAndImmediate
+ struct ISAAndImmediate
{
- uint32_t mode; // eModeARM or eModeThumb
- uint32_t data_value; // immdiate data
- } ModeAndImmediate;
+ uint32_t isa;
+ uint32_t unsigned_data32; // immdiate data
+ } ISAAndImmediate;
- struct ModeAndImmediateSigned
+ struct ISAAndImmediateSigned
{
- uint32_t mode; // eModeARM or eModeThumb
- int32_t signed_data_value; // signed immdiate data
- } ModeAndImmediateSigned;
+ uint32_t isa;
+ int32_t signed_data32; // signed immdiate data
+ } ISAAndImmediateSigned;
- uint32_t mode; // eModeARM or eModeThumb
+ uint32_t isa;
} info;
void
- SetRegisterPlusOffset (Register base_reg,
+ SetRegisterPlusOffset (RegisterInfo base_reg,
int64_t signed_offset)
{
info_type = eInfoTypeRegisterPlusOffset;
@@ -261,8 +243,8 @@
}
void
- SetRegisterPlusIndirectOffset (Register base_reg,
- Register offset_reg)
+ SetRegisterPlusIndirectOffset (RegisterInfo base_reg,
+ RegisterInfo offset_reg)
{
info_type = eInfoTypeRegisterPlusIndirectOffset;
info.RegisterPlusIndirectOffset.base_reg = base_reg;
@@ -270,8 +252,8 @@
}
void
- SetRegisterToRegisterPlusOffset (Register data_reg,
- Register base_reg,
+ SetRegisterToRegisterPlusOffset (RegisterInfo data_reg,
+ RegisterInfo base_reg,
int64_t offset)
{
info_type = eInfoTypeRegisterToRegisterPlusOffset;
@@ -281,9 +263,9 @@
}
void
- SetRegisterToRegisterPlusIndirectOffset (Register base_reg,
- Register offset_reg,
- Register data_reg)
+ SetRegisterToRegisterPlusIndirectOffset (RegisterInfo base_reg,
+ RegisterInfo offset_reg,
+ RegisterInfo data_reg)
{
info_type = eInfoTypeRegisterToRegisterPlusIndirectOffset;
info.RegisterToRegisterPlusIndirectOffset.base_reg = base_reg;
@@ -292,8 +274,8 @@
}
void
- SetRegisterRegisterOperands (Register op1_reg,
- Register op2_reg)
+ SetRegisterRegisterOperands (RegisterInfo op1_reg,
+ RegisterInfo op2_reg)
{
info_type = eInfoTypeRegisterRegisterOperands;
info.RegisterRegisterOperands.operand1 = op1_reg;
@@ -308,7 +290,7 @@
}
void
- SetRegister (Register reg)
+ SetRegister (RegisterInfo reg)
{
info_type = eInfoTypeRegister;
info.reg = reg;
@@ -318,7 +300,7 @@
SetImmediate (uint64_t immediate)
{
info_type = eInfoTypeImmediate;
- info.immediate = immediate;
+ info.unsigned_immediate = immediate;
}
void
@@ -335,26 +317,26 @@
info.address = address;
}
void
- SetModeAndImmediate (uint32_t mode, uint32_t data_value)
+ SetISAAndImmediate (uint32_t isa, uint32_t data)
{
- info_type = eInfoTypeModeAndImmediate;
- info.ModeAndImmediate.mode = mode;
- info.ModeAndImmediate.data_value = data_value;
+ info_type = eInfoTypeISAAndImmediate;
+ info.ISAAndImmediate.isa = isa;
+ info.ISAAndImmediate.unsigned_data32 = data;
}
void
- SetModeAndImmediateSigned (uint32_t mode, int32_t signed_data_value)
+ SetISAAndImmediateSigned (uint32_t isa, int32_t data)
{
- info_type = eInfoTypeModeAndImmediateSigned;
- info.ModeAndImmediateSigned.mode = mode;
- info.ModeAndImmediateSigned.signed_data_value = signed_data_value;
+ info_type = eInfoTypeISAAndImmediateSigned;
+ info.ISAAndImmediateSigned.isa = isa;
+ info.ISAAndImmediateSigned.signed_data32 = data;
}
void
- SetMode (uint32_t mode)
+ SetISA (uint32_t isa)
{
- info_type = eInfoTypeMode;
- info.mode = mode;
+ info_type = eInfoTypeISA;
+ info.isa = isa;
}
void
@@ -362,12 +344,13 @@
{
info_type = eInfoTypeNoArgs;
}
-
+
+ void
+ Dump (FILE *fh,
+ EmulateInstruction *instruction) const;
+
};
- static void
- PrintContext (const char *context_type, const Context &context);
-
typedef size_t (*ReadMemory) (EmulateInstruction *instruction,
void *baton,
const Context &context,
@@ -384,15 +367,13 @@
typedef bool (*ReadRegister) (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value);
typedef bool (*WriteRegister) (EmulateInstruction *instruction,
void *baton,
const Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value);
EmulateInstruction (const ArchSpec &arch);
@@ -418,14 +399,18 @@
virtual bool
TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data) = 0;
- virtual const char *
- GetRegisterName (uint32_t reg_kind, uint32_t reg_num) = 0;
+ virtual bool
+ GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info) = 0;
+
//----------------------------------------------------------------------
// Optional overrides
//----------------------------------------------------------------------
virtual bool
SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target);
-
+
+ virtual bool
+ CreateFunctionEntryUnwind (UnwindPlan &unwind_plan);
+
static const char *
TranslateRegister (uint32_t reg_kind, uint32_t reg_num, std::string ®_name);
@@ -435,10 +420,20 @@
uint64_t fail_value,
bool *success_ptr);
+ uint64_t
+ ReadRegisterUnsigned (const RegisterInfo ®_info,
+ uint64_t fail_value,
+ bool *success_ptr);
+
bool
WriteRegisterUnsigned (const Context &context,
uint32_t reg_kind,
- uint32_t reg_num,
+ uint32_t reg_num,
+ uint64_t reg_value);
+
+ bool
+ WriteRegisterUnsigned (const Context &context,
+ const RegisterInfo ®_info,
uint64_t reg_value);
uint64_t
@@ -498,8 +493,7 @@
static bool
ReadRegisterFrame (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value);
@@ -507,8 +501,7 @@
WriteRegisterFrame (EmulateInstruction *instruction,
void *baton,
const Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value);
static size_t
@@ -530,8 +523,7 @@
static bool
ReadRegisterDefault (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value);
@@ -539,8 +531,7 @@
WriteRegisterDefault (EmulateInstruction *instruction,
void *baton,
const Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value);
void
@@ -563,7 +554,15 @@
void
SetWriteRegCallback (WriteRegister write_reg_callback);
+
+ static bool
+ GetBestRegisterKindAndNumber (const RegisterInfo ®_info,
+ uint32_t ®_kind,
+ uint32_t ®_num);
+ static uint32_t
+ GetInternalRegisterNumber (RegisterContext *reg_ctx,
+ const RegisterInfo ®_info);
protected:
ArchSpec m_arch;
@@ -574,6 +573,9 @@
WriteRegister m_write_reg_callback;
lldb::addr_t m_opcode_pc;
Opcode m_opcode;
+
+
+private:
//------------------------------------------------------------------
// For EmulateInstruction only
//------------------------------------------------------------------
diff --git a/include/lldb/Symbol/UnwindPlan.h b/include/lldb/Symbol/UnwindPlan.h
index 5ed11ad..43ee40d 100644
--- a/include/lldb/Symbol/UnwindPlan.h
+++ b/include/lldb/Symbol/UnwindPlan.h
@@ -59,7 +59,11 @@
isDWARFExpression // reg = eval(dwarf_expr)
};
- RegisterLocation() : m_type(unspecified), m_location() { }
+ RegisterLocation() :
+ m_type(unspecified),
+ m_location()
+ {
+ }
bool
operator == (const RegisterLocation& rhs) const;
@@ -259,6 +263,15 @@
int
GetRowCount () const;
+ void
+ Clear()
+ {
+ m_row_list.clear();
+ m_plan_valid_address_range.Clear();
+ m_register_kind = UINT32_MAX;
+ m_source_name.Clear();
+ }
+
private:
typedef std::vector<Row> collection;
diff --git a/lldb.xcodeproj/project.pbxproj b/lldb.xcodeproj/project.pbxproj
index 432f034..c602105 100644
--- a/lldb.xcodeproj/project.pbxproj
+++ b/lldb.xcodeproj/project.pbxproj
@@ -404,7 +404,7 @@
26DE20611161902700A093E2 /* SBBlock.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26DE20601161902600A093E2 /* SBBlock.cpp */; };
26DE20631161904200A093E2 /* SBLineEntry.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26DE20621161904200A093E2 /* SBLineEntry.cpp */; };
26DE20651161904E00A093E2 /* SBSymbol.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26DE20641161904E00A093E2 /* SBSymbol.cpp */; };
- 26ECA04313665FED008D1F18 /* ARM_DWARF_Registers.c in Sources */ = {isa = PBXBuildFile; fileRef = 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.c */; };
+ 26ECA04313665FED008D1F18 /* ARM_DWARF_Registers.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.cpp */; };
26F5C27710F3D9E4009D5894 /* Driver.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26F5C27310F3D9E4009D5894 /* Driver.cpp */; };
26F5C27810F3D9E4009D5894 /* IOChannel.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 26F5C27510F3D9E4009D5894 /* IOChannel.cpp */; };
26F5C32510F3DF23009D5894 /* libpython.dylib in Frameworks */ = {isa = PBXBuildFile; fileRef = 26F5C32410F3DF23009D5894 /* libpython.dylib */; };
@@ -1044,7 +1044,7 @@
26E3EEF811A994E800FBADB6 /* RegisterContextMacOSXFrameBackchain.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = RegisterContextMacOSXFrameBackchain.h; path = Utility/RegisterContextMacOSXFrameBackchain.h; sourceTree = "<group>"; };
26E6902E129C6BD500DDECD9 /* ClangExternalASTSourceCallbacks.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = ClangExternalASTSourceCallbacks.h; path = include/lldb/Symbol/ClangExternalASTSourceCallbacks.h; sourceTree = "<group>"; };
26E69030129C6BEF00DDECD9 /* ClangExternalASTSourceCallbacks.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = ClangExternalASTSourceCallbacks.cpp; path = source/Symbol/ClangExternalASTSourceCallbacks.cpp; sourceTree = "<group>"; };
- 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = ARM_DWARF_Registers.c; path = source/Utility/ARM_DWARF_Registers.c; sourceTree = "<group>"; };
+ 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = ARM_DWARF_Registers.cpp; path = source/Utility/ARM_DWARF_Registers.cpp; sourceTree = "<group>"; };
26F5C26A10F3D9A4009D5894 /* lldb */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = lldb; sourceTree = BUILT_PRODUCTS_DIR; };
26F5C27210F3D9E4009D5894 /* lldb-Info.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; name = "lldb-Info.plist"; path = "tools/driver/lldb-Info.plist"; sourceTree = "<group>"; };
26F5C27310F3D9E4009D5894 /* Driver.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Driver.cpp; path = tools/driver/Driver.cpp; sourceTree = "<group>"; };
@@ -1763,7 +1763,7 @@
4C2FAE2E135E3A70001EDE44 /* SharedCluster.h */,
261B5A5311C3F2AD00AABD0A /* SharingPtr.h */,
26F996A7119B79C300412154 /* ARM_DWARF_Registers.h */,
- 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.c */,
+ 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.cpp */,
26F996A8119B79C300412154 /* ARM_GCC_Registers.h */,
2660D9F611922A1300958FBD /* StringExtractor.cpp */,
2660D9F711922A1300958FBD /* StringExtractor.h */,
@@ -3234,7 +3234,7 @@
2692BA231366150100F9E14D /* ArchVolatileRegs-x86.cpp in Sources */,
263E949F13661AEA00E7D1CE /* UnwindAssembly-x86.cpp in Sources */,
264D8D5013661BD7003A368F /* UnwindAssembly.cpp in Sources */,
- 26ECA04313665FED008D1F18 /* ARM_DWARF_Registers.c in Sources */,
+ 26ECA04313665FED008D1F18 /* ARM_DWARF_Registers.cpp in Sources */,
);
runOnlyForDeploymentPostprocessing = 0;
};
diff --git a/source/Core/EmulateInstruction.cpp b/source/Core/EmulateInstruction.cpp
index d730a53..a6c7f82 100644
--- a/source/Core/EmulateInstruction.cpp
+++ b/source/Core/EmulateInstruction.cpp
@@ -16,13 +16,12 @@
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/StreamString.h"
#include "lldb/Host/Endian.h"
+#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Target/Process.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Target/Target.h"
#include "lldb/Target/Thread.h"
-#include "Plugins/Instruction/ARM/EmulateInstructionARM.h"
-
using namespace lldb;
using namespace lldb_private;
@@ -64,11 +63,23 @@
::memset (&m_opcode, 0, sizeof (m_opcode));
}
+
uint64_t
EmulateInstruction::ReadRegisterUnsigned (uint32_t reg_kind, uint32_t reg_num, uint64_t fail_value, bool *success_ptr)
{
+ RegisterInfo reg_info;
+ if (GetRegisterInfo(reg_kind, reg_num, reg_info))
+ return ReadRegisterUnsigned (reg_info, fail_value, success_ptr);
+ if (success_ptr)
+ *success_ptr = false;
+ return fail_value;
+}
+
+uint64_t
+EmulateInstruction::ReadRegisterUnsigned (const RegisterInfo ®_info, uint64_t fail_value, bool *success_ptr)
+{
uint64_t uval64 = 0;
- bool success = m_read_reg_callback (this, m_baton, reg_kind, reg_num, uval64);
+ bool success = m_read_reg_callback (this, m_baton, reg_info, uval64);
if (success_ptr)
*success_ptr = success;
if (!success)
@@ -79,7 +90,16 @@
bool
EmulateInstruction::WriteRegisterUnsigned (const Context &context, uint32_t reg_kind, uint32_t reg_num, uint64_t reg_value)
{
- return m_write_reg_callback (this, m_baton, context, reg_kind, reg_num, reg_value);
+ RegisterInfo reg_info;
+ if (GetRegisterInfo(reg_kind, reg_num, reg_info))
+ return WriteRegisterUnsigned (context, reg_info, reg_value);
+ return false;
+}
+
+bool
+EmulateInstruction::WriteRegisterUnsigned (const Context &context, const RegisterInfo ®_info, uint64_t reg_value)
+{
+ return m_write_reg_callback (this, m_baton, context, reg_info, reg_value);
}
uint64_t
@@ -235,28 +255,26 @@
bool
EmulateInstruction::ReadRegisterFrame (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value)
{
if (!baton)
return false;
StackFrame *frame = (StackFrame *) baton;
- RegisterContext *reg_context = frame->GetRegisterContext().get();
+ RegisterContext *reg_ctx = frame->GetRegisterContext().get();
Scalar value;
- uint32_t internal_reg_num = reg_context->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num);
+ const uint32_t internal_reg_num = GetInternalRegisterNumber (reg_ctx, reg_info);
- if (internal_reg_num == LLDB_INVALID_REGNUM)
- return false;
-
- if (reg_context->ReadRegisterValue (internal_reg_num, value))
+ if (internal_reg_num != LLDB_INVALID_REGNUM)
{
- reg_value = value.GetRawBits64 (0);
- return true;
+ if (reg_ctx->ReadRegisterValue (internal_reg_num, value))
+ {
+ reg_value = value.GetRawBits64 (0);
+ return true;
+ }
}
-
return false;
}
@@ -264,22 +282,19 @@
EmulateInstruction::WriteRegisterFrame (EmulateInstruction *instruction,
void *baton,
const Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value)
{
if (!baton)
return false;
StackFrame *frame = (StackFrame *) baton;
- RegisterContext *reg_context = frame->GetRegisterContext().get();
+ RegisterContext *reg_ctx = frame->GetRegisterContext().get();
Scalar value (reg_value);
-
- uint32_t internal_reg_num = reg_context->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num);
+ const uint32_t internal_reg_num = GetInternalRegisterNumber (reg_ctx, reg_info);
if (internal_reg_num != LLDB_INVALID_REGNUM)
- return reg_context->WriteRegisterValue (internal_reg_num, value);
- else
- return false;
+ return reg_ctx->WriteRegisterValue (internal_reg_num, value);
+ return false;
}
size_t
@@ -290,9 +305,8 @@
void *dst,
size_t length)
{
- PrintContext ("Read from memory", context);
- fprintf (stdout, " Read from Memory (address = %p, length = %d)\n",(void *) addr, (uint32_t) length);
-
+ fprintf (stdout, " Read from Memory (address = 0x%llx, length = %zu, context = ", addr, (uint32_t) length);
+ context.Dump (stdout, instruction);
*((uint64_t *) dst) = 0xdeadbeef;
return length;
}
@@ -305,23 +319,24 @@
const void *dst,
size_t length)
{
- PrintContext ("Write to memory", context);
- fprintf (stdout, " Write to Memory (address = %p, length = %d)\n", (void *) addr, (uint32_t) length);
+ fprintf (stdout, " Write to Memory (address = 0x%llx, length = %zu, context = ", addr, (uint32_t) length);
+ context.Dump (stdout, instruction);
return length;
}
bool
EmulateInstruction::ReadRegisterDefault (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value)
{
- std::string reg_name;
- TranslateRegister (reg_kind, reg_num, reg_name);
- fprintf (stdout, " Read Register (%s)\n", reg_name.c_str());
-
- reg_value = 24;
+ fprintf (stdout, " Read Register (%s)\n", reg_info.name);
+ uint32_t reg_kind, reg_num;
+ if (GetBestRegisterKindAndNumber (reg_info, reg_kind, reg_num))
+ reg_value = (uint64_t)reg_kind << 24 | reg_num;
+ else
+ reg_value = 0;
+
return true;
}
@@ -329,252 +344,191 @@
EmulateInstruction::WriteRegisterDefault (EmulateInstruction *instruction,
void *baton,
const Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value)
{
- PrintContext ("Write to register", context);
- std::string reg_name;
- TranslateRegister (reg_kind, reg_num, reg_name);
- fprintf (stdout, " Write to Register (%s), value = 0x%llx\n", reg_name.c_str(), reg_value);
+ fprintf (stdout, " Write to Register (name = %s, value = 0x%llx, context = ", reg_info.name, reg_value);
+ context.Dump (stdout, instruction);
return true;
}
void
-EmulateInstruction::PrintContext (const char *context_type, const Context &context)
+EmulateInstruction::Context::Dump (FILE *fh,
+ EmulateInstruction *instruction) const
{
- switch (context.type)
+ switch (type)
{
case eContextReadOpcode:
- fprintf (stdout, " %s context: Reading an Opcode\n", context_type);
+ fprintf (fh, "reading opcode");
break;
case eContextImmediate:
- fprintf (stdout, " %s context: Immediate\n", context_type);
+ fprintf (fh, "immediate");
break;
case eContextPushRegisterOnStack:
- fprintf (stdout, " %s context: Pushing a register onto the stack.\n", context_type);
+ fprintf (fh, "push register");
break;
case eContextPopRegisterOffStack:
- fprintf (stdout, " %s context: Popping a register off the stack.\n", context_type);
+ fprintf (fh, "pop register");
break;
case eContextAdjustStackPointer:
- fprintf (stdout, " %s context: Adjusting the stack pointer.\n", context_type);
+ fprintf (fh, "adjust sp");
break;
case eContextAdjustBaseRegister:
- fprintf (stdout, " %s context: Adjusting (writing value back to) a base register.\n", context_type);
+ fprintf (fh, "adjusting (writing value back to) a base register");
break;
case eContextRegisterPlusOffset:
- fprintf (stdout, " %s context: Register plus offset\n", context_type);
+ fprintf (fh, "register + offset");
break;
case eContextRegisterStore:
- fprintf (stdout, " %s context: Storing a register.\n", context_type);
+ fprintf (fh, "store register");
break;
case eContextRegisterLoad:
- fprintf (stdout, " %s context: Loading a register.\n", context_type);
+ fprintf (fh, "load register");
break;
case eContextRelativeBranchImmediate:
- fprintf (stdout, " %s context: Relative branch immediate\n", context_type);
+ fprintf (fh, "relative branch immediate");
break;
case eContextAbsoluteBranchRegister:
- fprintf (stdout, " %s context: Absolute branch register\n", context_type);
+ fprintf (fh, "absolute branch register");
break;
case eContextSupervisorCall:
- fprintf (stdout, " %s context: Performing a supervisor call.\n", context_type);
+ fprintf (fh, "supervisor call");
break;
case eContextTableBranchReadMemory:
- fprintf (stdout, " %s context: Table branch read memory\n", context_type);
+ fprintf (fh, "table branch read memory");
break;
case eContextWriteRegisterRandomBits:
- fprintf (stdout, " %s context: Write random bits to a register\n", context_type);
+ fprintf (fh, "write random bits to a register");
break;
case eContextWriteMemoryRandomBits:
- fprintf (stdout, " %s context: Write random bits to a memory address\n", context_type);
+ fprintf (fh, "write random bits to a memory address");
break;
- case eContextMultiplication:
- fprintf (stdout, " %s context: Performing a multiplication\n", context_type);
- break;
-
- case eContextAddition:
- fprintf (stdout, " %s context: Performing an addition\n", context_type);
+ case eContextArithmetic:
+ fprintf (fh, "arithmetic");
break;
case eContextReturnFromException:
- fprintf (stdout, " %s context: Returning from an exception\n", context_type);
+ fprintf (fh, "return from exception");
break;
default:
- fprintf (stdout, " %s context: Unrecognized context.\n", context_type);
+ fprintf (fh, "unrecognized context.");
break;
}
- switch (context.info_type)
+ switch (info_type)
{
- case eInfoTypeRegisterPlusOffset:
+ case eInfoTypeRegisterPlusOffset:
{
- std::string reg_name;
- TranslateRegister (context.info.RegisterPlusOffset.reg.kind,
- context.info.RegisterPlusOffset.reg.num,
- reg_name);
- fprintf (stdout, " Info type: Register plus offset (%s +/- %lld)\n", reg_name.c_str(),
- context.info.RegisterPlusOffset.signed_offset);
+ fprintf (fh,
+ " (reg_plus_offset = %s%+lld)\n",
+ info.RegisterPlusOffset.reg.name,
+ info.RegisterPlusOffset.signed_offset);
}
- break;
- case eInfoTypeRegisterPlusIndirectOffset:
+ break;
+
+ case eInfoTypeRegisterPlusIndirectOffset:
{
- std::string base_reg_name;
- std::string offset_reg_name;
- TranslateRegister (context.info.RegisterPlusIndirectOffset.base_reg.kind,
- context.info.RegisterPlusIndirectOffset.base_reg.num,
- base_reg_name);
- TranslateRegister (context.info.RegisterPlusIndirectOffset.offset_reg.kind,
- context.info.RegisterPlusIndirectOffset.offset_reg.num,
- offset_reg_name);
- fprintf (stdout, " Info type: Register plus indirect offset (%s +/- %s)\n",
- base_reg_name.c_str(),
- offset_reg_name.c_str());
+ fprintf (fh, " (reg_plus_reg = %s + %s)\n",
+ info.RegisterPlusIndirectOffset.base_reg.name,
+ info.RegisterPlusIndirectOffset.offset_reg.name);
}
- break;
- case eInfoTypeRegisterToRegisterPlusOffset:
+ break;
+
+ case eInfoTypeRegisterToRegisterPlusOffset:
{
- std::string base_reg_name;
- std::string data_reg_name;
- TranslateRegister (context.info.RegisterToRegisterPlusOffset.base_reg.kind,
- context.info.RegisterToRegisterPlusOffset.base_reg.num,
- base_reg_name);
- TranslateRegister (context.info.RegisterToRegisterPlusOffset.data_reg.kind,
- context.info.RegisterToRegisterPlusOffset.data_reg.num,
- data_reg_name);
- fprintf (stdout, " Info type: Register plus offset (%s +/- %lld) and data register (%s)\n",
- base_reg_name.c_str(), context.info.RegisterToRegisterPlusOffset.offset,
- data_reg_name.c_str());
+ fprintf (fh, " (base_and_imm_offset = %s%+lld, data_reg = %s)\n",
+ info.RegisterToRegisterPlusOffset.base_reg.name,
+ info.RegisterToRegisterPlusOffset.offset,
+ info.RegisterToRegisterPlusOffset.data_reg.name);
}
- break;
- case eInfoTypeRegisterToRegisterPlusIndirectOffset:
+ break;
+
+ case eInfoTypeRegisterToRegisterPlusIndirectOffset:
{
- std::string base_reg_name;
- std::string offset_reg_name;
- std::string data_reg_name;
- TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.base_reg.kind,
- context.info.RegisterToRegisterPlusIndirectOffset.base_reg.num,
- base_reg_name);
- TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.offset_reg.kind,
- context.info.RegisterToRegisterPlusIndirectOffset.offset_reg.num,
- offset_reg_name);
- TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.data_reg.kind,
- context.info.RegisterToRegisterPlusIndirectOffset.data_reg.num,
- data_reg_name);
- fprintf (stdout, " Info type: Register plus indirect offset (%s +/- %s) and data register (%s)\n",
- base_reg_name.c_str(), offset_reg_name.c_str(), data_reg_name.c_str());
+ fprintf (fh, " (base_and_reg_offset = %s + %s, data_reg = %s)\n",
+ info.RegisterToRegisterPlusIndirectOffset.base_reg.name,
+ info.RegisterToRegisterPlusIndirectOffset.offset_reg.name,
+ info.RegisterToRegisterPlusIndirectOffset.data_reg.name);
}
- break;
+ break;
+
+ case eInfoTypeRegisterRegisterOperands:
+ {
+ fprintf (fh, " (register to register binary op: %s and %s)\n",
+ info.RegisterRegisterOperands.operand1.name,
+ info.RegisterRegisterOperands.operand2.name);
+ }
+ break;
+
+ case eInfoTypeOffset:
+ fprintf (fh, " (signed_offset = %+lld)\n", info.signed_offset);
+ break;
- case eInfoTypeRegisterRegisterOperands:
- {
- std::string op1_reg_name;
- std::string op2_reg_name;
- TranslateRegister (context.info.RegisterRegisterOperands.operand1.kind,
- context.info.RegisterRegisterOperands.operand1.num,
- op1_reg_name);
- TranslateRegister (context.info.RegisterRegisterOperands.operand2.kind,
- context.info.RegisterRegisterOperands.operand2.num,
- op2_reg_name);
- fprintf (stdout, " Info type: Register operands for binary op (%s, %s)\n",
- op1_reg_name.c_str(),
- op2_reg_name.c_str());
- }
- break;
- case eInfoTypeOffset:
- fprintf (stdout, " Info type: signed offset (%lld)\n", context.info.signed_offset);
- break;
-
- case eInfoTypeRegister:
- {
- std::string reg_name;
- TranslateRegister (context.info.reg.kind, context.info.reg.num, reg_name);
- fprintf (stdout, " Info type: Register (%s)\n", reg_name.c_str());
- }
- break;
-
- case eInfoTypeImmediate:
- fprintf (stdout, " Info type: Immediate (%lld)\n", context.info.immediate);
- break;
+ case eInfoTypeRegister:
+ fprintf (fh, " (reg = %s)\n", info.reg.name);
+ break;
+
+ case eInfoTypeImmediate:
+ fprintf (fh,
+ " (unsigned_immediate = %llu (0x%16.16llx))\n",
+ info.unsigned_immediate,
+ info.unsigned_immediate);
+ break;
- case eInfoTypeImmediateSigned:
- fprintf (stdout, " Info type: Signed immediate (%lld)\n", context.info.signed_immediate);
- break;
-
- case eInfoTypeAddress:
- fprintf (stdout, " Info type: Address (%p)\n", (void *) context.info.address);
- break;
-
- case eInfoTypeModeAndImmediate:
- {
- std::string mode_name;
-
- if (context.info.ModeAndImmediate.mode == EmulateInstructionARM::eModeARM)
- mode_name = "ARM";
- else if (context.info.ModeAndImmediate.mode == EmulateInstructionARM::eModeThumb)
- mode_name = "Thumb";
- else
- mode_name = "Unknown mode";
+ case eInfoTypeImmediateSigned:
+ fprintf (fh,
+ " (signed_immediate = %+lld (0x%16.16llx))\n",
+ info.signed_immediate,
+ info.signed_immediate);
+ break;
+
+ case eInfoTypeAddress:
+ fprintf (fh, " (address = 0x%llx)\n", info.address);
+ break;
+
+ case eInfoTypeISAAndImmediate:
+ fprintf (fh,
+ " (isa = %u, unsigned_immediate = %u (0x%8.8x))\n",
+ info.ISAAndImmediate.isa,
+ info.ISAAndImmediate.unsigned_data32,
+ info.ISAAndImmediate.unsigned_data32);
+ break;
+
+ case eInfoTypeISAAndImmediateSigned:
+ fprintf (fh,
+ " (isa = %u, signed_immediate = %i (0x%8.8x))\n",
+ info.ISAAndImmediateSigned.isa,
+ info.ISAAndImmediateSigned.signed_data32,
+ info.ISAAndImmediateSigned.signed_data32);
+ break;
+
+ case eInfoTypeISA:
+ fprintf (fh, " (isa = %u)\n", info.isa);
+ break;
+
+ case eInfoTypeNoArgs:
+ fprintf (fh, " \n");
+ break;
- fprintf (stdout, " Info type: Mode (%s) and immediate (%d)\n", mode_name.c_str(),
- context.info.ModeAndImmediate.data_value);
- }
- break;
-
- case eInfoTypeModeAndImmediateSigned:
- {
- std::string mode_name;
-
- if (context.info.ModeAndImmediateSigned.mode == EmulateInstructionARM::eModeARM)
- mode_name = "ARM";
- else if (context.info.ModeAndImmediateSigned.mode == EmulateInstructionARM::eModeThumb)
- mode_name = "Thumb";
- else
- mode_name = "Unknown mode";
-
- fprintf (stdout, " Info type: Mode (%s) and signed immediate (%d)\n", mode_name.c_str(),
- context.info.ModeAndImmediateSigned.signed_data_value);
- }
- break;
-
- case eInfoTypeMode:
- {
- std::string mode_name;
-
- if (context.info.mode == EmulateInstructionARM::eModeARM)
- mode_name = "ARM";
- else if (context.info.mode == EmulateInstructionARM::eModeThumb)
- mode_name = "Thumb";
- else
- mode_name = "Unknown mode";
-
- fprintf (stdout, " Info type: Mode (%s)\n", mode_name.c_str());
- }
- break;
-
- case eInfoTypeNoArgs:
- fprintf (stdout, " Info type: no arguments\n");
- break;
-
- default:
- break;
+ default:
+ fprintf (fh, " (unknown <info_type>)\n");
+ break;
}
}
@@ -593,54 +547,65 @@
return true;
}
-
-const char *
-EmulateInstruction::TranslateRegister (uint32_t kind, uint32_t num, std::string &name)
+bool
+EmulateInstruction::GetBestRegisterKindAndNumber (const RegisterInfo ®_info,
+ uint32_t ®_kind,
+ uint32_t ®_num)
{
- if (kind == eRegisterKindGeneric)
+ // Generic and DWARF should be the two most popular register kinds when
+ // emulating instructions since they are the most platform agnostic...
+ reg_num = reg_info.kinds[eRegisterKindGeneric];
+ if (reg_num != LLDB_INVALID_REGNUM)
{
- switch (num)
- {
- case LLDB_REGNUM_GENERIC_PC: name = "pc"; break;
- case LLDB_REGNUM_GENERIC_SP: name = "sp"; break;
- case LLDB_REGNUM_GENERIC_FP: name = "fp"; break;
- case LLDB_REGNUM_GENERIC_RA: name = "ra"; break;
- case LLDB_REGNUM_GENERIC_FLAGS: name = "flags"; break;
- default: name.clear(); break;
- }
- if (!name.empty())
- return name.c_str();
+ reg_kind = eRegisterKindGeneric;
+ return true;
}
- const char *kind_cstr = NULL;
- switch (kind)
+ reg_num = reg_info.kinds[eRegisterKindDWARF];
+ if (reg_num != LLDB_INVALID_REGNUM)
{
- case eRegisterKindGCC: // the register numbers seen in eh_frame
- kind_cstr = "gcc";
- break;
+ reg_kind = eRegisterKindDWARF;
+ return true;
+ }
- case eRegisterKindDWARF: // the register numbers seen DWARF
- kind_cstr = "dwarf";
- break;
-
- case eRegisterKindGeneric: // insn ptr reg, stack ptr reg, etc not specific to any particular target
- kind_cstr = "generic";
- break;
-
- case eRegisterKindGDB: // the register numbers gdb uses (matches stabs numbers?)
- kind_cstr = "gdb";
- break;
-
- case eRegisterKindLLDB: // lldb's internal register numbers
- kind_cstr = "lldb";
- break;
+ reg_num = reg_info.kinds[eRegisterKindLLDB];
+ if (reg_num != LLDB_INVALID_REGNUM)
+ {
+ reg_kind = eRegisterKindLLDB;
+ return true;
}
-
-
- StreamString sstr;
- sstr.Printf ("%s(%u)", kind_cstr, num);
- name.swap (sstr.GetString());
- return name.c_str();
+
+ reg_num = reg_info.kinds[eRegisterKindGCC];
+ if (reg_num != LLDB_INVALID_REGNUM)
+ {
+ reg_kind = eRegisterKindGCC;
+ return true;
+ }
+
+ reg_num = reg_info.kinds[eRegisterKindGDB];
+ if (reg_num != LLDB_INVALID_REGNUM)
+ {
+ reg_kind = eRegisterKindGDB;
+ return true;
+ }
+ return false;
+}
+
+uint32_t
+EmulateInstruction::GetInternalRegisterNumber (RegisterContext *reg_ctx, const RegisterInfo ®_info)
+{
+ uint32_t reg_kind, reg_num;
+ if (reg_ctx && GetBestRegisterKindAndNumber (reg_info, reg_kind, reg_num))
+ return reg_ctx->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num);
+ return LLDB_INVALID_REGNUM;
+}
+
+
+bool
+EmulateInstruction::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
+{
+ unwind_plan.Clear();
+ return false;
}
diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
index e445687..c791414 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
@@ -16,6 +16,7 @@
#include "lldb/Core/ConstString.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/Stream.h"
+#include "lldb/Symbol/UnwindPlan.h"
#include "Plugins/Process/Utility/ARMDefines.h"
#include "Plugins/Process/Utility/ARMUtils.h"
@@ -252,6 +253,27 @@
return true;
}
+bool
+EmulateInstructionARM::GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info)
+{
+ if (reg_kind == eRegisterKindGeneric)
+ {
+ switch (reg_num)
+ {
+ case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc; break;
+ case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp; break;
+ case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r7; break;
+ case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_lr; break;
+ case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_cpsr; break;
+ default: return false;
+ }
+ }
+
+ if (reg_kind == eRegisterKindDWARF)
+ return GetARMDWARFRegisterInfo(reg_num, reg_info);
+ return false;
+}
+
// Push Multiple Registers stores multiple registers to the stack, storing to
// consecutive memory locations ending just below the address in SP, and updates
// SP to point to the start of the stored data.
@@ -340,16 +362,15 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, 0);
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo reg_info;
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i=0; i<15; ++i)
{
if (BitIsSet (registers, i))
{
- dwarf_reg.num = dwarf_r0 + i;
- context.SetRegisterToRegisterPlusOffset (dwarf_reg, sp_reg, addr - sp);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, reg_info);
+ context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
uint32_t reg_value = ReadCoreReg(i, &success);
if (!success)
return false;
@@ -361,8 +382,8 @@
if (BitIsSet (registers, 15))
{
- dwarf_reg.num = dwarf_pc;
- context.SetRegisterPlusOffset (dwarf_reg, addr - sp);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, reg_info);
+ context.SetRegisterPlusOffset (reg_info, addr - sp);
const uint32_t pc = ReadCoreReg(PC_REG, &success);
if (!success)
return false;
@@ -393,7 +414,7 @@
address = SP;
for i = 0 to 14
if registers<i> == '1' then
- R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
+ R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
if registers<15> == '1' then
if UnalignedAllowed then
LoadWritePC(MemU[address,4]);
@@ -406,8 +427,7 @@
bool success = false;
- if (ConditionPassed(opcode))
- {
+ if (ConditionPassed(opcode)) {
const uint32_t addr_byte_size = GetAddressByteSize();
const addr_t sp = ReadCoreReg (SP_REG, &success);
if (!success)
@@ -469,20 +489,21 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPopRegisterOffStack;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, 0);
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
+
for (i=0; i<15; ++i)
{
if (BitIsSet (registers, i))
{
- dwarf_reg.num = dwarf_r0 + i;
context.SetRegisterPlusOffset (sp_reg, addr - sp);
data = MemARead(context, addr, 4, 0, &success);
if (!success)
return false;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data))
+ RegisterInfo reg_info;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, reg_info);
+ if (!WriteRegisterUnsigned(context, reg_info, data))
return false;
addr += addr_byte_size;
}
@@ -490,7 +511,6 @@
if (BitIsSet (registers, 15))
{
- dwarf_reg.num = dwarf_pc;
context.SetRegisterPlusOffset (sp_reg, addr - sp);
data = MemARead(context, addr, 4, 0, &success);
if (!success)
@@ -559,8 +579,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextAdjustStackPointer;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
context.SetRegisterPlusOffset (sp_reg, sp_offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
@@ -613,8 +633,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
context.SetRegisterPlusOffset (sp_reg, 0);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
@@ -706,8 +726,8 @@
// The context specifies that Rm is to be moved into Rd.
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterLoad;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
context.SetRegister (dwarf_reg);
if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
@@ -922,13 +942,13 @@
uint64_t result = operand1 * operand2;
// R[d] = result<31:0>;
- Register op1_reg;
- Register op2_reg;
- op1_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- op2_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo op1_reg;
+ RegisterInfo op2_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, op2_reg);
EmulateInstruction::Context context;
- context.type = eContextMultiplication;
+ context.type = eContextArithmetic;
context.SetRegisterRegisterOperands (op1_reg, op2_reg);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (0x0000ffff & result)))
@@ -1129,8 +1149,8 @@
// PC relative immediate load context
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register pc_reg;
- pc_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
+ RegisterInfo pc_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
context.SetRegisterPlusOffset (pc_reg, 0);
uint32_t Rt; // the destination register
@@ -1249,8 +1269,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextAdjustStackPointer;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
context.SetRegisterPlusOffset (sp_reg, sp_offset);
if (d == 15)
@@ -1313,11 +1333,12 @@
addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
EmulateInstruction::Context context;
- context.type = EmulateInstruction::eContextAddition;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
- Register other_reg;
- other_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+ context.type = eContextArithmetic;
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
+
+ RegisterInfo other_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
context.SetRegisterRegisterOperands (sp_reg, other_reg);
if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr))
@@ -1377,7 +1398,7 @@
uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
imm32 = llvm::SignExtend32<25>(imm25);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
if (InITBlock() && !LastInITBlock())
return false;
break;
@@ -1395,7 +1416,7 @@
uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
imm32 = llvm::SignExtend32<25>(imm25);
target = Align(pc, 4) + imm32;
- context.SetModeAndImmediateSigned (eModeARM, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeARM, 4 + imm32);
if (InITBlock() && !LastInITBlock())
return false;
break;
@@ -1404,13 +1425,13 @@
lr = pc - 4; // return address
imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
target = Align(pc, 4) + imm32;
- context.SetModeAndImmediateSigned (eModeARM, 8 + imm32);
+ context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
break;
case eEncodingA2:
lr = pc - 4; // return address
imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 8 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 8 + imm32);
break;
default:
return false;
@@ -1479,8 +1500,8 @@
addr_t target = ReadCoreReg (Rm, &success);
if (!success)
return false;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
context.SetRegister (dwarf_reg);
if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
return false;
@@ -1524,9 +1545,9 @@
addr_t target = ReadCoreReg (Rm, &success);
if (!success)
return false;
-
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
context.SetRegister (dwarf_reg);
if (!BXWritePC(context, target))
return false;
@@ -1583,8 +1604,8 @@
if (!success)
return false;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
context.SetRegister (dwarf_reg);
if (!BXWritePC(context, target))
return false;
@@ -1634,8 +1655,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r12);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r12, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, -ip_offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr))
@@ -1686,8 +1707,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, -sp_offset);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr))
@@ -1851,8 +1872,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
context.SetRegisterPlusOffset (sp_reg, addr - sp);
if (Rt != 15)
{
@@ -1952,16 +1973,15 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPushRegisterOnStack;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, 0);
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo dwarf_reg;
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i=0; i<regs; ++i)
{
- dwarf_reg.num = start_reg + d + i;
+ GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
// uint64_t to accommodate 64-bit registers.
- uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success);
+ uint64_t reg_value = ReadRegisterUnsigned(dwarf_reg, 0, &success);
if (!success)
return false;
if (!MemAWrite (context, addr, reg_value, reg_byte_size))
@@ -2047,18 +2067,17 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextPopRegisterOffStack;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, 0);
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+ RegisterInfo dwarf_reg;
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
for (i=0; i<regs; ++i)
{
- dwarf_reg.num = start_reg + d + i;
+ GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
context.SetRegisterPlusOffset (sp_reg, addr - sp);
data = MemARead(context, addr, reg_byte_size, 0, &success);
if (!success)
return false;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data))
+ if (!WriteRegisterUnsigned(context, dwarf_reg, data))
return false;
addr += reg_byte_size;
}
@@ -2112,7 +2131,7 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextSupervisorCall;
- context.SetModeAndImmediate (mode, imm32);
+ context.SetISAAndImmediate (mode, imm32);
if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
return false;
}
@@ -2162,12 +2181,12 @@
// The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
break;
case eEncodingT2:
imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
break;
case eEncodingT3:
// The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
@@ -2180,7 +2199,7 @@
uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
imm32 = llvm::SignExtend32<21>(imm21);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
break;
}
case eEncodingT4:
@@ -2195,13 +2214,13 @@
uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
imm32 = llvm::SignExtend32<25>(imm25);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
break;
}
case eEncodingA1:
imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeARM, 8 + imm32);
+ context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
break;
default:
return false;
@@ -2246,7 +2265,7 @@
imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
nonzero = BitIsSet(opcode, 11);
target = pc + imm32;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
break;
default:
return false;
@@ -2326,7 +2345,7 @@
// target address
addr_t target = pc + offset;
context.type = EmulateInstruction::eContextRelativeBranchImmediate;
- context.SetModeAndImmediateSigned (eModeThumb, 4 + offset);
+ context.SetISAAndImmediateSigned (eModeThumb, 4 + offset);
if (!BranchWritePC(context, target))
return false;
@@ -2427,11 +2446,11 @@
//(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
AddWithCarryResult res = AddWithCarry (Rn, imm32, 0);
- Register reg_n;
- reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo reg_n;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
EmulateInstruction::Context context;
- context.type = eContextAddition;
+ context.type = eContextArithmetic;
context.SetRegisterPlusOffset (reg_n, imm32);
//R[d] = result;
@@ -2495,9 +2514,9 @@
AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
EmulateInstruction::Context context;
- context.type = EmulateInstruction::eContextAddition;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, Rn);
+ context.type = eContextArithmetic;
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, Rn, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, imm32);
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
@@ -2582,11 +2601,11 @@
AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
EmulateInstruction::Context context;
- context.type = EmulateInstruction::eContextAddition;
- Register op1_reg;
- Register op2_reg;
- op1_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn);
- op2_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
+ context.type = eContextArithmetic;
+ RegisterInfo op1_reg;
+ RegisterInfo op2_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
context.SetRegisterRegisterOperands (op1_reg, op2_reg);
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
@@ -3297,8 +3316,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, offset);
for (int i = 0; i < 14; ++i)
@@ -3414,8 +3433,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, offset);
// for i = 0 to 14
@@ -3551,8 +3570,8 @@
addr_t address = Rn - (addr_byte_size * BitCount (registers));
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, Rn - address);
for (int i = 0; i < 14; ++i)
@@ -3663,8 +3682,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterPlusOffset;
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
context.SetRegisterPlusOffset (dwarf_reg, offset);
for (int i = 0; i < 14; ++i)
@@ -3833,8 +3852,8 @@
address = (index ? offset_addr : base);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
if (wback)
{
EmulateInstruction::Context ctx;
@@ -3966,8 +3985,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
// for i = 0 to 14
int lowest_set_bit = 14;
@@ -3989,8 +4008,8 @@
if (!success)
return false;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
if (!MemAWrite (context, address + offset, data, addr_byte_size))
return false;
@@ -4005,8 +4024,8 @@
// MemA[address,4] = PCStoreValue();
if (BitIsSet (registers, 15))
{
- Register pc_reg;
- pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc);
+ RegisterInfo pc_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
context.SetRegisterPlusOffset (pc_reg, 8);
const uint32_t pc = ReadCoreReg (PC_REG, &success);
if (!success)
@@ -4091,8 +4110,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
// for i = 0 to 14
int lowest_bit_set = 14;
@@ -4114,8 +4133,8 @@
if (!success)
return false;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
if (!MemAWrite (context, address + offset, data, addr_byte_size))
return false;
@@ -4130,8 +4149,8 @@
// MemA[address,4] = PCStoreValue();
if (BitIsSet (registers, 15))
{
- Register pc_reg;
- pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc);
+ RegisterInfo pc_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
context.SetRegisterPlusOffset (pc_reg, 8);
const uint32_t pc = ReadCoreReg (PC_REG, &success);
if (!success)
@@ -4242,8 +4261,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
// for i = 0 to 14
uint32_t lowest_set_bit = 14;
@@ -4265,8 +4284,8 @@
if (!success)
return false;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
if (!MemAWrite (context, address + offset, data, addr_byte_size))
return false;
@@ -4281,8 +4300,8 @@
// MemA[address,4] = PCStoreValue();
if (BitIsSet (registers, 15))
{
- Register pc_reg;
- pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc);
+ RegisterInfo pc_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
context.SetRegisterPlusOffset (pc_reg, 8);
const uint32_t pc = ReadCoreReg (PC_REG, &success);
if (!success)
@@ -4367,8 +4386,8 @@
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t lowest_set_bit = 14;
// for i = 0 to 14
@@ -4391,8 +4410,8 @@
if (!success)
return false;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size);
if (!MemAWrite (context, address + offset, data, addr_byte_size))
return false;
@@ -4407,8 +4426,8 @@
// MemA[address,4] = PCStoreValue();
if (BitIsSet (registers, 15))
{
- Register pc_reg;
- pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc);
+ RegisterInfo pc_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
context.SetRegisterPlusOffset (pc_reg, 8);
const uint32_t pc = ReadCoreReg (PC_REG, &success);
if (!success)
@@ -4556,8 +4575,8 @@
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
// if UnalignedSupport() || address<1:0> == '00' then
if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
@@ -4567,8 +4586,8 @@
if (!success)
return false;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
int32_t offset = address - base_address;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
if (!MemUWrite (context, address, data, addr_byte_size))
@@ -4754,11 +4773,11 @@
{
// MemU[address,4] = data;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
if (!MemUWrite (context, address, data, addr_byte_size))
@@ -4884,11 +4903,11 @@
address = base_address;
// MemU[address,1] = R[t]<7:0>
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
@@ -5050,10 +5069,10 @@
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
// if UnalignedSupport() || address<0> == '0' then
if (UnalignedSupport() || BitIsClear (address, 0))
@@ -5065,12 +5084,12 @@
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
@@ -5713,8 +5732,8 @@
// data = MemU[address,4];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -5916,8 +5935,8 @@
address = Rn;
// data = MemU[address,4];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6087,10 +6106,10 @@
address = Rn;
// R[t] = ZeroExtend(MemU[address,1], 32);
- Register base_reg;
- Register data_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6323,8 +6342,8 @@
address = Rn;
// R[t] = ZeroExtend(MemU[address,1],32);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6461,8 +6480,8 @@
address = Rn;
// data = MemU[address,2];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6575,8 +6594,8 @@
address = base - imm32;
// data = MemU[address,2];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6740,10 +6759,10 @@
address = Rn;
// data = MemU[address,2];
- Register base_reg;
- Register offset_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo base_reg;
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -6901,8 +6920,8 @@
address = Rn;
// R[t] = SignExtend(MemU[address,1], 32);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7000,8 +7019,8 @@
address = base - imm32;
// R[t] = SignExtend(MemU[address,1], 32);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7145,10 +7164,10 @@
address = Rn;
// R[t] = SignExtend(MemU[address,1], 32);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7296,8 +7315,8 @@
address = Rn;
// data = MemU[address,2];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7410,8 +7429,8 @@
address = base - imm32;
// data = MemU[address,2];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7572,11 +7591,11 @@
address = Rn;
// data = MemU[address,2];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7684,8 +7703,8 @@
// R[d] = SignExtend(rotated<7:0>, 32);
int64_t data = llvm::SignExtend64<8>(rotated);
- Register source_reg;
- source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo source_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7764,8 +7783,8 @@
uint64_t rotated = ROR (Rm, rotation);
// R[d] = SignExtend(rotated<15:0>, 32);
- Register source_reg;
- source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo source_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7846,8 +7865,8 @@
uint64_t rotated = ROR (Rm, rotation);
// R[d] = ZeroExtend(rotated<7:0>, 32);
- Register source_reg;
- source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo source_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -7925,8 +7944,8 @@
uint64_t rotated = ROR (Rm, rotation);
// R[d] = ZeroExtend(rotated<15:0>, 32);
- Register source_reg;
- source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo source_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -8043,8 +8062,8 @@
address = address + 4;
// CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextReturnFromException;
@@ -9331,11 +9350,11 @@
AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1);
EmulateInstruction::Context context;
- context.type = eContextSubtraction;
- Register sp_reg;
- sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
- Register dwarf_reg;
- dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ context.type = eContextArithmetic;
+ RegisterInfo sp_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
+ RegisterInfo dwarf_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, dwarf_reg);
context.SetRegisterRegisterOperands (sp_reg, dwarf_reg);
if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
@@ -9419,11 +9438,11 @@
// R[d] = result;
EmulateInstruction::Context context;
- context.type = eContextAddition;
- Register reg_n;
- reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 +n);
- Register reg_m;
- reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ context.type = eContextArithmetic;
+ RegisterInfo reg_n;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
+ RegisterInfo reg_m;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
context.SetRegisterRegisterOperands (reg_n, reg_m);
@@ -9551,11 +9570,11 @@
// APSR.V = overflow;
EmulateInstruction::Context context;
- context.type = eContextSubtraction;
- Register reg_n;
- reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register reg_m;
- reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ context.type = eContextArithmetic;
+ RegisterInfo reg_n;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
+ RegisterInfo reg_m;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
context.SetRegisterRegisterOperands (reg_n, reg_m);
if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
@@ -9638,10 +9657,10 @@
addr_t address = Rn + imm32;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, imm32);
@@ -9748,10 +9767,10 @@
if (!success)
return false;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
@@ -9838,10 +9857,10 @@
else
address = Rn;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
@@ -9986,8 +10005,8 @@
address = Rn;
//R[t] = MemA[address,4];
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
@@ -10093,14 +10112,14 @@
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
return false;
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rm = ReadCoreReg (m, &success);
if (!success)
return false;
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
// offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
addr_t offset_addr;
@@ -10238,8 +10257,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -10260,8 +10279,8 @@
address = Rn;
//MemA[address,4] = R[t];
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
uint32_t data = ReadCoreReg (t, &success);
if (!success)
@@ -10277,7 +10296,7 @@
return false;
//MemA[address+4,4] = R[t2];
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t2);
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
data = ReadCoreReg (t2, &success);
@@ -10367,12 +10386,11 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
- Register offset_reg;
- offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
+ RegisterInfo offset_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
+ RegisterInfo data_reg;
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -10402,6 +10420,7 @@
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
const uint32_t addr_byte_size = GetAddressByteSize();
@@ -10414,7 +10433,7 @@
if (!success)
return false;
- data_reg.num = dwarf_r0 + t2;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
@@ -10445,7 +10464,7 @@
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
address = if add then R[n] else R[n]-imm32;
- if wback then R[n] = if add then R[n}+imm32 else R[n]-imm32;
+ if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
for r = 0 to regs-1
if single_regs then
S[d+r] = MemA[address,4]; address = address+4;
@@ -10536,8 +10555,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -10550,7 +10569,7 @@
else
address = Rn - imm32;
- // if wback then R[n] = if add then R[n}+imm32 else R[n]-imm32;
+ // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
EmulateInstruction::Context context;
if (wback)
@@ -10636,7 +10655,7 @@
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
address = if add then R[n] else R[n]-imm32;
- if wback then R[n] = if add then R[n}+imm32 else R[n]-imm32;
+ if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
for r = 0 to regs-1
if single_regs then
MemA[address,4] = S[d+r]; address = address+4;
@@ -10729,8 +10748,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -10744,7 +10763,7 @@
address = Rn - imm32;
EmulateInstruction::Context context;
- // if wback then R[n] = if add then R[n}+imm32 else R[n]-imm32;
+ // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
if (wback)
{
uint32_t value;
@@ -10767,16 +10786,16 @@
// for r = 0 to regs-1
for (int r = 0; r < regs; ++r)
{
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, 0);
+
if (single_regs)
{
// MemA[address,4] = S[d+r]; address = address+4;
uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d + r, 0, &success);
if (!success)
return false;
-
- data_reg.num = start_reg + d + r;
+
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
if (!MemAWrite (context, address, data, addr_byte_size))
return false;
@@ -10792,7 +10811,8 @@
if (!success)
return false;
- data_reg.num = start_reg + d + r;
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
if (GetByteOrder() == eByteOrderBig)
{
@@ -10882,8 +10902,8 @@
default:
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11020,8 +11040,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11037,8 +11057,8 @@
const uint32_t addr_byte_size = GetAddressByteSize();
uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, start_reg + d);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, start_reg + d, data_reg);
EmulateInstruction::Context context;
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
@@ -11191,8 +11211,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11359,8 +11379,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11526,8 +11546,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11559,13 +11579,12 @@
return false;
}
+ RegisterInfo data_reg;
context.type = eContextRegisterStore;
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, 0);
// for r = 0 to regs-1
for (int r = 0; r < regs; ++r)
{
- data_reg.num = dwarf_d0 + d + r;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d + r, data_reg);
uint64_t register_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success);
if (!success)
return false;
@@ -11695,8 +11714,8 @@
return false;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -11735,8 +11754,8 @@
uint64_t word = Bits64 (register_data, ((index + 1) * esize) - 1, index * esize);
- Register data_reg;
- data_reg.SetRegister (eRegisterKindDWARF, dwarf_d0 + d);
+ RegisterInfo data_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d, data_reg);
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
@@ -11821,8 +11840,8 @@
break;
}
- Register base_reg;
- base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 +n);
+ RegisterInfo base_reg;
+ GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
uint32_t Rn = ReadCoreReg (n, &success);
if (!success)
@@ -12958,7 +12977,7 @@
cpsr_changed = true;
}
target = addr & 0xfffffffe;
- context.SetMode (eModeThumb);
+ context.SetISA (eModeThumb);
}
else if (BitIsClear(addr, 1))
{
@@ -12968,7 +12987,7 @@
cpsr_changed = true;
}
target = addr & 0xfffffffc;
- context.SetMode (eModeARM);
+ context.SetISA (eModeARM);
}
else
return false; // address<1:0> == '10' => UNPREDICTABLE
@@ -13369,27 +13388,52 @@
return success;
}
-
-
-const char *
-EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num)
+//
+//
+//const char *
+//EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num)
+//{
+// if (reg_kind == eRegisterKindGeneric)
+// {
+// switch (reg_num)
+// {
+// case LLDB_REGNUM_GENERIC_PC: return "pc";
+// case LLDB_REGNUM_GENERIC_SP: return "sp";
+// case LLDB_REGNUM_GENERIC_FP: return "fp";
+// case LLDB_REGNUM_GENERIC_RA: return "lr";
+// case LLDB_REGNUM_GENERIC_FLAGS: return "cpsr";
+// default: return NULL;
+// }
+// }
+// else if (reg_kind == eRegisterKindDWARF)
+// {
+// return GetARMDWARFRegisterName (reg_num);
+// }
+// return NULL;
+//}
+//
+bool
+EmulateInstructionARM::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
{
- if (reg_kind == eRegisterKindGeneric)
- {
- switch (reg_num)
- {
- case LLDB_REGNUM_GENERIC_PC: return "pc";
- case LLDB_REGNUM_GENERIC_SP: return "sp";
- case LLDB_REGNUM_GENERIC_FP: return "fp";
- case LLDB_REGNUM_GENERIC_RA: return "lr";
- case LLDB_REGNUM_GENERIC_FLAGS: return "cpsr";
- default: return NULL;
- }
- }
- else if (reg_kind == eRegisterKindDWARF)
- {
- return GetARMDWARFRegisterName (reg_num);
- }
- return NULL;
+ unwind_plan.SetRegisterKind (eRegisterKindDWARF);
+
+ UnwindPlan::Row row;
+ UnwindPlan::Row::RegisterLocation regloc;
+
+ // Our previous Call Frame Address is the stack pointer
+ row.SetCFARegister (dwarf_sp);
+
+ // Our previous PC is in the LR
+ regloc.SetInRegister(dwarf_lr);
+ row.SetRegisterInfo (dwarf_pc, regloc);
+ unwind_plan.AppendRow (row);
+
+ // All other registers are the same.
+
+ unwind_plan.SetSourceName ("EmulateInstructionARM");
+ return true;
}
+
+
+
diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
index bb7b7c2..dbafe69 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
@@ -120,7 +120,7 @@
enum Mode
{
- eModeInvalid,
+ eModeInvalid = -1,
eModeARM,
eModeThumb
};
@@ -178,8 +178,12 @@
virtual bool
TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data);
- virtual const char *
- GetRegisterName (uint32_t reg_kind, uint32_t reg_num);
+ virtual bool
+ GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info);
+
+
+ virtual bool
+ CreateFunctionEntryUnwind (UnwindPlan &unwind_plan);
uint32_t
ArchVersion();
diff --git a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
index 72fc484..296b13a 100644
--- a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
@@ -254,8 +254,7 @@
bool
EmulationStateARM::ReadPseudoRegister (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value)
{
if (!baton)
@@ -264,23 +263,8 @@
bool success = true;
EmulationStateARM *pseudo_state = (EmulationStateARM *) baton;
- if (reg_kind == eRegisterKindGeneric)
- {
- switch (reg_num)
- {
- case LLDB_REGNUM_GENERIC_PC:
- reg_num = dwarf_pc; break;
- case LLDB_REGNUM_GENERIC_SP:
- reg_num = dwarf_sp; break;
- case LLDB_REGNUM_GENERIC_FLAGS:
- reg_num = dwarf_cpsr; break;
- case LLDB_REGNUM_GENERIC_RA:
- reg_num = dwarf_lr; break;
- default:
- break;
- }
- }
- reg_value = pseudo_state->ReadPseudoRegisterValue (reg_num, success);
+ assert (reg_info.kinds[eRegisterKindDWARF] != LLDB_INVALID_REGNUM);
+ reg_value = pseudo_state->ReadPseudoRegisterValue (reg_info.kinds[eRegisterKindDWARF], success);
return success;
@@ -290,32 +274,15 @@
EmulationStateARM::WritePseudoRegister (EmulateInstruction *instruction,
void *baton,
const EmulateInstruction::Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value)
{
if (!baton)
return false;
- if (reg_kind == eRegisterKindGeneric)
- {
- switch (reg_num)
- {
- case LLDB_REGNUM_GENERIC_PC:
- reg_num = dwarf_pc; break;
- case LLDB_REGNUM_GENERIC_SP:
- reg_num = dwarf_sp; break;
- case LLDB_REGNUM_GENERIC_FLAGS:
- reg_num = dwarf_cpsr; break;
- case LLDB_REGNUM_GENERIC_RA:
- reg_num = dwarf_lr; break;
- default:
- break;
- }
- }
-
+ assert (reg_info.kinds[eRegisterKindDWARF] != LLDB_INVALID_REGNUM);
EmulationStateARM *pseudo_state = (EmulationStateARM *) baton;
- return pseudo_state->StorePseudoRegisterValue (reg_num, reg_value);
+ return pseudo_state->StorePseudoRegisterValue (reg_info.kinds[eRegisterKindDWARF], reg_value);
}
bool
diff --git a/source/Plugins/Instruction/ARM/EmulationStateARM.h b/source/Plugins/Instruction/ARM/EmulationStateARM.h
index 1dcc680..b4cc28b 100644
--- a/source/Plugins/Instruction/ARM/EmulationStateARM.h
+++ b/source/Plugins/Instruction/ARM/EmulationStateARM.h
@@ -70,16 +70,14 @@
static bool
ReadPseudoRegister (lldb_private::EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const lldb_private::RegisterInfo ®_info,
uint64_t ®_value);
static bool
WritePseudoRegister (lldb_private::EmulateInstruction *instruction,
void *baton,
const lldb_private::EmulateInstruction::Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const lldb_private::RegisterInfo ®_info,
uint64_t reg_value);
private:
uint32_t m_gpr[17];
diff --git a/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp b/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
index 3e9cef3..df16f56 100644
--- a/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
+++ b/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
@@ -147,8 +147,8 @@
{
case llvm::Triple::x86_64:
case llvm::Triple::x86:
- case llvm::Triple::arm:
- case llvm::Triple::thumb:
+// case llvm::Triple::arm:
+// case llvm::Triple::thumb:
m_unwinder_ap.reset (new UnwindLLDB (*this));
break;
diff --git a/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp b/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
index d9855b7..238a1e5 100644
--- a/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+++ b/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
@@ -18,6 +18,7 @@
#include "lldb/Core/Error.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/StreamFile.h"
+#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Target/ExecutionContext.h"
#include "lldb/Target/Process.h"
#include "lldb/Target/Thread.h"
@@ -101,7 +102,9 @@
// Initialize the stack pointer with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future addresss sizes
- SetRegisterValue (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, (1ull << ((addr_byte_size * 8) - 1)));
+ RegisterInfo sp_reg_info;
+ m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp_reg_info);
+ SetRegisterValue(sp_reg_info, (1ull << ((addr_byte_size * 8) - 1)));
const InstructionList &inst_list = disasm_sp->GetInstructionList ();
const size_t num_instructions = inst_list.GetSize();
@@ -201,6 +204,31 @@
}
+uint64_t
+UnwindAssemblyInstEmulation::MakeRegisterKindValuePair (const lldb_private::RegisterInfo ®_info)
+{
+ uint32_t reg_kind, reg_num;
+ if (EmulateInstruction::GetBestRegisterKindAndNumber (reg_info, reg_kind, reg_num))
+ return (uint64_t)reg_kind << 24 | reg_num;
+ return 0ull;
+}
+
+void
+UnwindAssemblyInstEmulation::SetRegisterValue (const lldb_private::RegisterInfo ®_info, uint64_t reg_value)
+{
+ m_register_values[MakeRegisterKindValuePair (reg_info)] = reg_value;
+}
+
+uint64_t
+UnwindAssemblyInstEmulation::GetRegisterValue (const lldb_private::RegisterInfo ®_info)
+{
+ const uint64_t reg_id = MakeRegisterKindValuePair (reg_info);
+ RegisterValueMap::const_iterator pos = m_register_values.find(reg_id);
+ if (pos != m_register_values.end())
+ return pos->second;
+ return MakeRegisterKindValuePair (reg_info);
+}
+
size_t
UnwindAssemblyInstEmulation::ReadMemory (EmulateInstruction *instruction,
@@ -211,12 +239,11 @@
size_t dst_len)
{
//UnwindAssemblyInstEmulation *inst_emulator = (UnwindAssemblyInstEmulation *)baton;
- printf ("UnwindAssemblyInstEmulation::ReadMemory (context.type = %i, context.info_type = %i, addr = 0x%16.16llx, dst = %p, dst_len = %zu)\n",
- context.type,
- context.info_type,
+ printf ("UnwindAssemblyInstEmulation::ReadMemory (addr = 0x%16.16llx, dst = %p, dst_len = %zu, context = ",
addr,
dst,
dst_len);
+ context.Dump(stdout, instruction);
return dst_len;
}
@@ -236,27 +263,23 @@
instruction->GetArchitecture ().GetAddressByteSize());
StreamFile strm(stdout, false);
- strm.Printf ("UnwindAssemblyInstEmulation::WriteMemory (context.type = %i, context.info_type = %i, ",
- context.type,
- context.info_type);
+ strm.PutCString ("UnwindAssemblyInstEmulation::WriteMemory (");
data.Dump(&strm, 0, eFormatBytes, 1, dst_len, UINT32_MAX, addr, 0, 0);
- strm.EOL();
+ strm.PutCString (", context = ");
+ context.Dump(stdout, instruction);
return dst_len;
}
bool
UnwindAssemblyInstEmulation::ReadRegister (EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t ®_value)
{
UnwindAssemblyInstEmulation *inst_emulator = (UnwindAssemblyInstEmulation *)baton;
- const char *reg_name = instruction->GetRegisterName (reg_kind, reg_num);
+ reg_value = inst_emulator->GetRegisterValue (reg_info);
- reg_value = inst_emulator->GetRegisterValue (reg_kind, reg_num);
-
- printf ("UnwindAssemblyInstEmulation::ReadRegister (name = \"%s\") => value = 0x%16.16llx\n", reg_name, reg_value);
+ printf ("UnwindAssemblyInstEmulation::ReadRegister (name = \"%s\") => value = 0x%16.16llx\n", reg_info.name, reg_value);
return true;
}
@@ -265,20 +288,19 @@
UnwindAssemblyInstEmulation::WriteRegister (EmulateInstruction *instruction,
void *baton,
const EmulateInstruction::Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const RegisterInfo ®_info,
uint64_t reg_value)
{
UnwindAssemblyInstEmulation *inst_emulator = (UnwindAssemblyInstEmulation *)baton;
- const char *reg_name = instruction->GetRegisterName (reg_kind, reg_num);
- printf ("UnwindAssemblyInstEmulation::WriteRegister (name = \"%s\", value = 0x%16.16llx, context.type = %i, context.info_type = %i)\n",
- reg_name,
- reg_value,
- context.type,
- context.info_type);
+ printf ("UnwindAssemblyInstEmulation::WriteRegister (name = \"%s\", value = 0x%16.16llx, context =",
+ reg_info.name,
+ reg_value);
+ context.Dump(stdout, instruction);
- inst_emulator->SetRegisterValue (reg_kind, reg_num, reg_value);
+ inst_emulator->SetRegisterValue (reg_info, reg_value);
+
+ UnwindPlan::Row::RegisterLocation regloc;
switch (context.type)
{
@@ -296,9 +318,7 @@
case EmulateInstruction::eContextTableBranchReadMemory:
case EmulateInstruction::eContextWriteRegisterRandomBits:
case EmulateInstruction::eContextWriteMemoryRandomBits:
- case EmulateInstruction::eContextMultiplication:
- case EmulateInstruction::eContextAddition:
- case EmulateInstruction::eContextSubtraction:
+ case EmulateInstruction::eContextArithmetic:
case EmulateInstruction::eContextAdvancePC:
case EmulateInstruction::eContextReturnFromException:
break;
diff --git a/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h b/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h
index c18cbab..2cd9827 100644
--- a/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h
+++ b/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h
@@ -88,16 +88,14 @@
static bool
ReadRegister (lldb_private::EmulateInstruction *instruction,
void *baton,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const lldb_private::RegisterInfo ®_info,
uint64_t ®_value);
static bool
WriteRegister (lldb_private::EmulateInstruction *instruction,
void *baton,
const lldb_private::EmulateInstruction::Context &context,
- uint32_t reg_kind,
- uint32_t reg_num,
+ const lldb_private::RegisterInfo ®_info,
uint64_t reg_value);
@@ -118,26 +116,13 @@
}
static uint64_t
- MakeRegisterKindValuePair (uint32_t reg_kind, uint32_t reg_num)
- {
- return (uint64_t)reg_kind << 32 | reg_num;
- }
+ MakeRegisterKindValuePair (const lldb_private::RegisterInfo ®_info);
void
- SetRegisterValue (uint32_t reg_kind, uint32_t reg_num, uint64_t reg_value)
- {
- m_register_values[MakeRegisterKindValuePair (reg_kind, reg_num)] = reg_value;
- }
+ SetRegisterValue (const lldb_private::RegisterInfo ®_info, uint64_t reg_value);
uint64_t
- GetRegisterValue (uint32_t reg_kind, uint32_t reg_num)
- {
- const uint64_t reg_id = MakeRegisterKindValuePair (reg_kind, reg_num);
- RegisterValueMap::const_iterator pos = m_register_values.find(reg_id);
- if (pos != m_register_values.end())
- return pos->second;
- return (uint64_t)reg_kind << 24 | (uint64_t)reg_num;
- }
+ GetRegisterValue (const lldb_private::RegisterInfo ®_info);
std::auto_ptr<lldb_private::EmulateInstruction> m_inst_emulator_ap;
lldb_private::AddressRange* m_range_ptr;
diff --git a/source/Symbol/UnwindPlan.cpp b/source/Symbol/UnwindPlan.cpp
index 691b054..29985af 100644
--- a/source/Symbol/UnwindPlan.cpp
+++ b/source/Symbol/UnwindPlan.cpp
@@ -8,10 +8,11 @@
//===----------------------------------------------------------------------===//
#include "lldb/Symbol/UnwindPlan.h"
+
+#include "lldb/Core/ConstString.h"
#include "lldb/Target/Process.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Target/Thread.h"
-#include "lldb/Core/ConstString.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/source/Utility/ARM_DWARF_Registers.c b/source/Utility/ARM_DWARF_Registers.c
deleted file mode 100644
index 2008e19..0000000
--- a/source/Utility/ARM_DWARF_Registers.c
+++ /dev/null
@@ -1,183 +0,0 @@
-//===-- ARM_DWARF_Registers.c -----------------------------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARM_DWARF_Registers.h"
-
-const char *
-GetARMDWARFRegisterName (unsigned reg_num)
-{
- switch (reg_num)
- {
- case dwarf_r0: return "r0";
- case dwarf_r1: return "r1";
- case dwarf_r2: return "r2";
- case dwarf_r3: return "r3";
- case dwarf_r4: return "r4";
- case dwarf_r5: return "r5";
- case dwarf_r6: return "r6";
- case dwarf_r7: return "r7";
- case dwarf_r8: return "r8";
- case dwarf_r9: return "r9";
- case dwarf_r10: return "r10";
- case dwarf_r11: return "r11";
- case dwarf_r12: return "r12";
- case dwarf_sp: return "sp";
- case dwarf_lr: return "lr";
- case dwarf_pc: return "pc";
- case dwarf_cpsr:return "cpsr";
-
- case dwarf_s0: return "s0";
- case dwarf_s1: return "s1";
- case dwarf_s2: return "s2";
- case dwarf_s3: return "s3";
- case dwarf_s4: return "s4";
- case dwarf_s5: return "s5";
- case dwarf_s6: return "s6";
- case dwarf_s7: return "s7";
- case dwarf_s8: return "s8";
- case dwarf_s9: return "s9";
- case dwarf_s10: return "s10";
- case dwarf_s11: return "s11";
- case dwarf_s12: return "s12";
- case dwarf_s13: return "s13";
- case dwarf_s14: return "s14";
- case dwarf_s15: return "s15";
- case dwarf_s16: return "s16";
- case dwarf_s17: return "s17";
- case dwarf_s18: return "s18";
- case dwarf_s19: return "s19";
- case dwarf_s20: return "s20";
- case dwarf_s21: return "s21";
- case dwarf_s22: return "s22";
- case dwarf_s23: return "s23";
- case dwarf_s24: return "s24";
- case dwarf_s25: return "s25";
- case dwarf_s26: return "s26";
- case dwarf_s27: return "s27";
- case dwarf_s28: return "s28";
- case dwarf_s29: return "s29";
- case dwarf_s30: return "s30";
- case dwarf_s31: return "s31";
-
- // FPA Registers 0-7
- case dwarf_f0: return "f0";
- case dwarf_f1: return "f1";
- case dwarf_f2: return "f2";
- case dwarf_f3: return "f3";
- case dwarf_f4: return "f4";
- case dwarf_f5: return "f5";
- case dwarf_f6: return "f6";
- case dwarf_f7: return "f7";
-
- // Intel wireless MMX general purpose registers 0–7
- // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7)
- case dwarf_wCGR0: return "wCGR0/ACC0";
- case dwarf_wCGR1: return "wCGR1/ACC1";
- case dwarf_wCGR2: return "wCGR2/ACC2";
- case dwarf_wCGR3: return "wCGR3/ACC3";
- case dwarf_wCGR4: return "wCGR4/ACC4";
- case dwarf_wCGR5: return "wCGR5/ACC5";
- case dwarf_wCGR6: return "wCGR6/ACC6";
- case dwarf_wCGR7: return "wCGR7/ACC7";
-
- // Intel wireless MMX data registers 0–15
- case dwarf_wR0: return "wR0";
- case dwarf_wR1: return "wR1";
- case dwarf_wR2: return "wR2";
- case dwarf_wR3: return "wR3";
- case dwarf_wR4: return "wR4";
- case dwarf_wR5: return "wR5";
- case dwarf_wR6: return "wR6";
- case dwarf_wR7: return "wR7";
- case dwarf_wR8: return "wR8";
- case dwarf_wR9: return "wR9";
- case dwarf_wR10: return "wR10";
- case dwarf_wR11: return "wR11";
- case dwarf_wR12: return "wR12";
- case dwarf_wR13: return "wR13";
- case dwarf_wR14: return "wR14";
- case dwarf_wR15: return "wR15";
-
- case dwarf_spsr: return "spsr";
- case dwarf_spsr_fiq: return "spsr_fiq";
- case dwarf_spsr_irq: return "spsr_irq";
- case dwarf_spsr_abt: return "spsr_abt";
- case dwarf_spsr_und: return "spsr_und";
- case dwarf_spsr_svc: return "spsr_svc";
-
- case dwarf_r8_usr: return "r8_usr";
- case dwarf_r9_usr: return "r9_usr";
- case dwarf_r10_usr: return "r10_usr";
- case dwarf_r11_usr: return "r11_usr";
- case dwarf_r12_usr: return "r12_usr";
- case dwarf_r13_usr: return "r13_usr";
- case dwarf_r14_usr: return "r14_usr";
- case dwarf_r8_fiq: return "r8_fiq";
- case dwarf_r9_fiq: return "r9_fiq";
- case dwarf_r10_fiq: return "r10_fiq";
- case dwarf_r11_fiq: return "r11_fiq";
- case dwarf_r12_fiq: return "r12_fiq";
- case dwarf_r13_fiq: return "r13_fiq";
- case dwarf_r14_fiq: return "r14_fiq";
- case dwarf_r13_irq: return "r13_irq";
- case dwarf_r14_irq: return "r14_irq";
- case dwarf_r13_abt: return "r13_abt";
- case dwarf_r14_abt: return "r14_abt";
- case dwarf_r13_und: return "r13_und";
- case dwarf_r14_und: return "r14_und";
- case dwarf_r13_svc: return "r13_svc";
- case dwarf_r14_svc: return "r14_svc";
-
- // Intel wireless MMX control register in co-processor 0–7
- case dwarf_wC0: return "wC0";
- case dwarf_wC1: return "wC1";
- case dwarf_wC2: return "wC2";
- case dwarf_wC3: return "wC3";
- case dwarf_wC4: return "wC4";
- case dwarf_wC5: return "wC5";
- case dwarf_wC6: return "wC6";
- case dwarf_wC7: return "wC7";
-
- // VFP-v3/Neon
- case dwarf_d0: return "d0";
- case dwarf_d1: return "d1";
- case dwarf_d2: return "d2";
- case dwarf_d3: return "d3";
- case dwarf_d4: return "d4";
- case dwarf_d5: return "d5";
- case dwarf_d6: return "d6";
- case dwarf_d7: return "d7";
- case dwarf_d8: return "d8";
- case dwarf_d9: return "d9";
- case dwarf_d10: return "d10";
- case dwarf_d11: return "d11";
- case dwarf_d12: return "d12";
- case dwarf_d13: return "d13";
- case dwarf_d14: return "d14";
- case dwarf_d15: return "d15";
- case dwarf_d16: return "d16";
- case dwarf_d17: return "d17";
- case dwarf_d18: return "d18";
- case dwarf_d19: return "d19";
- case dwarf_d20: return "d20";
- case dwarf_d21: return "d21";
- case dwarf_d22: return "d22";
- case dwarf_d23: return "d23";
- case dwarf_d24: return "d24";
- case dwarf_d25: return "d25";
- case dwarf_d26: return "d26";
- case dwarf_d27: return "d27";
- case dwarf_d28: return "d28";
- case dwarf_d29: return "d29";
- case dwarf_d30: return "d30";
- case dwarf_d31: return "d31";
- }
- return 0;
-}
-
diff --git a/source/Utility/ARM_DWARF_Registers.cpp b/source/Utility/ARM_DWARF_Registers.cpp
new file mode 100644
index 0000000..384171e
--- /dev/null
+++ b/source/Utility/ARM_DWARF_Registers.cpp
@@ -0,0 +1,388 @@
+//===-- ARM_DWARF_Registers.c -----------------------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARM_DWARF_Registers.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+const char *
+GetARMDWARFRegisterName (unsigned reg_num)
+{
+ switch (reg_num)
+ {
+ case dwarf_r0: return "r0";
+ case dwarf_r1: return "r1";
+ case dwarf_r2: return "r2";
+ case dwarf_r3: return "r3";
+ case dwarf_r4: return "r4";
+ case dwarf_r5: return "r5";
+ case dwarf_r6: return "r6";
+ case dwarf_r7: return "r7";
+ case dwarf_r8: return "r8";
+ case dwarf_r9: return "r9";
+ case dwarf_r10: return "r10";
+ case dwarf_r11: return "r11";
+ case dwarf_r12: return "r12";
+ case dwarf_sp: return "sp";
+ case dwarf_lr: return "lr";
+ case dwarf_pc: return "pc";
+ case dwarf_cpsr:return "cpsr";
+
+ case dwarf_s0: return "s0";
+ case dwarf_s1: return "s1";
+ case dwarf_s2: return "s2";
+ case dwarf_s3: return "s3";
+ case dwarf_s4: return "s4";
+ case dwarf_s5: return "s5";
+ case dwarf_s6: return "s6";
+ case dwarf_s7: return "s7";
+ case dwarf_s8: return "s8";
+ case dwarf_s9: return "s9";
+ case dwarf_s10: return "s10";
+ case dwarf_s11: return "s11";
+ case dwarf_s12: return "s12";
+ case dwarf_s13: return "s13";
+ case dwarf_s14: return "s14";
+ case dwarf_s15: return "s15";
+ case dwarf_s16: return "s16";
+ case dwarf_s17: return "s17";
+ case dwarf_s18: return "s18";
+ case dwarf_s19: return "s19";
+ case dwarf_s20: return "s20";
+ case dwarf_s21: return "s21";
+ case dwarf_s22: return "s22";
+ case dwarf_s23: return "s23";
+ case dwarf_s24: return "s24";
+ case dwarf_s25: return "s25";
+ case dwarf_s26: return "s26";
+ case dwarf_s27: return "s27";
+ case dwarf_s28: return "s28";
+ case dwarf_s29: return "s29";
+ case dwarf_s30: return "s30";
+ case dwarf_s31: return "s31";
+
+ // FPA Registers 0-7
+ case dwarf_f0: return "f0";
+ case dwarf_f1: return "f1";
+ case dwarf_f2: return "f2";
+ case dwarf_f3: return "f3";
+ case dwarf_f4: return "f4";
+ case dwarf_f5: return "f5";
+ case dwarf_f6: return "f6";
+ case dwarf_f7: return "f7";
+
+ // Intel wireless MMX general purpose registers 0–7
+ // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7)
+ case dwarf_wCGR0: return "wCGR0/ACC0";
+ case dwarf_wCGR1: return "wCGR1/ACC1";
+ case dwarf_wCGR2: return "wCGR2/ACC2";
+ case dwarf_wCGR3: return "wCGR3/ACC3";
+ case dwarf_wCGR4: return "wCGR4/ACC4";
+ case dwarf_wCGR5: return "wCGR5/ACC5";
+ case dwarf_wCGR6: return "wCGR6/ACC6";
+ case dwarf_wCGR7: return "wCGR7/ACC7";
+
+ // Intel wireless MMX data registers 0–15
+ case dwarf_wR0: return "wR0";
+ case dwarf_wR1: return "wR1";
+ case dwarf_wR2: return "wR2";
+ case dwarf_wR3: return "wR3";
+ case dwarf_wR4: return "wR4";
+ case dwarf_wR5: return "wR5";
+ case dwarf_wR6: return "wR6";
+ case dwarf_wR7: return "wR7";
+ case dwarf_wR8: return "wR8";
+ case dwarf_wR9: return "wR9";
+ case dwarf_wR10: return "wR10";
+ case dwarf_wR11: return "wR11";
+ case dwarf_wR12: return "wR12";
+ case dwarf_wR13: return "wR13";
+ case dwarf_wR14: return "wR14";
+ case dwarf_wR15: return "wR15";
+
+ case dwarf_spsr: return "spsr";
+ case dwarf_spsr_fiq: return "spsr_fiq";
+ case dwarf_spsr_irq: return "spsr_irq";
+ case dwarf_spsr_abt: return "spsr_abt";
+ case dwarf_spsr_und: return "spsr_und";
+ case dwarf_spsr_svc: return "spsr_svc";
+
+ case dwarf_r8_usr: return "r8_usr";
+ case dwarf_r9_usr: return "r9_usr";
+ case dwarf_r10_usr: return "r10_usr";
+ case dwarf_r11_usr: return "r11_usr";
+ case dwarf_r12_usr: return "r12_usr";
+ case dwarf_r13_usr: return "r13_usr";
+ case dwarf_r14_usr: return "r14_usr";
+ case dwarf_r8_fiq: return "r8_fiq";
+ case dwarf_r9_fiq: return "r9_fiq";
+ case dwarf_r10_fiq: return "r10_fiq";
+ case dwarf_r11_fiq: return "r11_fiq";
+ case dwarf_r12_fiq: return "r12_fiq";
+ case dwarf_r13_fiq: return "r13_fiq";
+ case dwarf_r14_fiq: return "r14_fiq";
+ case dwarf_r13_irq: return "r13_irq";
+ case dwarf_r14_irq: return "r14_irq";
+ case dwarf_r13_abt: return "r13_abt";
+ case dwarf_r14_abt: return "r14_abt";
+ case dwarf_r13_und: return "r13_und";
+ case dwarf_r14_und: return "r14_und";
+ case dwarf_r13_svc: return "r13_svc";
+ case dwarf_r14_svc: return "r14_svc";
+
+ // Intel wireless MMX control register in co-processor 0–7
+ case dwarf_wC0: return "wC0";
+ case dwarf_wC1: return "wC1";
+ case dwarf_wC2: return "wC2";
+ case dwarf_wC3: return "wC3";
+ case dwarf_wC4: return "wC4";
+ case dwarf_wC5: return "wC5";
+ case dwarf_wC6: return "wC6";
+ case dwarf_wC7: return "wC7";
+
+ // VFP-v3/Neon
+ case dwarf_d0: return "d0";
+ case dwarf_d1: return "d1";
+ case dwarf_d2: return "d2";
+ case dwarf_d3: return "d3";
+ case dwarf_d4: return "d4";
+ case dwarf_d5: return "d5";
+ case dwarf_d6: return "d6";
+ case dwarf_d7: return "d7";
+ case dwarf_d8: return "d8";
+ case dwarf_d9: return "d9";
+ case dwarf_d10: return "d10";
+ case dwarf_d11: return "d11";
+ case dwarf_d12: return "d12";
+ case dwarf_d13: return "d13";
+ case dwarf_d14: return "d14";
+ case dwarf_d15: return "d15";
+ case dwarf_d16: return "d16";
+ case dwarf_d17: return "d17";
+ case dwarf_d18: return "d18";
+ case dwarf_d19: return "d19";
+ case dwarf_d20: return "d20";
+ case dwarf_d21: return "d21";
+ case dwarf_d22: return "d22";
+ case dwarf_d23: return "d23";
+ case dwarf_d24: return "d24";
+ case dwarf_d25: return "d25";
+ case dwarf_d26: return "d26";
+ case dwarf_d27: return "d27";
+ case dwarf_d28: return "d28";
+ case dwarf_d29: return "d29";
+ case dwarf_d30: return "d30";
+ case dwarf_d31: return "d31";
+ }
+ return 0;
+}
+
+bool
+GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info)
+{
+ ::memset (®_info, 0, sizeof(RegisterInfo));
+ ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
+
+ if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31)
+ {
+ reg_info.byte_size = 8;
+ reg_info.format = eFormatFloat;
+ reg_info.encoding = eEncodingIEEE754;
+ }
+ else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31)
+ {
+ reg_info.byte_size = 4;
+ reg_info.format = eFormatFloat;
+ reg_info.encoding = eEncodingIEEE754;
+ }
+ else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7)
+ {
+ reg_info.byte_size = 12;
+ reg_info.format = eFormatFloat;
+ reg_info.encoding = eEncodingIEEE754;
+ }
+ else
+ {
+ reg_info.byte_size = 4;
+ reg_info.format = eFormatHex;
+ reg_info.encoding = eEncodingUint;
+ }
+
+ reg_info.kinds[eRegisterKindDWARF] = reg_num;
+
+ switch (reg_num)
+ {
+ case dwarf_r0: reg_info.name = "r0"; break;
+ case dwarf_r1: reg_info.name = "r1"; break;
+ case dwarf_r2: reg_info.name = "r2"; break;
+ case dwarf_r3: reg_info.name = "r3"; break;
+ case dwarf_r4: reg_info.name = "r4"; break;
+ case dwarf_r5: reg_info.name = "r5"; break;
+ case dwarf_r6: reg_info.name = "r6"; break;
+ case dwarf_r7: reg_info.name = "r7"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break;
+ case dwarf_r8: reg_info.name = "r8"; break;
+ case dwarf_r9: reg_info.name = "r9"; break;
+ case dwarf_r10: reg_info.name = "r10"; break;
+ case dwarf_r11: reg_info.name = "r11"; break;
+ case dwarf_r12: reg_info.name = "r12"; break;
+ case dwarf_sp: reg_info.name = "sp"; reg_info.alt_name = "r13"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break;
+ case dwarf_lr: reg_info.name = "lr"; reg_info.alt_name = "r14"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break;
+ case dwarf_pc: reg_info.name = "pc"; reg_info.alt_name = "r15"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break;
+ case dwarf_cpsr:reg_info.name = "cpsr"; reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break;
+
+ case dwarf_s0: reg_info.name = "s0"; break;
+ case dwarf_s1: reg_info.name = "s1"; break;
+ case dwarf_s2: reg_info.name = "s2"; break;
+ case dwarf_s3: reg_info.name = "s3"; break;
+ case dwarf_s4: reg_info.name = "s4"; break;
+ case dwarf_s5: reg_info.name = "s5"; break;
+ case dwarf_s6: reg_info.name = "s6"; break;
+ case dwarf_s7: reg_info.name = "s7"; break;
+ case dwarf_s8: reg_info.name = "s8"; break;
+ case dwarf_s9: reg_info.name = "s9"; break;
+ case dwarf_s10: reg_info.name = "s10"; break;
+ case dwarf_s11: reg_info.name = "s11"; break;
+ case dwarf_s12: reg_info.name = "s12"; break;
+ case dwarf_s13: reg_info.name = "s13"; break;
+ case dwarf_s14: reg_info.name = "s14"; break;
+ case dwarf_s15: reg_info.name = "s15"; break;
+ case dwarf_s16: reg_info.name = "s16"; break;
+ case dwarf_s17: reg_info.name = "s17"; break;
+ case dwarf_s18: reg_info.name = "s18"; break;
+ case dwarf_s19: reg_info.name = "s19"; break;
+ case dwarf_s20: reg_info.name = "s20"; break;
+ case dwarf_s21: reg_info.name = "s21"; break;
+ case dwarf_s22: reg_info.name = "s22"; break;
+ case dwarf_s23: reg_info.name = "s23"; break;
+ case dwarf_s24: reg_info.name = "s24"; break;
+ case dwarf_s25: reg_info.name = "s25"; break;
+ case dwarf_s26: reg_info.name = "s26"; break;
+ case dwarf_s27: reg_info.name = "s27"; break;
+ case dwarf_s28: reg_info.name = "s28"; break;
+ case dwarf_s29: reg_info.name = "s29"; break;
+ case dwarf_s30: reg_info.name = "s30"; break;
+ case dwarf_s31: reg_info.name = "s31"; break;
+
+ // FPA Registers 0-7
+ case dwarf_f0: reg_info.name = "f0"; break;
+ case dwarf_f1: reg_info.name = "f1"; break;
+ case dwarf_f2: reg_info.name = "f2"; break;
+ case dwarf_f3: reg_info.name = "f3"; break;
+ case dwarf_f4: reg_info.name = "f4"; break;
+ case dwarf_f5: reg_info.name = "f5"; break;
+ case dwarf_f6: reg_info.name = "f6"; break;
+ case dwarf_f7: reg_info.name = "f7"; break;
+
+ // Intel wireless MMX general purpose registers 0–7
+ // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7)
+ case dwarf_wCGR0: reg_info.name = "wCGR0/ACC0"; break;
+ case dwarf_wCGR1: reg_info.name = "wCGR1/ACC1"; break;
+ case dwarf_wCGR2: reg_info.name = "wCGR2/ACC2"; break;
+ case dwarf_wCGR3: reg_info.name = "wCGR3/ACC3"; break;
+ case dwarf_wCGR4: reg_info.name = "wCGR4/ACC4"; break;
+ case dwarf_wCGR5: reg_info.name = "wCGR5/ACC5"; break;
+ case dwarf_wCGR6: reg_info.name = "wCGR6/ACC6"; break;
+ case dwarf_wCGR7: reg_info.name = "wCGR7/ACC7"; break;
+
+ // Intel wireless MMX data registers 0–15
+ case dwarf_wR0: reg_info.name = "wR0"; break;
+ case dwarf_wR1: reg_info.name = "wR1"; break;
+ case dwarf_wR2: reg_info.name = "wR2"; break;
+ case dwarf_wR3: reg_info.name = "wR3"; break;
+ case dwarf_wR4: reg_info.name = "wR4"; break;
+ case dwarf_wR5: reg_info.name = "wR5"; break;
+ case dwarf_wR6: reg_info.name = "wR6"; break;
+ case dwarf_wR7: reg_info.name = "wR7"; break;
+ case dwarf_wR8: reg_info.name = "wR8"; break;
+ case dwarf_wR9: reg_info.name = "wR9"; break;
+ case dwarf_wR10: reg_info.name = "wR10"; break;
+ case dwarf_wR11: reg_info.name = "wR11"; break;
+ case dwarf_wR12: reg_info.name = "wR12"; break;
+ case dwarf_wR13: reg_info.name = "wR13"; break;
+ case dwarf_wR14: reg_info.name = "wR14"; break;
+ case dwarf_wR15: reg_info.name = "wR15"; break;
+
+ case dwarf_spsr: reg_info.name = "spsr"; break;
+ case dwarf_spsr_fiq: reg_info.name = "spsr_fiq"; break;
+ case dwarf_spsr_irq: reg_info.name = "spsr_irq"; break;
+ case dwarf_spsr_abt: reg_info.name = "spsr_abt"; break;
+ case dwarf_spsr_und: reg_info.name = "spsr_und"; break;
+ case dwarf_spsr_svc: reg_info.name = "spsr_svc"; break;
+
+ case dwarf_r8_usr: reg_info.name = "r8_usr"; break;
+ case dwarf_r9_usr: reg_info.name = "r9_usr"; break;
+ case dwarf_r10_usr: reg_info.name = "r10_usr"; break;
+ case dwarf_r11_usr: reg_info.name = "r11_usr"; break;
+ case dwarf_r12_usr: reg_info.name = "r12_usr"; break;
+ case dwarf_r13_usr: reg_info.name = "r13_usr"; break;
+ case dwarf_r14_usr: reg_info.name = "r14_usr"; break;
+ case dwarf_r8_fiq: reg_info.name = "r8_fiq"; break;
+ case dwarf_r9_fiq: reg_info.name = "r9_fiq"; break;
+ case dwarf_r10_fiq: reg_info.name = "r10_fiq"; break;
+ case dwarf_r11_fiq: reg_info.name = "r11_fiq"; break;
+ case dwarf_r12_fiq: reg_info.name = "r12_fiq"; break;
+ case dwarf_r13_fiq: reg_info.name = "r13_fiq"; break;
+ case dwarf_r14_fiq: reg_info.name = "r14_fiq"; break;
+ case dwarf_r13_irq: reg_info.name = "r13_irq"; break;
+ case dwarf_r14_irq: reg_info.name = "r14_irq"; break;
+ case dwarf_r13_abt: reg_info.name = "r13_abt"; break;
+ case dwarf_r14_abt: reg_info.name = "r14_abt"; break;
+ case dwarf_r13_und: reg_info.name = "r13_und"; break;
+ case dwarf_r14_und: reg_info.name = "r14_und"; break;
+ case dwarf_r13_svc: reg_info.name = "r13_svc"; break;
+ case dwarf_r14_svc: reg_info.name = "r14_svc"; break;
+
+ // Intel wireless MMX control register in co-processor 0–7
+ case dwarf_wC0: reg_info.name = "wC0"; break;
+ case dwarf_wC1: reg_info.name = "wC1"; break;
+ case dwarf_wC2: reg_info.name = "wC2"; break;
+ case dwarf_wC3: reg_info.name = "wC3"; break;
+ case dwarf_wC4: reg_info.name = "wC4"; break;
+ case dwarf_wC5: reg_info.name = "wC5"; break;
+ case dwarf_wC6: reg_info.name = "wC6"; break;
+ case dwarf_wC7: reg_info.name = "wC7"; break;
+
+ // VFP-v3/Neon
+ case dwarf_d0: reg_info.name = "d0"; break;
+ case dwarf_d1: reg_info.name = "d1"; break;
+ case dwarf_d2: reg_info.name = "d2"; break;
+ case dwarf_d3: reg_info.name = "d3"; break;
+ case dwarf_d4: reg_info.name = "d4"; break;
+ case dwarf_d5: reg_info.name = "d5"; break;
+ case dwarf_d6: reg_info.name = "d6"; break;
+ case dwarf_d7: reg_info.name = "d7"; break;
+ case dwarf_d8: reg_info.name = "d8"; break;
+ case dwarf_d9: reg_info.name = "d9"; break;
+ case dwarf_d10: reg_info.name = "d10"; break;
+ case dwarf_d11: reg_info.name = "d11"; break;
+ case dwarf_d12: reg_info.name = "d12"; break;
+ case dwarf_d13: reg_info.name = "d13"; break;
+ case dwarf_d14: reg_info.name = "d14"; break;
+ case dwarf_d15: reg_info.name = "d15"; break;
+ case dwarf_d16: reg_info.name = "d16"; break;
+ case dwarf_d17: reg_info.name = "d17"; break;
+ case dwarf_d18: reg_info.name = "d18"; break;
+ case dwarf_d19: reg_info.name = "d19"; break;
+ case dwarf_d20: reg_info.name = "d20"; break;
+ case dwarf_d21: reg_info.name = "d21"; break;
+ case dwarf_d22: reg_info.name = "d22"; break;
+ case dwarf_d23: reg_info.name = "d23"; break;
+ case dwarf_d24: reg_info.name = "d24"; break;
+ case dwarf_d25: reg_info.name = "d25"; break;
+ case dwarf_d26: reg_info.name = "d26"; break;
+ case dwarf_d27: reg_info.name = "d27"; break;
+ case dwarf_d28: reg_info.name = "d28"; break;
+ case dwarf_d29: reg_info.name = "d29"; break;
+ case dwarf_d30: reg_info.name = "d30"; break;
+ case dwarf_d31: reg_info.name = "d31"; break;
+ default: return false;
+ }
+ return true;
+}
diff --git a/source/Utility/ARM_DWARF_Registers.h b/source/Utility/ARM_DWARF_Registers.h
index 9c1cb91..678089d 100644
--- a/source/Utility/ARM_DWARF_Registers.h
+++ b/source/Utility/ARM_DWARF_Registers.h
@@ -10,6 +10,8 @@
#ifndef utility_ARM_DWARF_Registers_h_
#define utility_ARM_DWARF_Registers_h_
+#include "lldb/lldb-private.h"
+
enum
{
dwarf_r0 = 0,
@@ -186,16 +188,12 @@
dwarf_d31
};
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
const char *
GetARMDWARFRegisterName (unsigned reg_num);
-
-#if defined(__cplusplus)
-}
-#endif
+
+bool
+GetARMDWARFRegisterInfo (unsigned reg_num,
+ lldb_private::RegisterInfo ®_info);
#endif // utility_ARM_DWARF_Registers_h_