Add Encoding T1 entry of emulate_sub_sp_imm to the g_thumb_opcodes table.
Update emulate_sub_sp_imm to handle Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvdb/trunk@124253 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
index 99edee3..1c2739c 100644
--- a/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
+++ b/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
@@ -225,6 +225,8 @@
return false;
uint32_t imm32;
switch (encoding) {
+ case eEncodingT1:
+ imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
case eEncodingT2:
imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
break;
@@ -326,6 +328,7 @@
static ARMOpcode g_arm_opcodes[] =
{
+ // push register(s)
{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, emulate_push,
"push <registers> ; <registers> contains more than one register" },
{ 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, emulate_push,
@@ -342,7 +345,8 @@
static ARMOpcode g_thumb_opcodes[] =
{
- { 0x0000fe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push,
+ // push register(s)
+ { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push,
"push <registers>" },
{ 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push,
"push.w <registers> ; <registers> contains more than one register" },
@@ -350,6 +354,9 @@
"push.w <registers> ; <registers> contains one register, <Rt>" },
// adjust the stack pointer
+ { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, emulate_sub_sp_imm,
+ "sub{s} sp, sp, #<imm>"},
+ // adjust the stack pointer
{ 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_sub_sp_imm,
"sub{s}.w sp, sp, #<const>"},
// adjust the stack pointer