A8.6.14 ASR (register)

Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvdb/trunk@125614 91177308-0d34-0410-b5e6-96231b3b80d8
2 files changed