diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
index e118603..b85dac5 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
@@ -7,6 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include <stdlib.h>
+
 #include "EmulateInstructionARM.h"
 #include "lldb/Core/ConstString.h"
 
@@ -141,6 +143,24 @@
 {
 }
 
+// Write "bits (32) UNKNOWN" to memory address "address".  Helper function for many ARM instructions.
+bool
+EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address)
+{
+    EmulateInstruction::Context context = { EmulateInstruction::eContextWriteMemoryRandomBits, 
+                                            address, 
+                                            0, 
+                                            0 };
+
+    uint32_t random_data = rand ();
+    const uint32_t addr_byte_size = GetAddressByteSize();
+    
+    if (!WriteMemoryUnsigned (context, address, random_data, addr_byte_size))
+        return false;
+    
+    return true;
+}
+
 // Write "bits (32) UNKNOWN" to register n.  Helper function for many ARM instructions.
 bool
 EmulateInstructionARM::WriteBits32Unknown (int n)
@@ -1953,11 +1973,11 @@
                              
         if (wback && BitIsClear (registers, n))
         {
-            addr_t offset = addr_byte_size * BitCount (registers);
-            context.type = EmulateInstruction::eContextRegisterPlusOffset;
+            // R[n] = R[n] + 4 * BitCount (registers)
+            int32_t offset = addr_byte_size * BitCount (registers);
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
             context.arg2 = offset;
                 
-            // R[n] = R[n] + 4 * BitCount (registers)
             if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset))
                 return false;
         }
@@ -2069,11 +2089,14 @@
         // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); 
         if (wback && BitIsClear (registers, n))
         {
-            context.arg2 = offset;      
             addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
             if (!success)
                 return false;
-            addr = addr - (addr_byte_size * BitCount (registers));
+
+            offset = (addr_byte_size * BitCount (registers)) * -1;
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
+            context.arg2 = offset;      
+            addr = addr + offset;
             if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                 return false;
         }
@@ -2207,11 +2230,14 @@
         // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers);
         if (wback && BitIsClear (registers, n))
         {
-            context.arg2 = offset;      
             addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
             if (!success)
                 return false;
-            addr = addr - (addr_byte_size * BitCount (registers));
+            
+            offset = (addr_byte_size * BitCount (registers)) * -1;
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
+            context.arg2 = offset;
+            addr = addr + offset;
             if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                 return false;
         }
@@ -2320,11 +2346,14 @@
         // if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers);
         if (wback && BitIsClear (registers, n))
         {
-            context.arg2 = offset;      
             addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
             if (!success)
                 return false;
-            addr = addr + (addr_byte_size * BitCount (registers));
+
+            offset = addr_byte_size * BitCount (registers);
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
+            context.arg2 = offset;
+            addr = addr + offset;
             if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                 return false;
         }
@@ -2439,6 +2468,164 @@
     return true;
 }
 
+// STM stores multiple registers to consecutive memory locations using an address from a base register.  The 
+// consecutive memory locations start at this address, and teh address just above the last of those locations can 
+// optionally be written back to the base register.
+bool
+EmulateInstructionARM::EmulateSTM (ARMEncoding encoding)
+{
+#if 0
+    if ConditionPassed() then 
+        EncodingSpecificOperations(); NullCheckIfThumbEE(n); 
+        address = R[n];
+                  
+        for i = 0 to 14 
+            if registers<i> == ’1’ then
+                if i == n && wback && i != LowestSetBit(registers) then 
+                    MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
+                else 
+                    MemA[address,4] = R[i];
+                address = address + 4;
+                  
+        if registers<15> == ’1’ then // Only possible for encoding A1 
+            MemA[address,4] = PCStoreValue();
+        if wback then R[n] = R[n] + 4*BitCount(registers);
+#endif
+    
+    bool success = false;
+    const uint32_t opcode = OpcodeAsUnsigned (&success);
+    if (!success)
+        return false;
+                  
+    if (ConditionPassed ())
+    {
+        uint32_t n;
+        uint32_t registers = 0;
+        bool wback;
+        const uint32_t addr_byte_size = GetAddressByteSize();
+                  
+        // EncodingSpecificOperations(); NullCheckIfThumbEE(n); 
+        switch (encoding)
+        {
+            case eEncodingT1:
+                // n = UInt(Rn); registers = ’00000000’:register_list; wback = TRUE;
+                n = Bits32 (opcode, 10, 8);
+                registers = Bits32 (opcode, 7, 0);
+                wback = true;
+                  
+                // if BitCount(registers) < 1 then UNPREDICTABLE;
+                if (BitCount (registers) < 1)
+                    return false;
+                  
+                break;
+                  
+            case eEncodingT2:
+                // n = UInt(Rn); registers = ’0’:M:’0’:register_list; wback = (W == ’1’);
+                n = Bits32 (opcode, 19, 16);
+                registers = Bits32 (opcode, 15, 0);
+                wback = BitIsSet (opcode, 21);
+                  
+                // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
+                if ((n == 15) || (BitCount (registers) < 2))
+                    return false;
+                  
+                // if wback && registers<n> == ’1’ then UNPREDICTABLE;
+                if (wback && BitIsSet (registers, n))
+                    return false;
+                  
+                break;
+                  
+            case eEncodingA1:
+                // n = UInt(Rn); registers = register_list; wback = (W == ’1’);
+                n = Bits32 (opcode, 19, 16);
+                registers = Bits32 (opcode, 15, 0);
+                wback = BitIsSet (opcode, 21);
+                  
+                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
+                if ((n == 15) || (BitCount (registers) < 1))
+                    return false;
+                  
+                break;
+                  
+            default:
+                return false;
+        }
+        
+        // address = R[n];
+        int32_t offset = 0;
+        const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
+        if (!success)
+            return false;
+                  
+        EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterStore,
+                                                eRegisterKindDWARF, 
+                                                dwarf_r0 + n,
+                                                offset }; 
+                  
+        // for i = 0 to 14
+        for (int i = 0; i < 14; ++i)
+        {
+            int lowest_set_bit = 14;
+            // if registers<i> == ’1’ then
+            if (BitIsSet (registers, i))
+            {
+                  if (i < lowest_set_bit)
+                      lowest_set_bit = i;
+                  // if i == n && wback && i != LowestSetBit(registers) then 
+                  if ((i == n) && wback && (i != lowest_set_bit))
+                      // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
+                      WriteBits32UnknownToMemory (address + offset);
+                  else
+                  {
+                     // MemA[address,4] = R[i];
+                      uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
+                      if (!success)
+                          return false;
+                  
+                      context.arg1 = dwarf_r0 + i;
+                      context.arg2 = address + offset;
+                      if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size))
+                          return false;
+                  }
+                  
+                  // address = address + 4;
+                  offset += addr_byte_size;
+            }
+        }
+                  
+        // if registers<15> == ’1’ then // Only possible for encoding A1 
+        //     MemA[address,4] = PCStoreValue();
+        if (BitIsSet (registers, 15))
+        {
+            const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success);
+            if (!success)
+                return false;
+                  
+            context.arg1 = dwarf_pc;    // arg1 in the context is the DWARF register number
+            context.arg2 = address + offset - sp;   // arg2 in the context is the stack pointer offset
+            const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
+            if (!success)
+                return false;
+                  
+            if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size))
+                return false;
+        }
+                  
+        // if wback then R[n] = R[n] + 4*BitCount(registers);
+        if (wback)
+        {
+            offset = addr_byte_size * BitCount (registers);
+            context.type = EmulateInstruction::eContextAdjustBaseRegister;
+            context.arg1 = dwarf_r0 + n;
+            context.arg2 = offset;
+            addr_t data = address + offset;
+            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
+                return false;
+        }
+    }
+    return true;
+}
+
 EmulateInstructionARM::ARMOpcode*
 EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
 {
@@ -2501,7 +2688,12 @@
         { 0x0fd00000, 0x08900000, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
         { 0x0fd00000, 0x08100000, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" },
         { 0x0fd00000, 0x09100000, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
-        { 0x0fd00000, 0x09900000, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" }
+        { 0x0fd00000, 0x09900000, ARMvAll,       eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" },
+                  
+        //----------------------------------------------------------------------
+        // Store instructions
+        //----------------------------------------------------------------------
+        { 0x0fd00000, 0x08800000, ARMvAll,      eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }
         
     };
     static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
@@ -2612,7 +2804,13 @@
         { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
         { 0xfffff800, 0x00006800, ARMvAll,       eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
         // Thumb2 PC-relative load into register
-        { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"}
+        { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
+                  
+        //----------------------------------------------------------------------
+        // Store instructions
+        //----------------------------------------------------------------------
+        { 0xfffff800, 0x0000c000, ARMV4T_ABOVE,  eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
+        { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" }
         
     };