Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | #include "EmulateInstructionARM.h" |
Johnny Chen | 4baf2e3 | 2011-01-24 18:24:53 +0000 | [diff] [blame] | 11 | #include "ARMUtils.h" |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 12 | |
| 13 | using namespace lldb; |
| 14 | using namespace lldb_private; |
| 15 | |
| 16 | // ARM constants used during decoding |
| 17 | #define REG_RD 0 |
| 18 | #define LDM_REGLIST 1 |
| 19 | #define PC_REG 15 |
| 20 | #define PC_REGLIST_BIT 0x8000 |
| 21 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 22 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 23 | #define ARMv4T (1u << 1) |
| 24 | #define ARMv5T (1u << 2) |
| 25 | #define ARMv5TE (1u << 3) |
| 26 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 27 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 28 | #define ARMv6K (1u << 6) |
| 29 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 30 | #define ARMv7 (1u << 8) |
| 31 | #define ARMv8 (1u << 8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 32 | #define ARMvAll (0xffffffffu) |
| 33 | |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 34 | typedef enum |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 35 | { |
| 36 | eEncodingA1, |
| 37 | eEncodingA2, |
| 38 | eEncodingA3, |
| 39 | eEncodingA4, |
| 40 | eEncodingA5, |
| 41 | eEncodingT1, |
| 42 | eEncodingT2, |
| 43 | eEncodingT3, |
| 44 | eEncodingT4, |
| 45 | eEncodingT5, |
| 46 | } ARMEncoding; |
| 47 | |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 48 | typedef enum |
| 49 | { |
| 50 | eSize16, |
| 51 | eSize32 |
| 52 | } ARMInstrSize; |
| 53 | |
Johnny Chen | 4baf2e3 | 2011-01-24 18:24:53 +0000 | [diff] [blame] | 54 | // Typedef for the callback function used during the emulation. |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 55 | // Pass along (ARMEncoding)encoding as the callback data. |
| 56 | typedef bool (*EmulateCallback) (EmulateInstructionARM *emulator, ARMEncoding encoding); |
| 57 | |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 58 | typedef struct |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 59 | { |
| 60 | uint32_t mask; |
| 61 | uint32_t value; |
| 62 | uint32_t variants; |
| 63 | ARMEncoding encoding; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 64 | ARMInstrSize size; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 65 | EmulateCallback callback; |
Johnny Chen | 4bee8ce | 2011-01-22 00:59:07 +0000 | [diff] [blame] | 66 | const char *name; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 67 | } ARMOpcode; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 68 | |
| 69 | static bool |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 70 | emulate_push (EmulateInstructionARM *emulator, ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 71 | { |
| 72 | #if 0 |
| 73 | // ARM pseudo code... |
| 74 | if (ConditionPassed()) |
| 75 | { |
| 76 | EncodingSpecificOperations(); |
| 77 | NullCheckIfThumbEE(13); |
| 78 | address = SP - 4*BitCount(registers); |
| 79 | |
| 80 | for (i = 0 to 14) |
| 81 | { |
| 82 | if (registers<i> == ’1’) |
| 83 | { |
| 84 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 85 | MemA[address,4] = bits(32) UNKNOWN; |
| 86 | else |
| 87 | MemA[address,4] = R[i]; |
| 88 | address = address + 4; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | if (registers<15> == ’1’) // Only possible for encoding A1 or A2 |
| 93 | MemA[address,4] = PCStoreValue(); |
| 94 | |
| 95 | SP = SP - 4*BitCount(registers); |
| 96 | } |
| 97 | #endif |
| 98 | |
| 99 | bool success = false; |
| 100 | const uint32_t opcode = emulator->OpcodeAsUnsigned (&success); |
| 101 | if (!success) |
| 102 | return false; |
| 103 | |
| 104 | if (emulator->ConditionPassed()) |
| 105 | { |
| 106 | const uint32_t addr_byte_size = emulator->GetAddressByteSize(); |
| 107 | const addr_t sp = emulator->ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 108 | if (!success) |
| 109 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 110 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 111 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 112 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 113 | case eEncodingT1: |
| 114 | registers = EmulateInstruction::UnsignedBits (opcode, 7, 0); |
| 115 | // The M bit represents LR. |
| 116 | if (EmulateInstruction::UnsignedBits (opcode, 8, 8)) |
| 117 | registers |= 0x000eu; |
| 118 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 119 | if (BitCount(registers) < 1) |
| 120 | return false; |
| 121 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 122 | case eEncodingT2: |
| 123 | // Ignore bits 15 & 13. |
| 124 | registers = EmulateInstruction::UnsignedBits (opcode, 15, 0) & ~0xa000; |
| 125 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 126 | if (BitCount(registers) < 2) |
| 127 | return false; |
| 128 | break; |
| 129 | case eEncodingT3: |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 130 | Rt = EmulateInstruction::UnsignedBits (opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 131 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 132 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 133 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 134 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 135 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 136 | case eEncodingA1: |
| 137 | registers = EmulateInstruction::UnsignedBits (opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 138 | // Instead of return false, let's handle the following case as well, |
| 139 | // which amounts to pushing one reg onto the full descending stacks. |
| 140 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 141 | break; |
| 142 | case eEncodingA2: |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 143 | Rt = EmulateInstruction::UnsignedBits (opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 144 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 145 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 146 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 147 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 148 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 149 | default: |
| 150 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 151 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 152 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 153 | addr_t addr = sp - sp_offset; |
| 154 | uint32_t i; |
| 155 | |
| 156 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
| 157 | for (i=0; i<15; ++i) |
| 158 | { |
| 159 | if (EmulateInstruction::BitIsSet (registers, 1u << i)) |
| 160 | { |
| 161 | context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number |
| 162 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 163 | uint32_t reg_value = emulator->ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
| 164 | if (!success) |
| 165 | return false; |
| 166 | if (!emulator->WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
| 167 | return false; |
| 168 | addr += addr_byte_size; |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | if (EmulateInstruction::BitIsSet (registers, 1u << 15)) |
| 173 | { |
| 174 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 175 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 176 | const uint32_t pc = emulator->ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 177 | if (!success) |
| 178 | return false; |
| 179 | if (!emulator->WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
| 180 | return false; |
| 181 | } |
| 182 | |
| 183 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 184 | context.arg0 = eRegisterKindGeneric; |
| 185 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 186 | context.arg2 = sp_offset; |
| 187 | |
| 188 | if (!emulator->WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
| 189 | return false; |
| 190 | } |
| 191 | return true; |
| 192 | } |
| 193 | |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 194 | // A store operation to the SP that also updates the SP. |
| 195 | static bool |
| 196 | emulate_str_rt_sp (EmulateInstructionARM *emulator, ARMEncoding encoding) |
| 197 | { |
| 198 | #if 0 |
| 199 | // ARM pseudo code... |
| 200 | if (ConditionPassed()) |
| 201 | { |
| 202 | EncodingSpecificOperations(); |
| 203 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 204 | address = if index then offset_addr else R[n]; |
| 205 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 206 | if wback then R[n] = offset_addr; |
| 207 | } |
| 208 | #endif |
| 209 | |
| 210 | bool success = false; |
| 211 | const uint32_t opcode = emulator->OpcodeAsUnsigned (&success); |
| 212 | if (!success) |
| 213 | return false; |
| 214 | |
| 215 | if (emulator->ConditionPassed()) |
| 216 | { |
| 217 | const uint32_t addr_byte_size = emulator->GetAddressByteSize(); |
| 218 | const addr_t sp = emulator->ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 219 | if (!success) |
| 220 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 221 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 222 | uint32_t imm12; |
| 223 | switch (encoding) { |
| 224 | case eEncodingA1: |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 225 | Rt = EmulateInstruction::UnsignedBits (opcode, 15, 12); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 226 | imm12 = EmulateInstruction::UnsignedBits (opcode, 11, 0); |
| 227 | break; |
| 228 | default: |
| 229 | return false; |
| 230 | } |
| 231 | addr_t sp_offset = imm12; |
| 232 | addr_t addr = sp - sp_offset; |
| 233 | |
| 234 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 235 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 236 | { |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 237 | context.arg1 = dwarf_r0 + Rt; // arg1 in the context is the DWARF register number |
| 238 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 239 | uint32_t reg_value = emulator->ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
| 240 | if (!success) |
| 241 | return false; |
| 242 | if (!emulator->WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
| 243 | return false; |
| 244 | } |
| 245 | else |
| 246 | { |
| 247 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 248 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 249 | const uint32_t pc = emulator->ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 250 | if (!success) |
| 251 | return false; |
| 252 | if (!emulator->WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
| 253 | return false; |
| 254 | } |
| 255 | |
| 256 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 257 | context.arg0 = eRegisterKindGeneric; |
| 258 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 259 | context.arg2 = sp_offset; |
| 260 | |
| 261 | if (!emulator->WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
| 262 | return false; |
| 263 | } |
| 264 | return true; |
| 265 | } |
| 266 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 267 | static ARMOpcode g_arm_opcodes[] = |
| 268 | { |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 269 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, emulate_push, |
Johnny Chen | d6873ed | 2011-01-24 22:02:46 +0000 | [diff] [blame] | 270 | "push<c> <registers> ; <registers> contains more than one register" }, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 271 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, emulate_push, |
| 272 | "push<c> <registers> ; <registers> contains one register, <Rt>" }, |
| 273 | |
| 274 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
| 275 | { 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, emulate_str_rt_sp, |
| 276 | "str<c><q> Rt, [sp, #-n]!" } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 277 | }; |
| 278 | |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 279 | static ARMOpcode g_thumb_opcodes[] = |
| 280 | { |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 281 | { 0x0000fe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push, |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 282 | "push<c> <registers>" }, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 283 | { 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push, |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 284 | "push<c>.w <registers> ; <registers> contains more than one register" }, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 285 | { 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, emulate_push, |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 286 | "push<c>.w <registers> ; <registers> contains one register, <Rt>" } |
| 287 | }; |
| 288 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 289 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 290 | static const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 291 | |
| 292 | bool |
| 293 | EmulateInstructionARM::ReadInstruction () |
| 294 | { |
| 295 | bool success = false; |
| 296 | m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
| 297 | if (success) |
| 298 | { |
| 299 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 300 | if (success) |
| 301 | { |
| 302 | Context read_inst_context = {eContextReadOpcode, 0, 0}; |
| 303 | if (m_inst_cpsr & MASK_CPSR_T) |
| 304 | { |
| 305 | m_inst_mode = eModeThumb; |
| 306 | uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success); |
| 307 | |
| 308 | if (success) |
| 309 | { |
| 310 | if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0)) |
| 311 | { |
| 312 | m_inst.opcode_type = eOpcode16; |
| 313 | m_inst.opcode.inst16 = thumb_opcode; |
| 314 | } |
| 315 | else |
| 316 | { |
| 317 | m_inst.opcode_type = eOpcode32; |
| 318 | m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success); |
| 319 | } |
| 320 | } |
| 321 | } |
| 322 | else |
| 323 | { |
| 324 | m_inst_mode = eModeARM; |
| 325 | m_inst.opcode_type = eOpcode32; |
| 326 | m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success); |
| 327 | } |
| 328 | } |
| 329 | } |
| 330 | if (!success) |
| 331 | { |
| 332 | m_inst_mode = eModeInvalid; |
| 333 | m_inst_pc = LLDB_INVALID_ADDRESS; |
| 334 | } |
| 335 | return success; |
| 336 | } |
| 337 | |
| 338 | uint32_t |
| 339 | EmulateInstructionARM::CurrentCond () |
| 340 | { |
| 341 | switch (m_inst_mode) |
| 342 | { |
| 343 | default: |
| 344 | case eModeInvalid: |
| 345 | break; |
| 346 | |
| 347 | case eModeARM: |
| 348 | return UnsignedBits(m_inst.opcode.inst32, 31, 28); |
| 349 | |
| 350 | case eModeThumb: |
| 351 | return 0x0000000Eu; // Return always for now, we need to handl IT instructions later |
| 352 | } |
| 353 | return UINT32_MAX; // Return invalid value |
| 354 | } |
| 355 | bool |
| 356 | EmulateInstructionARM::ConditionPassed () |
| 357 | { |
| 358 | if (m_inst_cpsr == 0) |
| 359 | return false; |
| 360 | |
| 361 | const uint32_t cond = CurrentCond (); |
| 362 | |
| 363 | if (cond == UINT32_MAX) |
| 364 | return false; |
| 365 | |
| 366 | bool result = false; |
| 367 | switch (UnsignedBits(cond, 3, 1)) |
| 368 | { |
| 369 | case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break; |
| 370 | case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break; |
| 371 | case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break; |
| 372 | case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break; |
| 373 | case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break; |
| 374 | case 5: |
| 375 | { |
| 376 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 377 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 378 | result = n == v; |
| 379 | } |
| 380 | break; |
| 381 | case 6: |
| 382 | { |
| 383 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 384 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 385 | result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0); |
| 386 | } |
| 387 | break; |
| 388 | case 7: |
| 389 | result = true; |
| 390 | break; |
| 391 | } |
| 392 | |
| 393 | if (cond & 1) |
| 394 | result = !result; |
| 395 | return result; |
| 396 | } |
| 397 | |
| 398 | |
| 399 | bool |
| 400 | EmulateInstructionARM::EvaluateInstruction () |
| 401 | { |
| 402 | return false; |
| 403 | } |