Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10 | #include <stdlib.h> |
| 11 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 12 | #include "EmulateInstructionARM.h" |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 13 | #include "lldb/Core/ArchSpec.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 14 | #include "lldb/Core/ConstString.h" |
| 15 | |
Greg Clayton | f29a08f | 2011-02-09 17:41:27 +0000 | [diff] [blame] | 16 | #include "Plugins/Process/Utility/ARMDefines.h" |
| 17 | #include "Plugins/Process/Utility/ARMUtils.h" |
| 18 | #include "Utility/ARM_DWARF_Registers.h" |
| 19 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 20 | #include "llvm/Support/MathExtras.h" // for SignExtend32 template function |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 21 | // and CountTrailingZeros_32 function |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace lldb; |
| 24 | using namespace lldb_private; |
| 25 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 26 | // Convenient macro definitions. |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 27 | #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS) |
| 28 | #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS) |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 29 | |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 30 | #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) |
| 31 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 32 | //---------------------------------------------------------------------- |
| 33 | // |
| 34 | // ITSession implementation |
| 35 | // |
| 36 | //---------------------------------------------------------------------- |
| 37 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 38 | // A8.6.50 |
| 39 | // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. |
| 40 | static unsigned short CountITSize(unsigned ITMask) { |
| 41 | // First count the trailing zeros of the IT mask. |
| 42 | unsigned TZ = llvm::CountTrailingZeros_32(ITMask); |
| 43 | if (TZ > 3) |
| 44 | { |
| 45 | printf("Encoding error: IT Mask '0000'\n"); |
| 46 | return 0; |
| 47 | } |
| 48 | return (4 - TZ); |
| 49 | } |
| 50 | |
| 51 | // Init ITState. Note that at least one bit is always 1 in mask. |
| 52 | bool ITSession::InitIT(unsigned short bits7_0) |
| 53 | { |
| 54 | ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); |
| 55 | if (ITCounter == 0) |
| 56 | return false; |
| 57 | |
| 58 | // A8.6.50 IT |
| 59 | unsigned short FirstCond = Bits32(bits7_0, 7, 4); |
| 60 | if (FirstCond == 0xF) |
| 61 | { |
| 62 | printf("Encoding error: IT FirstCond '1111'\n"); |
| 63 | return false; |
| 64 | } |
| 65 | if (FirstCond == 0xE && ITCounter != 1) |
| 66 | { |
| 67 | printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n"); |
| 68 | return false; |
| 69 | } |
| 70 | |
| 71 | ITState = bits7_0; |
| 72 | return true; |
| 73 | } |
| 74 | |
| 75 | // Update ITState if necessary. |
| 76 | void ITSession::ITAdvance() |
| 77 | { |
| 78 | assert(ITCounter); |
| 79 | --ITCounter; |
| 80 | if (ITCounter == 0) |
| 81 | ITState = 0; |
| 82 | else |
| 83 | { |
| 84 | unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; |
| 85 | SetBits32(ITState, 4, 0, NewITState4_0); |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | // Return true if we're inside an IT Block. |
| 90 | bool ITSession::InITBlock() |
| 91 | { |
| 92 | return ITCounter != 0; |
| 93 | } |
| 94 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 95 | // Return true if we're the last instruction inside an IT Block. |
| 96 | bool ITSession::LastInITBlock() |
| 97 | { |
| 98 | return ITCounter == 1; |
| 99 | } |
| 100 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 101 | // Get condition bits for the current thumb instruction. |
| 102 | uint32_t ITSession::GetCond() |
| 103 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 104 | if (InITBlock()) |
| 105 | return Bits32(ITState, 7, 4); |
| 106 | else |
| 107 | return COND_AL; |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 108 | } |
| 109 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 110 | // ARM constants used during decoding |
| 111 | #define REG_RD 0 |
| 112 | #define LDM_REGLIST 1 |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 113 | #define SP_REG 13 |
| 114 | #define LR_REG 14 |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 115 | #define PC_REG 15 |
| 116 | #define PC_REGLIST_BIT 0x8000 |
| 117 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 118 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 119 | #define ARMv4T (1u << 1) |
| 120 | #define ARMv5T (1u << 2) |
| 121 | #define ARMv5TE (1u << 3) |
| 122 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 123 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 124 | #define ARMv6K (1u << 6) |
| 125 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 126 | #define ARMv7 (1u << 8) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 127 | #define ARMv8 (1u << 9) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 128 | #define ARMvAll (0xffffffffu) |
| 129 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 130 | #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 131 | #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 132 | #define ARMV5TE_ABOVE (ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 133 | #define ARMV5J_ABOVE (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 134 | #define ARMV6_ABOVE (ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 135 | #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 136 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 137 | //---------------------------------------------------------------------- |
| 138 | // |
| 139 | // EmulateInstructionARM implementation |
| 140 | // |
| 141 | //---------------------------------------------------------------------- |
| 142 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 143 | void |
| 144 | EmulateInstructionARM::Initialize () |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 145 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 146 | } |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 147 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 148 | void |
| 149 | EmulateInstructionARM::Terminate () |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 150 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 151 | } |
| 152 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 153 | // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions. |
| 154 | bool |
| 155 | EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address) |
| 156 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 157 | EmulateInstruction::Context context; |
| 158 | context.type = EmulateInstruction::eContextWriteMemoryRandomBits; |
| 159 | context.SetNoArgs (); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 160 | |
| 161 | uint32_t random_data = rand (); |
| 162 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 163 | |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 164 | if (!MemAWrite (context, address, random_data, addr_byte_size)) |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 165 | return false; |
| 166 | |
| 167 | return true; |
| 168 | } |
| 169 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 170 | // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions. |
| 171 | bool |
| 172 | EmulateInstructionARM::WriteBits32Unknown (int n) |
| 173 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 174 | EmulateInstruction::Context context; |
| 175 | context.type = EmulateInstruction::eContextWriteRegisterRandomBits; |
| 176 | context.SetNoArgs (); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 177 | |
Johnny Chen | 62ff6f5 | 2011-02-11 18:11:22 +0000 | [diff] [blame] | 178 | bool success; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 179 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 180 | |
| 181 | if (!success) |
| 182 | return false; |
| 183 | |
| 184 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 185 | return false; |
| 186 | |
| 187 | return true; |
| 188 | } |
| 189 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 190 | // Push Multiple Registers stores multiple registers to the stack, storing to |
| 191 | // consecutive memory locations ending just below the address in SP, and updates |
| 192 | // SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 193 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 194 | EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 195 | { |
| 196 | #if 0 |
| 197 | // ARM pseudo code... |
| 198 | if (ConditionPassed()) |
| 199 | { |
| 200 | EncodingSpecificOperations(); |
| 201 | NullCheckIfThumbEE(13); |
| 202 | address = SP - 4*BitCount(registers); |
| 203 | |
| 204 | for (i = 0 to 14) |
| 205 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 206 | if (registers<i> == '1') |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 207 | { |
| 208 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 209 | MemA[address,4] = bits(32) UNKNOWN; |
| 210 | else |
| 211 | MemA[address,4] = R[i]; |
| 212 | address = address + 4; |
| 213 | } |
| 214 | } |
| 215 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 216 | if (registers<15> == '1') // Only possible for encoding A1 or A2 |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 217 | MemA[address,4] = PCStoreValue(); |
| 218 | |
| 219 | SP = SP - 4*BitCount(registers); |
| 220 | } |
| 221 | #endif |
| 222 | |
| 223 | bool success = false; |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 224 | if (ConditionPassed(opcode)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 225 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 226 | const uint32_t addr_byte_size = GetAddressByteSize(); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 227 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 228 | if (!success) |
| 229 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 230 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 231 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 232 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 233 | case eEncodingT1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 234 | registers = Bits32(opcode, 7, 0); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 235 | // The M bit represents LR. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 236 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 237 | registers |= (1u << 14); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 238 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 239 | if (BitCount(registers) < 1) |
| 240 | return false; |
| 241 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 242 | case eEncodingT2: |
| 243 | // Ignore bits 15 & 13. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 244 | registers = Bits32(opcode, 15, 0) & ~0xa000; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 245 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 246 | if (BitCount(registers) < 2) |
| 247 | return false; |
| 248 | break; |
| 249 | case eEncodingT3: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 250 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 251 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 252 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 253 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 254 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 255 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 256 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 257 | registers = Bits32(opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 258 | // Instead of return false, let's handle the following case as well, |
| 259 | // which amounts to pushing one reg onto the full descending stacks. |
| 260 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 261 | break; |
| 262 | case eEncodingA2: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 263 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 264 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 265 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 266 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 267 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 268 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 269 | default: |
| 270 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 271 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 272 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 273 | addr_t addr = sp - sp_offset; |
| 274 | uint32_t i; |
| 275 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 276 | EmulateInstruction::Context context; |
| 277 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 278 | Register dwarf_reg; |
| 279 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 280 | Register sp_reg; |
| 281 | sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 282 | for (i=0; i<15; ++i) |
| 283 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 284 | if (BitIsSet (registers, i)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 285 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 286 | dwarf_reg.num = dwarf_r0 + i; |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 287 | context.SetRegisterToRegisterPlusOffset (dwarf_reg, sp_reg, addr - sp); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 288 | uint32_t reg_value = ReadCoreReg(i, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 289 | if (!success) |
| 290 | return false; |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 291 | if (!MemAWrite (context, addr, reg_value, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 292 | return false; |
| 293 | addr += addr_byte_size; |
| 294 | } |
| 295 | } |
| 296 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 297 | if (BitIsSet (registers, 15)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 298 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 299 | dwarf_reg.num = dwarf_pc; |
| 300 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 301 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 302 | if (!success) |
| 303 | return false; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 304 | if (!MemAWrite (context, addr, pc, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 305 | return false; |
| 306 | } |
| 307 | |
| 308 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 309 | context.SetImmediateSigned (-sp_offset); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 310 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 311 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 312 | return false; |
| 313 | } |
| 314 | return true; |
| 315 | } |
| 316 | |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 317 | // Pop Multiple Registers loads multiple registers from the stack, loading from |
| 318 | // consecutive memory locations staring at the address in SP, and updates |
| 319 | // SP to point just above the loaded data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 320 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 321 | EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 322 | { |
| 323 | #if 0 |
| 324 | // ARM pseudo code... |
| 325 | if (ConditionPassed()) |
| 326 | { |
| 327 | EncodingSpecificOperations(); NullCheckIfThumbEE(13); |
| 328 | address = SP; |
| 329 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 330 | if registers<i> == '1' then |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 331 | R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 332 | if registers<15> == '1' then |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 333 | if UnalignedAllowed then |
| 334 | LoadWritePC(MemU[address,4]); |
| 335 | else |
| 336 | LoadWritePC(MemA[address,4]); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 337 | if registers<13> == '0' then SP = SP + 4*BitCount(registers); |
| 338 | if registers<13> == '1' then SP = bits(32) UNKNOWN; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 339 | } |
| 340 | #endif |
| 341 | |
| 342 | bool success = false; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 343 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 344 | if (ConditionPassed(opcode)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 345 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 346 | const uint32_t addr_byte_size = GetAddressByteSize(); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 347 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 348 | if (!success) |
| 349 | return false; |
| 350 | uint32_t registers = 0; |
| 351 | uint32_t Rt; // the destination register |
| 352 | switch (encoding) { |
| 353 | case eEncodingT1: |
| 354 | registers = Bits32(opcode, 7, 0); |
| 355 | // The P bit represents PC. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 356 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 357 | registers |= (1u << 15); |
| 358 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 359 | if (BitCount(registers) < 1) |
| 360 | return false; |
| 361 | break; |
| 362 | case eEncodingT2: |
| 363 | // Ignore bit 13. |
| 364 | registers = Bits32(opcode, 15, 0) & ~0x2000; |
| 365 | // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 366 | if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 367 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 368 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 369 | if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock()) |
| 370 | return false; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 371 | break; |
| 372 | case eEncodingT3: |
| 373 | Rt = Bits32(opcode, 15, 12); |
| 374 | // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 375 | if (Rt == 13) |
| 376 | return false; |
| 377 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 378 | return false; |
| 379 | registers = (1u << Rt); |
| 380 | break; |
| 381 | case eEncodingA1: |
| 382 | registers = Bits32(opcode, 15, 0); |
| 383 | // Instead of return false, let's handle the following case as well, |
| 384 | // which amounts to popping one reg from the full descending stacks. |
| 385 | // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; |
| 386 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 387 | // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 388 | if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 389 | return false; |
| 390 | break; |
| 391 | case eEncodingA2: |
| 392 | Rt = Bits32(opcode, 15, 12); |
| 393 | // if t == 13 then UNPREDICTABLE; |
| 394 | if (Rt == dwarf_sp) |
| 395 | return false; |
| 396 | registers = (1u << Rt); |
| 397 | break; |
| 398 | default: |
| 399 | return false; |
| 400 | } |
| 401 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
| 402 | addr_t addr = sp; |
| 403 | uint32_t i, data; |
| 404 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 405 | EmulateInstruction::Context context; |
| 406 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 407 | Register dwarf_reg; |
| 408 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 409 | Register sp_reg; |
| 410 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 411 | for (i=0; i<15; ++i) |
| 412 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 413 | if (BitIsSet (registers, i)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 414 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 415 | dwarf_reg.num = dwarf_r0 + i; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 416 | context.SetRegisterPlusOffset (sp_reg, addr - sp); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 417 | data = MemARead(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 418 | if (!success) |
| 419 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 420 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 421 | return false; |
| 422 | addr += addr_byte_size; |
| 423 | } |
| 424 | } |
| 425 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 426 | if (BitIsSet (registers, 15)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 427 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 428 | dwarf_reg.num = dwarf_pc; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 429 | context.SetRegisterPlusOffset (sp_reg, addr - sp); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 430 | data = MemARead(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 431 | if (!success) |
| 432 | return false; |
Johnny Chen | f3eaacf | 2011-02-09 19:30:49 +0000 | [diff] [blame] | 433 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 434 | if (!LoadWritePC(context, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 435 | return false; |
| 436 | addr += addr_byte_size; |
| 437 | } |
| 438 | |
| 439 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 440 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 441 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 442 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 443 | return false; |
| 444 | } |
| 445 | return true; |
| 446 | } |
| 447 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 448 | // Set r7 or ip to point to saved value residing within the stack. |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 449 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 450 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 451 | EmulateInstructionARM::EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 452 | { |
| 453 | #if 0 |
| 454 | // ARM pseudo code... |
| 455 | if (ConditionPassed()) |
| 456 | { |
| 457 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 458 | (result, carry, overflow) = AddWithCarry(SP, imm32, '0'); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 459 | if d == 15 then |
| 460 | ALUWritePC(result); // setflags is always FALSE here |
| 461 | else |
| 462 | R[d] = result; |
| 463 | if setflags then |
| 464 | APSR.N = result<31>; |
| 465 | APSR.Z = IsZeroBit(result); |
| 466 | APSR.C = carry; |
| 467 | APSR.V = overflow; |
| 468 | } |
| 469 | #endif |
| 470 | |
| 471 | bool success = false; |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 472 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 473 | if (ConditionPassed(opcode)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 474 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 475 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 476 | if (!success) |
| 477 | return false; |
| 478 | uint32_t Rd; // the destination register |
| 479 | uint32_t imm32; |
| 480 | switch (encoding) { |
| 481 | case eEncodingT1: |
| 482 | Rd = 7; |
| 483 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) |
| 484 | break; |
| 485 | case eEncodingA1: |
| 486 | Rd = Bits32(opcode, 15, 12); |
| 487 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 488 | break; |
| 489 | default: |
| 490 | return false; |
| 491 | } |
| 492 | addr_t sp_offset = imm32; |
| 493 | addr_t addr = sp + sp_offset; // a pointer to the stack area |
| 494 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 495 | EmulateInstruction::Context context; |
| 496 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 497 | Register sp_reg; |
| 498 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 499 | context.SetRegisterPlusOffset (sp_reg, sp_offset); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 500 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 501 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 502 | return false; |
| 503 | } |
| 504 | return true; |
| 505 | } |
| 506 | |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 507 | // Set r7 or ip to the current stack pointer. |
| 508 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 509 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 510 | EmulateInstructionARM::EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 511 | { |
| 512 | #if 0 |
| 513 | // ARM pseudo code... |
| 514 | if (ConditionPassed()) |
| 515 | { |
| 516 | EncodingSpecificOperations(); |
| 517 | result = R[m]; |
| 518 | if d == 15 then |
| 519 | ALUWritePC(result); // setflags is always FALSE here |
| 520 | else |
| 521 | R[d] = result; |
| 522 | if setflags then |
| 523 | APSR.N = result<31>; |
| 524 | APSR.Z = IsZeroBit(result); |
| 525 | // APSR.C unchanged |
| 526 | // APSR.V unchanged |
| 527 | } |
| 528 | #endif |
| 529 | |
| 530 | bool success = false; |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 531 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 532 | if (ConditionPassed(opcode)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 533 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 534 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 535 | if (!success) |
| 536 | return false; |
| 537 | uint32_t Rd; // the destination register |
| 538 | switch (encoding) { |
| 539 | case eEncodingT1: |
| 540 | Rd = 7; |
| 541 | break; |
| 542 | case eEncodingA1: |
| 543 | Rd = 12; |
| 544 | break; |
| 545 | default: |
| 546 | return false; |
| 547 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 548 | |
| 549 | EmulateInstruction::Context context; |
| 550 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 551 | Register sp_reg; |
| 552 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 553 | context.SetRegisterPlusOffset (sp_reg, 0); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 554 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 555 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 556 | return false; |
| 557 | } |
| 558 | return true; |
| 559 | } |
| 560 | |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 561 | // Move from high register (r8-r15) to low register (r0-r7). |
| 562 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 563 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 564 | EmulateInstructionARM::EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 565 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 566 | return EmulateMOVRdRm (opcode, encoding); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | // Move from register to register. |
| 570 | // MOV (register) |
| 571 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 572 | EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 573 | { |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 574 | #if 0 |
| 575 | // ARM pseudo code... |
| 576 | if (ConditionPassed()) |
| 577 | { |
| 578 | EncodingSpecificOperations(); |
| 579 | result = R[m]; |
| 580 | if d == 15 then |
| 581 | ALUWritePC(result); // setflags is always FALSE here |
| 582 | else |
| 583 | R[d] = result; |
| 584 | if setflags then |
| 585 | APSR.N = result<31>; |
| 586 | APSR.Z = IsZeroBit(result); |
| 587 | // APSR.C unchanged |
| 588 | // APSR.V unchanged |
| 589 | } |
| 590 | #endif |
| 591 | |
| 592 | bool success = false; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 593 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 594 | if (ConditionPassed(opcode)) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 595 | { |
| 596 | uint32_t Rm; // the source register |
| 597 | uint32_t Rd; // the destination register |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 598 | bool setflags; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 599 | switch (encoding) { |
| 600 | case eEncodingT1: |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 601 | Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 602 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 603 | setflags = false; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 604 | if (Rd == 15 && InITBlock() && !LastInITBlock()) |
| 605 | return false; |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 606 | break; |
| 607 | case eEncodingT2: |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 608 | Rd = Bits32(opcode, 2, 0); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 609 | Rm = Bits32(opcode, 5, 3); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 610 | setflags = true; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 611 | if (InITBlock()) |
| 612 | return false; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 613 | break; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 614 | case eEncodingT3: |
| 615 | Rd = Bits32(opcode, 11, 8); |
| 616 | Rm = Bits32(opcode, 3, 0); |
| 617 | setflags = BitIsSet(opcode, 20); |
| 618 | // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE; |
| 619 | if (setflags && (BadReg(Rd) || BadReg(Rm))) |
| 620 | return false; |
| 621 | // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE; |
| 622 | if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) |
| 623 | return false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 624 | break; |
Johnny Chen | 01d6157 | 2011-02-25 00:23:25 +0000 | [diff] [blame] | 625 | case eEncodingA1: |
| 626 | Rd = Bits32(opcode, 15, 12); |
| 627 | Rm = Bits32(opcode, 3, 0); |
| 628 | setflags = BitIsSet(opcode, 20); |
| 629 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 630 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 631 | if (Rd == 15 && setflags) |
| 632 | return false; |
| 633 | break; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 634 | default: |
| 635 | return false; |
| 636 | } |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 637 | uint32_t result = ReadCoreReg(Rm, &success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 638 | if (!success) |
| 639 | return false; |
| 640 | |
| 641 | // The context specifies that Rm is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 642 | EmulateInstruction::Context context; |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 643 | context.type = EmulateInstruction::eContextRegisterLoad; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 644 | Register dwarf_reg; |
| 645 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 646 | context.SetRegister (dwarf_reg); |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 647 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 648 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 649 | return false; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 650 | } |
| 651 | return true; |
| 652 | } |
| 653 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 654 | // Move (immediate) writes an immediate value to the destination register. It |
| 655 | // can optionally update the condition flags based on the value. |
| 656 | // MOV (immediate) |
| 657 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 658 | EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 659 | { |
| 660 | #if 0 |
| 661 | // ARM pseudo code... |
| 662 | if (ConditionPassed()) |
| 663 | { |
| 664 | EncodingSpecificOperations(); |
| 665 | result = imm32; |
| 666 | if d == 15 then // Can only occur for ARM encoding |
| 667 | ALUWritePC(result); // setflags is always FALSE here |
| 668 | else |
| 669 | R[d] = result; |
| 670 | if setflags then |
| 671 | APSR.N = result<31>; |
| 672 | APSR.Z = IsZeroBit(result); |
| 673 | APSR.C = carry; |
| 674 | // APSR.V unchanged |
| 675 | } |
| 676 | #endif |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 677 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 678 | if (ConditionPassed(opcode)) |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 679 | { |
| 680 | uint32_t Rd; // the destination register |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 681 | uint32_t imm32; // the immediate value to be written to Rd |
| 682 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C. |
| 683 | bool setflags; |
| 684 | switch (encoding) { |
Caroline Tice | 89c6d58 | 2011-03-29 19:53:44 +0000 | [diff] [blame] | 685 | case eEncodingT1: |
| 686 | Rd = Bits32(opcode, 10, 8); |
| 687 | setflags = !InITBlock(); |
| 688 | imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) |
| 689 | carry = APSR_C; |
| 690 | |
| 691 | break; |
| 692 | |
| 693 | case eEncodingT2: |
| 694 | Rd = Bits32(opcode, 11, 8); |
| 695 | setflags = BitIsSet(opcode, 20); |
| 696 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); |
| 697 | if (BadReg(Rd)) |
| 698 | return false; |
| 699 | |
| 700 | break; |
| 701 | |
| 702 | case eEncodingT3: |
| 703 | { |
| 704 | // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32); |
| 705 | Rd = Bits32 (opcode, 11, 8); |
| 706 | setflags = false; |
| 707 | uint32_t imm4 = Bits32 (opcode, 19, 16); |
| 708 | uint32_t imm3 = Bits32 (opcode, 14, 12); |
| 709 | uint32_t i = Bit32 (opcode, 26); |
| 710 | uint32_t imm8 = Bits32 (opcode, 7, 0); |
| 711 | imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; |
| 712 | |
| 713 | // if BadReg(d) then UNPREDICTABLE; |
| 714 | if (BadReg (Rd)) |
| 715 | return false; |
| 716 | } |
| 717 | break; |
| 718 | |
| 719 | case eEncodingA1: |
| 720 | // if Rd == ‘1111’ && S == ‘1’ then SEE SUBS PC, LR and related instructions; |
| 721 | // d = UInt(Rd); setflags = (S == ‘1’); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C); |
| 722 | Rd = Bits32 (opcode, 15, 12); |
| 723 | setflags = BitIsSet (opcode, 20); |
| 724 | imm32 = ARMExpandImm_C (opcode, APSR_C, carry); |
| 725 | |
| 726 | break; |
| 727 | |
| 728 | case eEncodingA2: |
| 729 | { |
| 730 | // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32); |
| 731 | Rd = Bits32 (opcode, 15, 12); |
| 732 | setflags = false; |
| 733 | uint32_t imm4 = Bits32 (opcode, 19, 16); |
| 734 | uint32_t imm12 = Bits32 (opcode, 11, 0); |
| 735 | imm32 = (imm4 << 12) | imm12; |
| 736 | |
| 737 | // if d == 15 then UNPREDICTABLE; |
| 738 | if (Rd == 15) |
| 739 | return false; |
| 740 | } |
| 741 | break; |
| 742 | |
| 743 | default: |
Johnny Chen | 9798cfc | 2011-02-14 23:33:58 +0000 | [diff] [blame] | 744 | return false; |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 745 | } |
| 746 | uint32_t result = imm32; |
| 747 | |
| 748 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 749 | EmulateInstruction::Context context; |
| 750 | context.type = EmulateInstruction::eContextImmediate; |
| 751 | context.SetNoArgs (); |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 752 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 753 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 754 | return false; |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 755 | } |
| 756 | return true; |
| 757 | } |
| 758 | |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 759 | // MUL multiplies two register values. The least significant 32 bits of the result are written to the destination |
| 760 | // register. These 32 bits do not depend on whether the source register values are considered to be signed values or |
| 761 | // unsigned values. |
| 762 | // |
| 763 | // Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is |
| 764 | // limited to only a few forms of the instruction. |
| 765 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 766 | EmulateInstructionARM::EmulateMUL (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 767 | { |
| 768 | #if 0 |
| 769 | if ConditionPassed() then |
| 770 | EncodingSpecificOperations(); |
| 771 | operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results |
| 772 | operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results |
| 773 | result = operand1 * operand2; |
| 774 | R[d] = result<31:0>; |
| 775 | if setflags then |
| 776 | APSR.N = result<31>; |
| 777 | APSR.Z = IsZeroBit(result); |
| 778 | if ArchVersion() == 4 then |
| 779 | APSR.C = bit UNKNOWN; |
| 780 | // else APSR.C unchanged |
| 781 | // APSR.V always unchanged |
| 782 | #endif |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 783 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 784 | if (ConditionPassed(opcode)) |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 785 | { |
| 786 | uint32_t d; |
| 787 | uint32_t n; |
| 788 | uint32_t m; |
| 789 | bool setflags; |
| 790 | |
| 791 | // EncodingSpecificOperations(); |
| 792 | switch (encoding) |
| 793 | { |
| 794 | case eEncodingT1: |
| 795 | // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock(); |
| 796 | d = Bits32 (opcode, 2, 0); |
| 797 | n = Bits32 (opcode, 5, 3); |
| 798 | m = Bits32 (opcode, 2, 0); |
| 799 | setflags = !InITBlock(); |
| 800 | |
| 801 | // if ArchVersion() < 6 && d == n then UNPREDICTABLE; |
| 802 | if ((ArchVersion() < ARMv6) && (d == n)) |
| 803 | return false; |
| 804 | |
| 805 | break; |
| 806 | |
| 807 | case eEncodingT2: |
| 808 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE; |
| 809 | d = Bits32 (opcode, 11, 8); |
| 810 | n = Bits32 (opcode, 19, 16); |
| 811 | m = Bits32 (opcode, 3, 0); |
| 812 | setflags = false; |
| 813 | |
| 814 | // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE; |
| 815 | if (BadReg (d) || BadReg (n) || BadReg (m)) |
| 816 | return false; |
| 817 | |
| 818 | break; |
| 819 | |
| 820 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 821 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1'); |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 822 | d = Bits32 (opcode, 19, 16); |
| 823 | n = Bits32 (opcode, 3, 0); |
| 824 | m = Bits32 (opcode, 11, 8); |
| 825 | setflags = BitIsSet (opcode, 20); |
| 826 | |
| 827 | // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; |
| 828 | if ((d == 15) || (n == 15) || (m == 15)) |
| 829 | return false; |
| 830 | |
| 831 | // if ArchVersion() < 6 && d == n then UNPREDICTABLE; |
| 832 | if ((ArchVersion() < ARMv6) && (d == n)) |
| 833 | return false; |
| 834 | |
| 835 | break; |
| 836 | |
| 837 | default: |
| 838 | return false; |
| 839 | } |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 840 | |
| 841 | bool success = false; |
| 842 | |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 843 | // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results |
| 844 | uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 845 | if (!success) |
| 846 | return false; |
| 847 | |
| 848 | // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results |
| 849 | uint64_t operand2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 850 | if (!success) |
| 851 | return false; |
| 852 | |
| 853 | // result = operand1 * operand2; |
| 854 | uint64_t result = operand1 * operand2; |
| 855 | |
| 856 | // R[d] = result<31:0>; |
| 857 | Register op1_reg; |
| 858 | Register op2_reg; |
| 859 | op1_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 860 | op2_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 861 | |
| 862 | EmulateInstruction::Context context; |
| 863 | context.type = eContextMultiplication; |
| 864 | context.SetRegisterRegisterOperands (op1_reg, op2_reg); |
| 865 | |
| 866 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (0x0000ffff & result))) |
| 867 | return false; |
| 868 | |
| 869 | // if setflags then |
| 870 | if (setflags) |
| 871 | { |
| 872 | // APSR.N = result<31>; |
| 873 | // APSR.Z = IsZeroBit(result); |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 874 | m_new_inst_cpsr = m_opcode_cpsr; |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 875 | SetBit32 (m_new_inst_cpsr, CPSR_N_POS, Bit32 (result, 31)); |
| 876 | SetBit32 (m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0); |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 877 | if (m_new_inst_cpsr != m_opcode_cpsr) |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 878 | { |
| 879 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 880 | return false; |
| 881 | } |
| 882 | |
| 883 | // if ArchVersion() == 4 then |
| 884 | // APSR.C = bit UNKNOWN; |
| 885 | } |
| 886 | } |
| 887 | return true; |
| 888 | } |
| 889 | |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 890 | // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. |
| 891 | // It can optionally update the condition flags based on the value. |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 892 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 893 | EmulateInstructionARM::EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 894 | { |
| 895 | #if 0 |
| 896 | // ARM pseudo code... |
| 897 | if (ConditionPassed()) |
| 898 | { |
| 899 | EncodingSpecificOperations(); |
| 900 | result = NOT(imm32); |
| 901 | if d == 15 then // Can only occur for ARM encoding |
| 902 | ALUWritePC(result); // setflags is always FALSE here |
| 903 | else |
| 904 | R[d] = result; |
| 905 | if setflags then |
| 906 | APSR.N = result<31>; |
| 907 | APSR.Z = IsZeroBit(result); |
| 908 | APSR.C = carry; |
| 909 | // APSR.V unchanged |
| 910 | } |
| 911 | #endif |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 912 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 913 | if (ConditionPassed(opcode)) |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 914 | { |
| 915 | uint32_t Rd; // the destination register |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 916 | uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C |
| 917 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 918 | bool setflags; |
| 919 | switch (encoding) { |
| 920 | case eEncodingT1: |
| 921 | Rd = Bits32(opcode, 11, 8); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 922 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 923 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 924 | break; |
| 925 | case eEncodingA1: |
| 926 | Rd = Bits32(opcode, 15, 12); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 927 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 928 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); |
| 929 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 930 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 931 | if (Rd == 15 && setflags) |
| 932 | return false; |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 933 | break; |
| 934 | default: |
| 935 | return false; |
| 936 | } |
| 937 | uint32_t result = ~imm32; |
| 938 | |
| 939 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 940 | EmulateInstruction::Context context; |
| 941 | context.type = EmulateInstruction::eContextImmediate; |
| 942 | context.SetNoArgs (); |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 943 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 944 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 945 | return false; |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 946 | } |
| 947 | return true; |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 948 | } |
| 949 | |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 950 | // Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. |
| 951 | // It can optionally update the condition flags based on the result. |
| 952 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 953 | EmulateInstructionARM::EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 954 | { |
| 955 | #if 0 |
| 956 | // ARM pseudo code... |
| 957 | if (ConditionPassed()) |
| 958 | { |
| 959 | EncodingSpecificOperations(); |
| 960 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 961 | result = NOT(shifted); |
| 962 | if d == 15 then // Can only occur for ARM encoding |
| 963 | ALUWritePC(result); // setflags is always FALSE here |
| 964 | else |
| 965 | R[d] = result; |
| 966 | if setflags then |
| 967 | APSR.N = result<31>; |
| 968 | APSR.Z = IsZeroBit(result); |
| 969 | APSR.C = carry; |
| 970 | // APSR.V unchanged |
| 971 | } |
| 972 | #endif |
| 973 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 974 | if (ConditionPassed(opcode)) |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 975 | { |
| 976 | uint32_t Rm; // the source register |
| 977 | uint32_t Rd; // the destination register |
| 978 | ARM_ShifterType shift_t; |
| 979 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 980 | bool setflags; |
| 981 | uint32_t carry; // the carry bit after the shift operation |
| 982 | switch (encoding) { |
| 983 | case eEncodingT1: |
| 984 | Rd = Bits32(opcode, 2, 0); |
| 985 | Rm = Bits32(opcode, 5, 3); |
| 986 | setflags = !InITBlock(); |
| 987 | shift_t = SRType_LSL; |
| 988 | shift_n = 0; |
| 989 | if (InITBlock()) |
| 990 | return false; |
| 991 | break; |
| 992 | case eEncodingT2: |
| 993 | Rd = Bits32(opcode, 11, 8); |
| 994 | Rm = Bits32(opcode, 3, 0); |
| 995 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 996 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 997 | // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 998 | if (BadReg(Rd) || BadReg(Rm)) |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 999 | return false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 1000 | break; |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 1001 | case eEncodingA1: |
| 1002 | Rd = Bits32(opcode, 15, 12); |
| 1003 | Rm = Bits32(opcode, 3, 0); |
| 1004 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 1005 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 1006 | break; |
| 1007 | default: |
| 1008 | return false; |
| 1009 | } |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1010 | bool success = false; |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 1011 | uint32_t value = ReadCoreReg(Rm, &success); |
| 1012 | if (!success) |
| 1013 | return false; |
| 1014 | |
| 1015 | uint32_t shifted = Shift_C(value, shift_t, shift_n, APSR_C, carry); |
| 1016 | uint32_t result = ~shifted; |
| 1017 | |
| 1018 | // The context specifies that an immediate is to be moved into Rd. |
| 1019 | EmulateInstruction::Context context; |
| 1020 | context.type = EmulateInstruction::eContextImmediate; |
| 1021 | context.SetNoArgs (); |
| 1022 | |
| 1023 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 1024 | return false; |
| 1025 | } |
| 1026 | return true; |
| 1027 | } |
| 1028 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1029 | // PC relative immediate load into register, possibly followed by ADD (SP plus register). |
| 1030 | // LDR (literal) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1031 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1032 | EmulateInstructionARM::EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1033 | { |
| 1034 | #if 0 |
| 1035 | // ARM pseudo code... |
| 1036 | if (ConditionPassed()) |
| 1037 | { |
| 1038 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 1039 | base = Align(PC,4); |
| 1040 | address = if add then (base + imm32) else (base - imm32); |
| 1041 | data = MemU[address,4]; |
| 1042 | if t == 15 then |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1043 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 1044 | elsif UnalignedSupport() || address<1:0> = '00' then |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1045 | R[t] = data; |
| 1046 | else // Can only apply before ARMv7 |
| 1047 | if CurrentInstrSet() == InstrSet_ARM then |
| 1048 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 1049 | else |
| 1050 | R[t] = bits(32) UNKNOWN; |
| 1051 | } |
| 1052 | #endif |
| 1053 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1054 | if (ConditionPassed(opcode)) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1055 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1056 | bool success = false; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1057 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1058 | if (!success) |
| 1059 | return false; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 1060 | |
| 1061 | // PC relative immediate load context |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1062 | EmulateInstruction::Context context; |
| 1063 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1064 | Register pc_reg; |
| 1065 | pc_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 1066 | context.SetRegisterPlusOffset (pc_reg, 0); |
| 1067 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1068 | uint32_t Rt; // the destination register |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1069 | uint32_t imm32; // immediate offset from the PC |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1070 | bool add; // +imm32 or -imm32? |
| 1071 | addr_t base; // the base address |
| 1072 | addr_t address; // the PC relative address |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1073 | uint32_t data; // the literal data value from the PC relative load |
| 1074 | switch (encoding) { |
| 1075 | case eEncodingT1: |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1076 | Rt = Bits32(opcode, 10, 8); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1077 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1078 | add = true; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1079 | break; |
| 1080 | case eEncodingT2: |
| 1081 | Rt = Bits32(opcode, 15, 12); |
| 1082 | imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); |
| 1083 | add = BitIsSet(opcode, 23); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1084 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1085 | return false; |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1086 | break; |
| 1087 | default: |
| 1088 | return false; |
| 1089 | } |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1090 | |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1091 | base = Align(pc, 4); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1092 | if (add) |
| 1093 | address = base + imm32; |
| 1094 | else |
| 1095 | address = base - imm32; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1096 | |
| 1097 | context.SetRegisterPlusOffset(pc_reg, address - base); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 1098 | data = MemURead(context, address, 4, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1099 | if (!success) |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 1100 | return false; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1101 | |
| 1102 | if (Rt == 15) |
| 1103 | { |
| 1104 | if (Bits32(address, 1, 0) == 0) |
| 1105 | { |
| 1106 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1107 | if (!LoadWritePC(context, data)) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 1108 | return false; |
| 1109 | } |
| 1110 | else |
| 1111 | return false; |
| 1112 | } |
| 1113 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 1114 | { |
| 1115 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 1116 | return false; |
| 1117 | } |
| 1118 | else // We don't handle ARM for now. |
| 1119 | return false; |
| 1120 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1121 | } |
| 1122 | return true; |
| 1123 | } |
| 1124 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1125 | // An add operation to adjust the SP. |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1126 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1127 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1128 | EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1129 | { |
| 1130 | #if 0 |
| 1131 | // ARM pseudo code... |
| 1132 | if (ConditionPassed()) |
| 1133 | { |
| 1134 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1135 | (result, carry, overflow) = AddWithCarry(SP, imm32, '0'); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1136 | if d == 15 then // Can only occur for ARM encoding |
| 1137 | ALUWritePC(result); // setflags is always FALSE here |
| 1138 | else |
| 1139 | R[d] = result; |
| 1140 | if setflags then |
| 1141 | APSR.N = result<31>; |
| 1142 | APSR.Z = IsZeroBit(result); |
| 1143 | APSR.C = carry; |
| 1144 | APSR.V = overflow; |
| 1145 | } |
| 1146 | #endif |
| 1147 | |
| 1148 | bool success = false; |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1149 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1150 | if (ConditionPassed(opcode)) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1151 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1152 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1153 | if (!success) |
| 1154 | return false; |
| 1155 | uint32_t imm32; // the immediate operand |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 1156 | uint32_t d; |
| 1157 | bool setflags; |
| 1158 | switch (encoding) |
| 1159 | { |
| 1160 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1161 | // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32); |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 1162 | d = Bits32 (opcode, 10, 8); |
| 1163 | setflags = false; |
| 1164 | imm32 = (Bits32 (opcode, 7, 0) << 2); |
| 1165 | |
| 1166 | break; |
| 1167 | |
| 1168 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1169 | // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32); |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 1170 | d = 13; |
| 1171 | setflags = false; |
| 1172 | imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
| 1173 | |
| 1174 | break; |
| 1175 | |
| 1176 | default: |
| 1177 | return false; |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1178 | } |
| 1179 | addr_t sp_offset = imm32; |
| 1180 | addr_t addr = sp + sp_offset; // the adjusted stack pointer value |
| 1181 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1182 | EmulateInstruction::Context context; |
| 1183 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1184 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1185 | |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 1186 | if (d == 15) |
| 1187 | { |
| 1188 | if (!ALUWritePC (context, addr)) |
| 1189 | return false; |
| 1190 | } |
| 1191 | else |
| 1192 | { |
| 1193 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, addr)) |
| 1194 | return false; |
| 1195 | } |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1196 | } |
| 1197 | return true; |
| 1198 | } |
| 1199 | |
| 1200 | // An add operation to adjust the SP. |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1201 | // ADD (SP plus register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1202 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1203 | EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1204 | { |
| 1205 | #if 0 |
| 1206 | // ARM pseudo code... |
| 1207 | if (ConditionPassed()) |
| 1208 | { |
| 1209 | EncodingSpecificOperations(); |
| 1210 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1211 | (result, carry, overflow) = AddWithCarry(SP, shifted, '0'); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1212 | if d == 15 then |
| 1213 | ALUWritePC(result); // setflags is always FALSE here |
| 1214 | else |
| 1215 | R[d] = result; |
| 1216 | if setflags then |
| 1217 | APSR.N = result<31>; |
| 1218 | APSR.Z = IsZeroBit(result); |
| 1219 | APSR.C = carry; |
| 1220 | APSR.V = overflow; |
| 1221 | } |
| 1222 | #endif |
| 1223 | |
| 1224 | bool success = false; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1225 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1226 | if (ConditionPassed(opcode)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1227 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1228 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1229 | if (!success) |
| 1230 | return false; |
| 1231 | uint32_t Rm; // the second operand |
| 1232 | switch (encoding) { |
| 1233 | case eEncodingT2: |
| 1234 | Rm = Bits32(opcode, 6, 3); |
| 1235 | break; |
| 1236 | default: |
| 1237 | return false; |
| 1238 | } |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1239 | int32_t reg_value = ReadCoreReg(Rm, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1240 | if (!success) |
| 1241 | return false; |
| 1242 | |
| 1243 | addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value |
| 1244 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1245 | EmulateInstruction::Context context; |
| 1246 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1247 | context.SetImmediateSigned (reg_value); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1248 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1249 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1250 | return false; |
| 1251 | } |
| 1252 | return true; |
| 1253 | } |
| 1254 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1255 | // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine |
| 1256 | // at a PC-relative address, and changes instruction set from ARM to Thumb, or |
| 1257 | // from Thumb to ARM. |
| 1258 | // BLX (immediate) |
| 1259 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1260 | EmulateInstructionARM::EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1261 | { |
| 1262 | #if 0 |
| 1263 | // ARM pseudo code... |
| 1264 | if (ConditionPassed()) |
| 1265 | { |
| 1266 | EncodingSpecificOperations(); |
| 1267 | if CurrentInstrSet() == InstrSet_ARM then |
| 1268 | LR = PC - 4; |
| 1269 | else |
| 1270 | LR = PC<31:1> : '1'; |
| 1271 | if targetInstrSet == InstrSet_ARM then |
| 1272 | targetAddress = Align(PC,4) + imm32; |
| 1273 | else |
| 1274 | targetAddress = PC + imm32; |
| 1275 | SelectInstrSet(targetInstrSet); |
| 1276 | BranchWritePC(targetAddress); |
| 1277 | } |
| 1278 | #endif |
| 1279 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1280 | bool success = true; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1281 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1282 | if (ConditionPassed(opcode)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1283 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1284 | EmulateInstruction::Context context; |
| 1285 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1286 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1287 | if (!success) |
| 1288 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1289 | addr_t lr; // next instruction address |
| 1290 | addr_t target; // target address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1291 | int32_t imm32; // PC-relative offset |
| 1292 | switch (encoding) { |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1293 | case eEncodingT1: |
| 1294 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1295 | lr = pc | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1296 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1297 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1298 | uint32_t J1 = Bit32(opcode, 13); |
| 1299 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1300 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1301 | uint32_t I1 = !(J1 ^ S); |
| 1302 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1303 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1304 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1305 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1306 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1307 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1308 | return false; |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1309 | break; |
| 1310 | } |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1311 | case eEncodingT2: |
| 1312 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1313 | lr = pc | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1314 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1315 | uint32_t imm10H = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1316 | uint32_t J1 = Bit32(opcode, 13); |
| 1317 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1318 | uint32_t imm10L = Bits32(opcode, 10, 1); |
| 1319 | uint32_t I1 = !(J1 ^ S); |
| 1320 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1321 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1322 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1323 | target = Align(pc, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1324 | context.SetModeAndImmediateSigned (eModeARM, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1325 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1326 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1327 | break; |
| 1328 | } |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1329 | case eEncodingA1: |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 1330 | lr = pc - 4; // return address |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1331 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1332 | target = Align(pc, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1333 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1334 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1335 | case eEncodingA2: |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 1336 | lr = pc - 4; // return address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1337 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1338 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1339 | context.SetModeAndImmediateSigned (eModeThumb, 8 + imm32); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1340 | break; |
| 1341 | default: |
| 1342 | return false; |
| 1343 | } |
| 1344 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1345 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1346 | if (!BranchWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1347 | return false; |
| 1348 | } |
| 1349 | return true; |
| 1350 | } |
| 1351 | |
| 1352 | // Branch with Link and Exchange (register) calls a subroutine at an address and |
| 1353 | // instruction set specified by a register. |
| 1354 | // BLX (register) |
| 1355 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1356 | EmulateInstructionARM::EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1357 | { |
| 1358 | #if 0 |
| 1359 | // ARM pseudo code... |
| 1360 | if (ConditionPassed()) |
| 1361 | { |
| 1362 | EncodingSpecificOperations(); |
| 1363 | target = R[m]; |
| 1364 | if CurrentInstrSet() == InstrSet_ARM then |
| 1365 | next_instr_addr = PC - 4; |
| 1366 | LR = next_instr_addr; |
| 1367 | else |
| 1368 | next_instr_addr = PC - 2; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1369 | LR = next_instr_addr<31:1> : '1'; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1370 | BXWritePC(target); |
| 1371 | } |
| 1372 | #endif |
| 1373 | |
| 1374 | bool success = false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1375 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1376 | if (ConditionPassed(opcode)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1377 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1378 | EmulateInstruction::Context context; |
| 1379 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1380 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1381 | addr_t lr; // next instruction address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1382 | if (!success) |
| 1383 | return false; |
| 1384 | uint32_t Rm; // the register with the target address |
| 1385 | switch (encoding) { |
| 1386 | case eEncodingT1: |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1387 | lr = (pc - 2) | 1u; // return address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1388 | Rm = Bits32(opcode, 6, 3); |
| 1389 | // if m == 15 then UNPREDICTABLE; |
| 1390 | if (Rm == 15) |
| 1391 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1392 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1393 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1394 | break; |
| 1395 | case eEncodingA1: |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1396 | lr = pc - 4; // return address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1397 | Rm = Bits32(opcode, 3, 0); |
| 1398 | // if m == 15 then UNPREDICTABLE; |
| 1399 | if (Rm == 15) |
| 1400 | return false; |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1401 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1402 | default: |
| 1403 | return false; |
| 1404 | } |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1405 | addr_t target = ReadCoreReg (Rm, &success); |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1406 | if (!success) |
| 1407 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1408 | Register dwarf_reg; |
| 1409 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 1410 | context.SetRegister (dwarf_reg); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1411 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1412 | return false; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1413 | if (!BXWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1414 | return false; |
| 1415 | } |
| 1416 | return true; |
| 1417 | } |
| 1418 | |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1419 | // Branch and Exchange causes a branch to an address and instruction set specified by a register. |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1420 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1421 | EmulateInstructionARM::EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1422 | { |
| 1423 | #if 0 |
| 1424 | // ARM pseudo code... |
| 1425 | if (ConditionPassed()) |
| 1426 | { |
| 1427 | EncodingSpecificOperations(); |
| 1428 | BXWritePC(R[m]); |
| 1429 | } |
| 1430 | #endif |
| 1431 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1432 | if (ConditionPassed(opcode)) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1433 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1434 | EmulateInstruction::Context context; |
| 1435 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1436 | uint32_t Rm; // the register with the target address |
| 1437 | switch (encoding) { |
| 1438 | case eEncodingT1: |
| 1439 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1440 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1441 | return false; |
| 1442 | break; |
| 1443 | case eEncodingA1: |
| 1444 | Rm = Bits32(opcode, 3, 0); |
| 1445 | break; |
| 1446 | default: |
| 1447 | return false; |
| 1448 | } |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1449 | bool success = false; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1450 | addr_t target = ReadCoreReg (Rm, &success); |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1451 | if (!success) |
| 1452 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1453 | |
| 1454 | Register dwarf_reg; |
| 1455 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1456 | context.SetRegister (dwarf_reg); |
| 1457 | if (!BXWritePC(context, target)) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1458 | return false; |
| 1459 | } |
| 1460 | return true; |
| 1461 | } |
| 1462 | |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 1463 | // Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an |
| 1464 | // address and instruction set specified by a register as though it were a BX instruction. |
| 1465 | // |
| 1466 | // TODO: Emulate Jazelle architecture? |
| 1467 | // We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation. |
| 1468 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1469 | EmulateInstructionARM::EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 1470 | { |
| 1471 | #if 0 |
| 1472 | // ARM pseudo code... |
| 1473 | if (ConditionPassed()) |
| 1474 | { |
| 1475 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1476 | if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 1477 | BXWritePC(R[m]); |
| 1478 | else |
| 1479 | if JazelleAcceptsExecution() then |
| 1480 | SwitchToJazelleExecution(); |
| 1481 | else |
| 1482 | SUBARCHITECTURE_DEFINED handler call; |
| 1483 | } |
| 1484 | #endif |
| 1485 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1486 | if (ConditionPassed(opcode)) |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 1487 | { |
| 1488 | EmulateInstruction::Context context; |
| 1489 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
| 1490 | uint32_t Rm; // the register with the target address |
| 1491 | switch (encoding) { |
| 1492 | case eEncodingT1: |
| 1493 | Rm = Bits32(opcode, 19, 16); |
| 1494 | if (BadReg(Rm)) |
| 1495 | return false; |
| 1496 | if (InITBlock() && !LastInITBlock()) |
| 1497 | return false; |
| 1498 | break; |
| 1499 | case eEncodingA1: |
| 1500 | Rm = Bits32(opcode, 3, 0); |
| 1501 | if (Rm == 15) |
| 1502 | return false; |
| 1503 | break; |
| 1504 | default: |
| 1505 | return false; |
| 1506 | } |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1507 | bool success = false; |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 1508 | addr_t target = ReadCoreReg (Rm, &success); |
| 1509 | if (!success) |
| 1510 | return false; |
| 1511 | |
| 1512 | Register dwarf_reg; |
| 1513 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 1514 | context.SetRegister (dwarf_reg); |
| 1515 | if (!BXWritePC(context, target)) |
| 1516 | return false; |
| 1517 | } |
| 1518 | return true; |
| 1519 | } |
| 1520 | |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1521 | // Set r7 to point to some ip offset. |
| 1522 | // SUB (immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1523 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1524 | EmulateInstructionARM::EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1525 | { |
| 1526 | #if 0 |
| 1527 | // ARM pseudo code... |
| 1528 | if (ConditionPassed()) |
| 1529 | { |
| 1530 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1531 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1532 | if d == 15 then // Can only occur for ARM encoding |
| 1533 | ALUWritePC(result); // setflags is always FALSE here |
| 1534 | else |
| 1535 | R[d] = result; |
| 1536 | if setflags then |
| 1537 | APSR.N = result<31>; |
| 1538 | APSR.Z = IsZeroBit(result); |
| 1539 | APSR.C = carry; |
| 1540 | APSR.V = overflow; |
| 1541 | } |
| 1542 | #endif |
| 1543 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1544 | if (ConditionPassed(opcode)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1545 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1546 | bool success = false; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1547 | const addr_t ip = ReadCoreReg (12, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1548 | if (!success) |
| 1549 | return false; |
| 1550 | uint32_t imm32; |
| 1551 | switch (encoding) { |
| 1552 | case eEncodingA1: |
| 1553 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1554 | break; |
| 1555 | default: |
| 1556 | return false; |
| 1557 | } |
| 1558 | addr_t ip_offset = imm32; |
| 1559 | addr_t addr = ip - ip_offset; // the adjusted ip value |
| 1560 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1561 | EmulateInstruction::Context context; |
| 1562 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1563 | Register dwarf_reg; |
| 1564 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r12); |
| 1565 | context.SetRegisterPlusOffset (dwarf_reg, -ip_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1566 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1567 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1568 | return false; |
| 1569 | } |
| 1570 | return true; |
| 1571 | } |
| 1572 | |
| 1573 | // Set ip to point to some stack offset. |
| 1574 | // SUB (SP minus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1575 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1576 | EmulateInstructionARM::EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1577 | { |
| 1578 | #if 0 |
| 1579 | // ARM pseudo code... |
| 1580 | if (ConditionPassed()) |
| 1581 | { |
| 1582 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1583 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1584 | if d == 15 then // Can only occur for ARM encoding |
| 1585 | ALUWritePC(result); // setflags is always FALSE here |
| 1586 | else |
| 1587 | R[d] = result; |
| 1588 | if setflags then |
| 1589 | APSR.N = result<31>; |
| 1590 | APSR.Z = IsZeroBit(result); |
| 1591 | APSR.C = carry; |
| 1592 | APSR.V = overflow; |
| 1593 | } |
| 1594 | #endif |
| 1595 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1596 | if (ConditionPassed(opcode)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1597 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1598 | bool success = false; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1599 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1600 | if (!success) |
| 1601 | return false; |
| 1602 | uint32_t imm32; |
| 1603 | switch (encoding) { |
| 1604 | case eEncodingA1: |
| 1605 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1606 | break; |
| 1607 | default: |
| 1608 | return false; |
| 1609 | } |
| 1610 | addr_t sp_offset = imm32; |
| 1611 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1612 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1613 | EmulateInstruction::Context context; |
| 1614 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1615 | Register dwarf_reg; |
| 1616 | dwarf_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 1617 | context.SetRegisterPlusOffset (dwarf_reg, -sp_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1618 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1619 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1620 | return false; |
| 1621 | } |
| 1622 | return true; |
| 1623 | } |
| 1624 | |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1625 | // This instruction subtracts an immediate value from the SP value, and writes |
| 1626 | // the result to the destination register. |
| 1627 | // |
| 1628 | // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1629 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1630 | EmulateInstructionARM::EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1631 | { |
| 1632 | #if 0 |
| 1633 | // ARM pseudo code... |
| 1634 | if (ConditionPassed()) |
| 1635 | { |
| 1636 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1637 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 1638 | if d == 15 then // Can only occur for ARM encoding |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1639 | ALUWritePC(result); // setflags is always FALSE here |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1640 | else |
| 1641 | R[d] = result; |
| 1642 | if setflags then |
| 1643 | APSR.N = result<31>; |
| 1644 | APSR.Z = IsZeroBit(result); |
| 1645 | APSR.C = carry; |
| 1646 | APSR.V = overflow; |
| 1647 | } |
| 1648 | #endif |
| 1649 | |
| 1650 | bool success = false; |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1651 | if (ConditionPassed(opcode)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1652 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1653 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1654 | if (!success) |
| 1655 | return false; |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1656 | |
| 1657 | uint32_t Rd; |
| 1658 | bool setflags; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1659 | uint32_t imm32; |
| 1660 | switch (encoding) { |
Johnny Chen | e445502 | 2011-01-26 00:08:59 +0000 | [diff] [blame] | 1661 | case eEncodingT1: |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1662 | Rd = 13; |
| 1663 | setflags = false; |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 1664 | imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 1665 | break; |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1666 | case eEncodingT2: |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1667 | Rd = Bits32(opcode, 11, 8); |
| 1668 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1669 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1670 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1671 | return EmulateCMPImm(opcode, eEncodingT2); |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1672 | if (Rd == 15 && !setflags) |
| 1673 | return false; |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1674 | break; |
| 1675 | case eEncodingT3: |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1676 | Rd = Bits32(opcode, 11, 8); |
| 1677 | setflags = false; |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1678 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 1679 | if (Rd == 15) |
| 1680 | return false; |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1681 | break; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1682 | case eEncodingA1: |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1683 | Rd = Bits32(opcode, 15, 12); |
| 1684 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1685 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 1686 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 1687 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 1688 | if (Rd == 15 && setflags) |
| 1689 | return false; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1690 | break; |
| 1691 | default: |
| 1692 | return false; |
| 1693 | } |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1694 | AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1); |
| 1695 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1696 | EmulateInstruction::Context context; |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1697 | if (Rd == 13) |
| 1698 | { |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 1699 | uint64_t imm64 = imm32; // Need to expand it to 64 bits before attempting to negate it, or the wrong |
| 1700 | // value gets passed down to context.SetImmediateSigned. |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1701 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 2b03ed8 | 2011-03-16 00:06:12 +0000 | [diff] [blame] | 1702 | context.SetImmediateSigned (-imm64); // the stack pointer offset |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 1703 | } |
| 1704 | else |
| 1705 | { |
| 1706 | context.type = EmulateInstruction::eContextImmediate; |
| 1707 | context.SetNoArgs (); |
| 1708 | } |
| 1709 | |
| 1710 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1711 | return false; |
| 1712 | } |
| 1713 | return true; |
| 1714 | } |
| 1715 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1716 | // A store operation to the stack that also updates the SP. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1717 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1718 | EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1719 | { |
| 1720 | #if 0 |
| 1721 | // ARM pseudo code... |
| 1722 | if (ConditionPassed()) |
| 1723 | { |
| 1724 | EncodingSpecificOperations(); |
| 1725 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 1726 | address = if index then offset_addr else R[n]; |
| 1727 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 1728 | if wback then R[n] = offset_addr; |
| 1729 | } |
| 1730 | #endif |
| 1731 | |
| 1732 | bool success = false; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1733 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1734 | if (ConditionPassed(opcode)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1735 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1736 | const uint32_t addr_byte_size = GetAddressByteSize(); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1737 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1738 | if (!success) |
| 1739 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1740 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1741 | uint32_t imm12; |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 1742 | uint32_t Rn; // This function assumes Rn is the SP, but we should verify that. |
| 1743 | |
| 1744 | bool index; |
| 1745 | bool add; |
| 1746 | bool wback; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1747 | switch (encoding) { |
| 1748 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 1749 | Rt = Bits32(opcode, 15, 12); |
| 1750 | imm12 = Bits32(opcode, 11, 0); |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 1751 | Rn = Bits32 (opcode, 19, 16); |
| 1752 | |
| 1753 | if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP. |
| 1754 | return false; |
| 1755 | |
| 1756 | index = BitIsSet (opcode, 24); |
| 1757 | add = BitIsSet (opcode, 23); |
| 1758 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 1759 | |
| 1760 | if (wback && ((Rn == 15) || (Rn == Rt))) |
| 1761 | return false; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1762 | break; |
| 1763 | default: |
| 1764 | return false; |
| 1765 | } |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 1766 | addr_t offset_addr; |
| 1767 | if (add) |
| 1768 | offset_addr = sp + imm12; |
| 1769 | else |
| 1770 | offset_addr = sp - imm12; |
| 1771 | |
| 1772 | addr_t addr; |
| 1773 | if (index) |
| 1774 | addr = offset_addr; |
| 1775 | else |
| 1776 | addr = sp; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1777 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1778 | EmulateInstruction::Context context; |
| 1779 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 1780 | Register sp_reg; |
| 1781 | sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); |
| 1782 | context.SetRegisterPlusOffset (sp_reg, addr - sp); |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1783 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1784 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1785 | uint32_t reg_value = ReadCoreReg(Rt, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1786 | if (!success) |
| 1787 | return false; |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 1788 | if (!MemUWrite (context, addr, reg_value, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1789 | return false; |
| 1790 | } |
| 1791 | else |
| 1792 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1793 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1794 | if (!success) |
| 1795 | return false; |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 1796 | if (!MemUWrite (context, addr, pc, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1797 | return false; |
| 1798 | } |
| 1799 | |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 1800 | |
| 1801 | if (wback) |
| 1802 | { |
| 1803 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1804 | context.SetImmediateSigned (addr - sp); |
| 1805 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, offset_addr)) |
| 1806 | return false; |
| 1807 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1808 | } |
| 1809 | return true; |
| 1810 | } |
| 1811 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1812 | // Vector Push stores multiple extension registers to the stack. |
| 1813 | // It also updates SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1814 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1815 | EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1816 | { |
| 1817 | #if 0 |
| 1818 | // ARM pseudo code... |
| 1819 | if (ConditionPassed()) |
| 1820 | { |
| 1821 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1822 | address = SP - imm32; |
| 1823 | SP = SP - imm32; |
| 1824 | if single_regs then |
| 1825 | for r = 0 to regs-1 |
| 1826 | MemA[address,4] = S[d+r]; address = address+4; |
| 1827 | else |
| 1828 | for r = 0 to regs-1 |
| 1829 | // Store as two word-aligned words in the correct order for current endianness. |
| 1830 | MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>; |
| 1831 | MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>; |
| 1832 | address = address+8; |
| 1833 | } |
| 1834 | #endif |
| 1835 | |
| 1836 | bool success = false; |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1837 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1838 | if (ConditionPassed(opcode)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1839 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1840 | const uint32_t addr_byte_size = GetAddressByteSize(); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1841 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1842 | if (!success) |
| 1843 | return false; |
| 1844 | bool single_regs; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1845 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1846 | uint32_t imm32; // stack offset |
| 1847 | uint32_t regs; // number of registers |
| 1848 | switch (encoding) { |
| 1849 | case eEncodingT1: |
| 1850 | case eEncodingA1: |
| 1851 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1852 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1853 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1854 | // If UInt(imm8) is odd, see "FSTMX". |
| 1855 | regs = Bits32(opcode, 7, 0) / 2; |
| 1856 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1857 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1858 | return false; |
| 1859 | break; |
| 1860 | case eEncodingT2: |
| 1861 | case eEncodingA2: |
| 1862 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1863 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1864 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1865 | regs = Bits32(opcode, 7, 0); |
| 1866 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1867 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1868 | return false; |
| 1869 | break; |
| 1870 | default: |
| 1871 | return false; |
| 1872 | } |
| 1873 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1874 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1875 | addr_t sp_offset = imm32; |
| 1876 | addr_t addr = sp - sp_offset; |
| 1877 | uint32_t i; |
| 1878 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1879 | EmulateInstruction::Context context; |
| 1880 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 1881 | Register dwarf_reg; |
| 1882 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1883 | Register sp_reg; |
| 1884 | sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); |
| 1885 | for (i=0; i<regs; ++i) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1886 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1887 | dwarf_reg.num = start_reg + d + i; |
| 1888 | context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1889 | // uint64_t to accommodate 64-bit registers. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1890 | uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1891 | if (!success) |
| 1892 | return false; |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 1893 | if (!MemAWrite (context, addr, reg_value, reg_byte_size)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1894 | return false; |
| 1895 | addr += reg_byte_size; |
| 1896 | } |
| 1897 | |
| 1898 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1899 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1900 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1901 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1902 | return false; |
| 1903 | } |
| 1904 | return true; |
| 1905 | } |
| 1906 | |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1907 | // Vector Pop loads multiple extension registers from the stack. |
| 1908 | // It also updates SP to point just above the loaded data. |
| 1909 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1910 | EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1911 | { |
| 1912 | #if 0 |
| 1913 | // ARM pseudo code... |
| 1914 | if (ConditionPassed()) |
| 1915 | { |
| 1916 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1917 | address = SP; |
| 1918 | SP = SP + imm32; |
| 1919 | if single_regs then |
| 1920 | for r = 0 to regs-1 |
| 1921 | S[d+r] = MemA[address,4]; address = address+4; |
| 1922 | else |
| 1923 | for r = 0 to regs-1 |
| 1924 | word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; |
| 1925 | // Combine the word-aligned words in the correct order for current endianness. |
| 1926 | D[d+r] = if BigEndian() then word1:word2 else word2:word1; |
| 1927 | } |
| 1928 | #endif |
| 1929 | |
| 1930 | bool success = false; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1931 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 1932 | if (ConditionPassed(opcode)) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1933 | { |
| 1934 | const uint32_t addr_byte_size = GetAddressByteSize(); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 1935 | const addr_t sp = ReadCoreReg (SP_REG, &success); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1936 | if (!success) |
| 1937 | return false; |
| 1938 | bool single_regs; |
| 1939 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
| 1940 | uint32_t imm32; // stack offset |
| 1941 | uint32_t regs; // number of registers |
| 1942 | switch (encoding) { |
| 1943 | case eEncodingT1: |
| 1944 | case eEncodingA1: |
| 1945 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1946 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1947 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1948 | // If UInt(imm8) is odd, see "FLDMX". |
| 1949 | regs = Bits32(opcode, 7, 0) / 2; |
| 1950 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1951 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1952 | return false; |
| 1953 | break; |
| 1954 | case eEncodingT2: |
| 1955 | case eEncodingA2: |
| 1956 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1957 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1958 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1959 | regs = Bits32(opcode, 7, 0); |
| 1960 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1961 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1962 | return false; |
| 1963 | break; |
| 1964 | default: |
| 1965 | return false; |
| 1966 | } |
| 1967 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1968 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1969 | addr_t sp_offset = imm32; |
| 1970 | addr_t addr = sp; |
| 1971 | uint32_t i; |
| 1972 | uint64_t data; // uint64_t to accomodate 64-bit registers. |
| 1973 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1974 | EmulateInstruction::Context context; |
| 1975 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 1976 | Register dwarf_reg; |
| 1977 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1978 | Register sp_reg; |
| 1979 | sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); |
| 1980 | for (i=0; i<regs; ++i) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1981 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 1982 | dwarf_reg.num = start_reg + d + i; |
| 1983 | context.SetRegisterPlusOffset (sp_reg, addr - sp); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 1984 | data = MemARead(context, addr, reg_byte_size, 0, &success); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1985 | if (!success) |
| 1986 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1987 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1988 | return false; |
| 1989 | addr += reg_byte_size; |
| 1990 | } |
| 1991 | |
| 1992 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1993 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1994 | |
| 1995 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
| 1996 | return false; |
| 1997 | } |
| 1998 | return true; |
| 1999 | } |
| 2000 | |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2001 | // SVC (previously SWI) |
| 2002 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2003 | EmulateInstructionARM::EmulateSVC (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2004 | { |
| 2005 | #if 0 |
| 2006 | // ARM pseudo code... |
| 2007 | if (ConditionPassed()) |
| 2008 | { |
| 2009 | EncodingSpecificOperations(); |
| 2010 | CallSupervisor(); |
| 2011 | } |
| 2012 | #endif |
| 2013 | |
| 2014 | bool success = false; |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2015 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2016 | if (ConditionPassed(opcode)) |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2017 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2018 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2019 | addr_t lr; // next instruction address |
| 2020 | if (!success) |
| 2021 | return false; |
| 2022 | uint32_t imm32; // the immediate constant |
| 2023 | uint32_t mode; // ARM or Thumb mode |
| 2024 | switch (encoding) { |
| 2025 | case eEncodingT1: |
| 2026 | lr = (pc + 2) | 1u; // return address |
| 2027 | imm32 = Bits32(opcode, 7, 0); |
| 2028 | mode = eModeThumb; |
| 2029 | break; |
| 2030 | case eEncodingA1: |
| 2031 | lr = pc + 4; // return address |
| 2032 | imm32 = Bits32(opcode, 23, 0); |
| 2033 | mode = eModeARM; |
| 2034 | break; |
| 2035 | default: |
| 2036 | return false; |
| 2037 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2038 | |
| 2039 | EmulateInstruction::Context context; |
| 2040 | context.type = EmulateInstruction::eContextSupervisorCall; |
| 2041 | context.SetModeAndImmediate (mode, imm32); |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 2042 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 2043 | return false; |
| 2044 | } |
| 2045 | return true; |
| 2046 | } |
| 2047 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 2048 | // If Then makes up to four following instructions (the IT block) conditional. |
| 2049 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2050 | EmulateInstructionARM::EmulateIT (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 2051 | { |
| 2052 | #if 0 |
| 2053 | // ARM pseudo code... |
| 2054 | EncodingSpecificOperations(); |
| 2055 | ITSTATE.IT<7:0> = firstcond:mask; |
| 2056 | #endif |
| 2057 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 2058 | m_it_session.InitIT(Bits32(opcode, 7, 0)); |
| 2059 | return true; |
| 2060 | } |
| 2061 | |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2062 | // Branch causes a branch to a target address. |
| 2063 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2064 | EmulateInstructionARM::EmulateB (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2065 | { |
| 2066 | #if 0 |
| 2067 | // ARM pseudo code... |
| 2068 | if (ConditionPassed()) |
| 2069 | { |
| 2070 | EncodingSpecificOperations(); |
| 2071 | BranchWritePC(PC + imm32); |
| 2072 | } |
| 2073 | #endif |
| 2074 | |
| 2075 | bool success = false; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2076 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2077 | if (ConditionPassed(opcode)) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2078 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2079 | EmulateInstruction::Context context; |
| 2080 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2081 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2082 | if (!success) |
| 2083 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2084 | addr_t target; // target address |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2085 | int32_t imm32; // PC-relative offset |
| 2086 | switch (encoding) { |
| 2087 | case eEncodingT1: |
| 2088 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 2089 | imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2090 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2091 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2092 | break; |
| 2093 | case eEncodingT2: |
| 2094 | imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0)); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2095 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2096 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2097 | break; |
| 2098 | case eEncodingT3: |
| 2099 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 2100 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2101 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2102 | uint32_t imm6 = Bits32(opcode, 21, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2103 | uint32_t J1 = Bit32(opcode, 13); |
| 2104 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2105 | uint32_t imm11 = Bits32(opcode, 10, 0); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2106 | uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2107 | imm32 = llvm::SignExtend32<21>(imm21); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2108 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2109 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2110 | break; |
| 2111 | } |
| 2112 | case eEncodingT4: |
| 2113 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2114 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2115 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2116 | uint32_t J1 = Bit32(opcode, 13); |
| 2117 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2118 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 2119 | uint32_t I1 = !(J1 ^ S); |
| 2120 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2121 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2122 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2123 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2124 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2125 | break; |
| 2126 | } |
| 2127 | case eEncodingA1: |
| 2128 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2129 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2130 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 2131 | break; |
| 2132 | default: |
| 2133 | return false; |
| 2134 | } |
| 2135 | if (!BranchWritePC(context, target)) |
| 2136 | return false; |
| 2137 | } |
| 2138 | return true; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 2139 | } |
| 2140 | |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2141 | // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with |
| 2142 | // zero and conditionally branch forward a constant value. They do not affect the condition flags. |
| 2143 | // CBNZ, CBZ |
| 2144 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2145 | EmulateInstructionARM::EmulateCB (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2146 | { |
| 2147 | #if 0 |
| 2148 | // ARM pseudo code... |
| 2149 | EncodingSpecificOperations(); |
| 2150 | if nonzero ^ IsZero(R[n]) then |
| 2151 | BranchWritePC(PC + imm32); |
| 2152 | #endif |
| 2153 | |
| 2154 | bool success = false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2155 | |
| 2156 | // Read the register value from the operand register Rn. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2157 | uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2158 | if (!success) |
| 2159 | return false; |
| 2160 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2161 | EmulateInstruction::Context context; |
| 2162 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2163 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2164 | if (!success) |
| 2165 | return false; |
| 2166 | |
| 2167 | addr_t target; // target address |
| 2168 | uint32_t imm32; // PC-relative offset to branch forward |
| 2169 | bool nonzero; |
| 2170 | switch (encoding) { |
| 2171 | case eEncodingT1: |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2172 | imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2173 | nonzero = BitIsSet(opcode, 11); |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2174 | target = pc + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2175 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 2176 | break; |
| 2177 | default: |
| 2178 | return false; |
| 2179 | } |
| 2180 | if (nonzero ^ (reg_val == 0)) |
| 2181 | if (!BranchWritePC(context, target)) |
| 2182 | return false; |
| 2183 | |
| 2184 | return true; |
| 2185 | } |
| 2186 | |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2187 | // Table Branch Byte causes a PC-relative forward branch using a table of single byte offsets. |
| 2188 | // A base register provides a pointer to the table, and a second register supplies an index into the table. |
| 2189 | // The branch length is twice the value of the byte returned from the table. |
| 2190 | // |
| 2191 | // Table Branch Halfword causes a PC-relative forward branch using a table of single halfword offsets. |
| 2192 | // A base register provides a pointer to the table, and a second register supplies an index into the table. |
| 2193 | // The branch length is twice the value of the halfword returned from the table. |
| 2194 | // TBB, TBH |
| 2195 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2196 | EmulateInstructionARM::EmulateTB (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2197 | { |
| 2198 | #if 0 |
| 2199 | // ARM pseudo code... |
| 2200 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2201 | if is_tbh then |
| 2202 | halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]); |
| 2203 | else |
| 2204 | halfwords = UInt(MemU[R[n]+R[m], 1]); |
| 2205 | BranchWritePC(PC + 2*halfwords); |
| 2206 | #endif |
| 2207 | |
| 2208 | bool success = false; |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2209 | |
| 2210 | uint32_t Rn; // the base register which contains the address of the table of branch lengths |
| 2211 | uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table |
| 2212 | bool is_tbh; // true if table branch halfword |
| 2213 | switch (encoding) { |
| 2214 | case eEncodingT1: |
| 2215 | Rn = Bits32(opcode, 19, 16); |
| 2216 | Rm = Bits32(opcode, 3, 0); |
| 2217 | is_tbh = BitIsSet(opcode, 4); |
| 2218 | if (Rn == 13 || BadReg(Rm)) |
| 2219 | return false; |
| 2220 | if (InITBlock() && !LastInITBlock()) |
| 2221 | return false; |
| 2222 | break; |
| 2223 | default: |
| 2224 | return false; |
| 2225 | } |
| 2226 | |
| 2227 | // Read the address of the table from the operand register Rn. |
| 2228 | // The PC can be used, in which case the table immediately follows this instruction. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2229 | uint32_t base = ReadCoreReg(Rm, &success); |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2230 | if (!success) |
| 2231 | return false; |
| 2232 | |
| 2233 | // the table index |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2234 | uint32_t index = ReadCoreReg(Rm, &success); |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2235 | if (!success) |
| 2236 | return false; |
| 2237 | |
| 2238 | // the offsetted table address |
| 2239 | addr_t addr = base + (is_tbh ? index*2 : index); |
| 2240 | |
| 2241 | // PC-relative offset to branch forward |
| 2242 | EmulateInstruction::Context context; |
| 2243 | context.type = EmulateInstruction::eContextTableBranchReadMemory; |
Johnny Chen | 104c8b6 | 2011-02-17 23:27:44 +0000 | [diff] [blame] | 2244 | uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2; |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2245 | if (!success) |
| 2246 | return false; |
| 2247 | |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2248 | const uint32_t pc = ReadCoreReg(PC_REG, &success); |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2249 | if (!success) |
| 2250 | return false; |
| 2251 | |
| 2252 | // target address |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2253 | addr_t target = pc + offset; |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 2254 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
| 2255 | context.SetModeAndImmediateSigned (eModeThumb, 4 + offset); |
| 2256 | |
| 2257 | if (!BranchWritePC(context, target)) |
| 2258 | return false; |
| 2259 | |
| 2260 | return true; |
| 2261 | } |
| 2262 | |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2263 | // This instruction adds an immediate value to a register value, and writes the result to the destination register. |
| 2264 | // It can optionally update the condition flags based on the result. |
| 2265 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2266 | EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2267 | { |
| 2268 | #if 0 |
| 2269 | if ConditionPassed() then |
| 2270 | EncodingSpecificOperations(); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 2271 | (result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2272 | R[d] = result; |
| 2273 | if setflags then |
| 2274 | APSR.N = result<31>; |
| 2275 | APSR.Z = IsZeroBit(result); |
| 2276 | APSR.C = carry; |
| 2277 | APSR.V = overflow; |
| 2278 | #endif |
| 2279 | |
| 2280 | bool success = false; |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2281 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2282 | if (ConditionPassed(opcode)) |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2283 | { |
| 2284 | uint32_t d; |
| 2285 | uint32_t n; |
| 2286 | bool setflags; |
| 2287 | uint32_t imm32; |
| 2288 | uint32_t carry_out; |
| 2289 | |
| 2290 | //EncodingSpecificOperations(); |
| 2291 | switch (encoding) |
| 2292 | { |
| 2293 | case eEncodingT1: |
| 2294 | // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32); |
| 2295 | d = Bits32 (opcode, 2, 0); |
| 2296 | n = Bits32 (opcode, 5, 3); |
| 2297 | setflags = !InITBlock(); |
| 2298 | imm32 = Bits32 (opcode, 8,6); |
| 2299 | |
| 2300 | break; |
| 2301 | |
| 2302 | case eEncodingT2: |
| 2303 | // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 = ZeroExtend(imm8, 32); |
| 2304 | d = Bits32 (opcode, 10, 8); |
| 2305 | n = Bits32 (opcode, 10, 8); |
| 2306 | setflags = !InITBlock(); |
| 2307 | imm32 = Bits32 (opcode, 7, 0); |
| 2308 | |
| 2309 | break; |
| 2310 | |
| 2311 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 2312 | // if Rd == '1111' && S == '1' then SEE CMN (immediate); |
| 2313 | // if Rn == '1101' then SEE ADD (SP plus immediate); |
| 2314 | // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8); |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2315 | d = Bits32 (opcode, 11, 8); |
| 2316 | n = Bits32 (opcode, 19, 16); |
| 2317 | setflags = BitIsSet (opcode, 20); |
| 2318 | imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out); |
| 2319 | |
| 2320 | // if BadReg(d) || n == 15 then UNPREDICTABLE; |
| 2321 | if (BadReg (d) || (n == 15)) |
| 2322 | return false; |
| 2323 | |
| 2324 | break; |
| 2325 | |
| 2326 | case eEncodingT4: |
| 2327 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 2328 | // if Rn == '1111' then SEE ADR; |
| 2329 | // if Rn == '1101' then SEE ADD (SP plus immediate); |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2330 | // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32); |
| 2331 | d = Bits32 (opcode, 11, 8); |
| 2332 | n = Bits32 (opcode, 19, 16); |
| 2333 | setflags = false; |
| 2334 | uint32_t i = Bit32 (opcode, 26); |
| 2335 | uint32_t imm3 = Bits32 (opcode, 14, 12); |
| 2336 | uint32_t imm8 = Bits32 (opcode, 7, 0); |
| 2337 | imm32 = (i << 11) | (imm3 << 8) | imm8; |
| 2338 | |
| 2339 | // if BadReg(d) then UNPREDICTABLE; |
| 2340 | if (BadReg (d)) |
| 2341 | return false; |
| 2342 | |
| 2343 | break; |
| 2344 | } |
| 2345 | default: |
| 2346 | return false; |
| 2347 | } |
| 2348 | |
| 2349 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2350 | if (!success) |
| 2351 | return false; |
| 2352 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 2353 | //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 2354 | AddWithCarryResult res = AddWithCarry (Rn, imm32, 0); |
| 2355 | |
| 2356 | Register reg_n; |
| 2357 | reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2358 | |
| 2359 | EmulateInstruction::Context context; |
| 2360 | context.type = eContextAddition; |
| 2361 | context.SetRegisterPlusOffset (reg_n, imm32); |
| 2362 | |
| 2363 | //R[d] = result; |
| 2364 | //if setflags then |
| 2365 | //APSR.N = result<31>; |
| 2366 | //APSR.Z = IsZeroBit(result); |
| 2367 | //APSR.C = carry; |
| 2368 | //APSR.V = overflow; |
| 2369 | if (!WriteCoreRegOptionalFlags (context, res.result, d, setflags, res.carry_out, res.overflow)) |
| 2370 | return false; |
| 2371 | |
| 2372 | } |
| 2373 | return true; |
| 2374 | } |
| 2375 | |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2376 | // This instruction adds an immediate value to a register value, and writes the result to the destination |
| 2377 | // register. It can optionally update the condition flags based on the result. |
| 2378 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2379 | EmulateInstructionARM::EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2380 | { |
| 2381 | #if 0 |
| 2382 | // ARM pseudo code... |
| 2383 | if ConditionPassed() then |
| 2384 | EncodingSpecificOperations(); |
| 2385 | (result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); |
| 2386 | if d == 15 then |
| 2387 | ALUWritePC(result); // setflags is always FALSE here |
| 2388 | else |
| 2389 | R[d] = result; |
| 2390 | if setflags then |
| 2391 | APSR.N = result<31>; |
| 2392 | APSR.Z = IsZeroBit(result); |
| 2393 | APSR.C = carry; |
| 2394 | APSR.V = overflow; |
| 2395 | #endif |
| 2396 | |
| 2397 | bool success = false; |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2398 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2399 | if (ConditionPassed(opcode)) |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2400 | { |
| 2401 | uint32_t Rd, Rn; |
| 2402 | uint32_t imm32; // the immediate value to be added to the value obtained from Rn |
| 2403 | bool setflags; |
| 2404 | switch (encoding) |
| 2405 | { |
| 2406 | case eEncodingA1: |
| 2407 | Rd = Bits32(opcode, 15, 12); |
| 2408 | Rn = Bits32(opcode, 19, 16); |
| 2409 | setflags = BitIsSet(opcode, 20); |
| 2410 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 2411 | break; |
| 2412 | default: |
| 2413 | return false; |
| 2414 | } |
| 2415 | |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2416 | // Read the first operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 2417 | uint32_t val1 = ReadCoreReg(Rn, &success); |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2418 | if (!success) |
| 2419 | return false; |
| 2420 | |
| 2421 | AddWithCarryResult res = AddWithCarry(val1, imm32, 0); |
| 2422 | |
| 2423 | EmulateInstruction::Context context; |
| 2424 | context.type = EmulateInstruction::eContextImmediate; |
| 2425 | context.SetNoArgs (); |
| 2426 | |
| 2427 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 2428 | return false; |
| 2429 | } |
| 2430 | return true; |
| 2431 | } |
| 2432 | |
Johnny Chen | d761dcf | 2011-02-17 22:03:29 +0000 | [diff] [blame] | 2433 | // This instruction adds a register value and an optionally-shifted register value, and writes the result |
| 2434 | // to the destination register. It can optionally update the condition flags based on the result. |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2435 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2436 | EmulateInstructionARM::EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2437 | { |
| 2438 | #if 0 |
| 2439 | // ARM pseudo code... |
| 2440 | if ConditionPassed() then |
| 2441 | EncodingSpecificOperations(); |
| 2442 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2443 | (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); |
| 2444 | if d == 15 then |
| 2445 | ALUWritePC(result); // setflags is always FALSE here |
| 2446 | else |
| 2447 | R[d] = result; |
| 2448 | if setflags then |
| 2449 | APSR.N = result<31>; |
| 2450 | APSR.Z = IsZeroBit(result); |
| 2451 | APSR.C = carry; |
| 2452 | APSR.V = overflow; |
| 2453 | #endif |
| 2454 | |
| 2455 | bool success = false; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2456 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2457 | if (ConditionPassed(opcode)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2458 | { |
| 2459 | uint32_t Rd, Rn, Rm; |
Johnny Chen | d761dcf | 2011-02-17 22:03:29 +0000 | [diff] [blame] | 2460 | ARM_ShifterType shift_t; |
| 2461 | uint32_t shift_n; // the shift applied to the value read from Rm |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 2462 | bool setflags; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2463 | switch (encoding) |
| 2464 | { |
Johnny Chen | d761dcf | 2011-02-17 22:03:29 +0000 | [diff] [blame] | 2465 | case eEncodingT1: |
| 2466 | Rd = Bits32(opcode, 2, 0); |
| 2467 | Rn = Bits32(opcode, 5, 3); |
| 2468 | Rm = Bits32(opcode, 8, 6); |
| 2469 | setflags = !InITBlock(); |
| 2470 | shift_t = SRType_LSL; |
| 2471 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2472 | break; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2473 | case eEncodingT2: |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 2474 | Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2475 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 2476 | setflags = false; |
Johnny Chen | d761dcf | 2011-02-17 22:03:29 +0000 | [diff] [blame] | 2477 | shift_t = SRType_LSL; |
| 2478 | shift_n = 0; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2479 | if (Rn == 15 && Rm == 15) |
| 2480 | return false; |
Johnny Chen | d761dcf | 2011-02-17 22:03:29 +0000 | [diff] [blame] | 2481 | if (Rd == 15 && InITBlock() && !LastInITBlock()) |
| 2482 | return false; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2483 | break; |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2484 | case eEncodingA1: |
| 2485 | Rd = Bits32(opcode, 15, 12); |
| 2486 | Rn = Bits32(opcode, 19, 16); |
| 2487 | Rm = Bits32(opcode, 3, 0); |
| 2488 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 2489 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2490 | break; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2491 | default: |
| 2492 | return false; |
| 2493 | } |
| 2494 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2495 | // Read the first operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 2496 | uint32_t val1 = ReadCoreReg(Rn, &success); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2497 | if (!success) |
| 2498 | return false; |
| 2499 | |
| 2500 | // Read the second operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 2501 | uint32_t val2 = ReadCoreReg(Rm, &success); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2502 | if (!success) |
| 2503 | return false; |
| 2504 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 2505 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 2506 | AddWithCarryResult res = AddWithCarry(val1, shifted, 0); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2507 | |
| 2508 | EmulateInstruction::Context context; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 2509 | context.type = EmulateInstruction::eContextAddition; |
| 2510 | Register op1_reg; |
| 2511 | Register op2_reg; |
| 2512 | op1_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn); |
| 2513 | op2_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 2514 | context.SetRegisterRegisterOperands (op1_reg, op2_reg); |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 2515 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 2516 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 2517 | return false; |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 2518 | } |
| 2519 | return true; |
| 2520 | } |
| 2521 | |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2522 | // Compare Negative (immediate) adds a register value and an immediate value. |
| 2523 | // It updates the condition flags based on the result, and discards the result. |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2524 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2525 | EmulateInstructionARM::EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2526 | { |
| 2527 | #if 0 |
| 2528 | // ARM pseudo code... |
| 2529 | if ConditionPassed() then |
| 2530 | EncodingSpecificOperations(); |
| 2531 | (result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); |
| 2532 | APSR.N = result<31>; |
| 2533 | APSR.Z = IsZeroBit(result); |
| 2534 | APSR.C = carry; |
| 2535 | APSR.V = overflow; |
| 2536 | #endif |
| 2537 | |
| 2538 | bool success = false; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2539 | |
| 2540 | uint32_t Rn; // the first operand |
| 2541 | uint32_t imm32; // the immediate value to be compared with |
| 2542 | switch (encoding) { |
| 2543 | case eEncodingT1: |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2544 | Rn = Bits32(opcode, 19, 16); |
| 2545 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 2546 | if (Rn == 15) |
| 2547 | return false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2548 | break; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2549 | case eEncodingA1: |
| 2550 | Rn = Bits32(opcode, 19, 16); |
| 2551 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 2552 | break; |
| 2553 | default: |
| 2554 | return false; |
| 2555 | } |
| 2556 | // Read the register value from the operand register Rn. |
| 2557 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 2558 | if (!success) |
| 2559 | return false; |
| 2560 | |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2561 | AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0); |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2562 | |
| 2563 | EmulateInstruction::Context context; |
| 2564 | context.type = EmulateInstruction::eContextImmediate; |
| 2565 | context.SetNoArgs (); |
| 2566 | if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) |
| 2567 | return false; |
| 2568 | |
| 2569 | return true; |
| 2570 | } |
| 2571 | |
| 2572 | // Compare Negative (register) adds a register value and an optionally-shifted register value. |
| 2573 | // It updates the condition flags based on the result, and discards the result. |
| 2574 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2575 | EmulateInstructionARM::EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2576 | { |
| 2577 | #if 0 |
| 2578 | // ARM pseudo code... |
| 2579 | if ConditionPassed() then |
| 2580 | EncodingSpecificOperations(); |
| 2581 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2582 | (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); |
| 2583 | APSR.N = result<31>; |
| 2584 | APSR.Z = IsZeroBit(result); |
| 2585 | APSR.C = carry; |
| 2586 | APSR.V = overflow; |
| 2587 | #endif |
| 2588 | |
| 2589 | bool success = false; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2590 | |
| 2591 | uint32_t Rn; // the first operand |
| 2592 | uint32_t Rm; // the second operand |
| 2593 | ARM_ShifterType shift_t; |
| 2594 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 2595 | switch (encoding) { |
| 2596 | case eEncodingT1: |
| 2597 | Rn = Bits32(opcode, 2, 0); |
| 2598 | Rm = Bits32(opcode, 5, 3); |
| 2599 | shift_t = SRType_LSL; |
| 2600 | shift_n = 0; |
| 2601 | break; |
| 2602 | case eEncodingT2: |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2603 | Rn = Bits32(opcode, 19, 16); |
| 2604 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 2605 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2606 | // if n == 15 || BadReg(m) then UNPREDICTABLE; |
| 2607 | if (Rn == 15 || BadReg(Rm)) |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2608 | return false; |
| 2609 | break; |
| 2610 | case eEncodingA1: |
| 2611 | Rn = Bits32(opcode, 19, 16); |
| 2612 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 2613 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2614 | break; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2615 | default: |
| 2616 | return false; |
| 2617 | } |
| 2618 | // Read the register value from register Rn. |
| 2619 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 2620 | if (!success) |
| 2621 | return false; |
| 2622 | |
| 2623 | // Read the register value from register Rm. |
| 2624 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 2625 | if (!success) |
| 2626 | return false; |
| 2627 | |
| 2628 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2629 | AddWithCarryResult res = AddWithCarry(val1, shifted, 0); |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2630 | |
| 2631 | EmulateInstruction::Context context; |
| 2632 | context.type = EmulateInstruction::eContextImmediate; |
| 2633 | context.SetNoArgs(); |
| 2634 | if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) |
| 2635 | return false; |
| 2636 | |
| 2637 | return true; |
| 2638 | } |
| 2639 | |
| 2640 | // Compare (immediate) subtracts an immediate value from a register value. |
| 2641 | // It updates the condition flags based on the result, and discards the result. |
| 2642 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2643 | EmulateInstructionARM::EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2644 | { |
| 2645 | #if 0 |
| 2646 | // ARM pseudo code... |
| 2647 | if ConditionPassed() then |
| 2648 | EncodingSpecificOperations(); |
| 2649 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 2650 | APSR.N = result<31>; |
| 2651 | APSR.Z = IsZeroBit(result); |
| 2652 | APSR.C = carry; |
| 2653 | APSR.V = overflow; |
| 2654 | #endif |
| 2655 | |
| 2656 | bool success = false; |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2657 | |
| 2658 | uint32_t Rn; // the first operand |
| 2659 | uint32_t imm32; // the immediate value to be compared with |
| 2660 | switch (encoding) { |
| 2661 | case eEncodingT1: |
| 2662 | Rn = Bits32(opcode, 10, 8); |
| 2663 | imm32 = Bits32(opcode, 7, 0); |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2664 | break; |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 2665 | case eEncodingT2: |
| 2666 | Rn = Bits32(opcode, 19, 16); |
| 2667 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 2668 | if (Rn == 15) |
| 2669 | return false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2670 | break; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2671 | case eEncodingA1: |
| 2672 | Rn = Bits32(opcode, 19, 16); |
| 2673 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2674 | break; |
| 2675 | default: |
| 2676 | return false; |
| 2677 | } |
| 2678 | // Read the register value from the operand register Rn. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 2679 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2680 | if (!success) |
| 2681 | return false; |
| 2682 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 2683 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 2684 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2685 | EmulateInstruction::Context context; |
| 2686 | context.type = EmulateInstruction::eContextImmediate; |
| 2687 | context.SetNoArgs (); |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 2688 | if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) |
| 2689 | return false; |
| 2690 | |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2691 | return true; |
| 2692 | } |
| 2693 | |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2694 | // Compare (register) subtracts an optionally-shifted register value from a register value. |
| 2695 | // It updates the condition flags based on the result, and discards the result. |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2696 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2697 | EmulateInstructionARM::EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2698 | { |
| 2699 | #if 0 |
| 2700 | // ARM pseudo code... |
| 2701 | if ConditionPassed() then |
| 2702 | EncodingSpecificOperations(); |
| 2703 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2704 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); |
| 2705 | APSR.N = result<31>; |
| 2706 | APSR.Z = IsZeroBit(result); |
| 2707 | APSR.C = carry; |
| 2708 | APSR.V = overflow; |
| 2709 | #endif |
| 2710 | |
| 2711 | bool success = false; |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2712 | |
| 2713 | uint32_t Rn; // the first operand |
| 2714 | uint32_t Rm; // the second operand |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2715 | ARM_ShifterType shift_t; |
| 2716 | uint32_t shift_n; // the shift applied to the value read from Rm |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2717 | switch (encoding) { |
| 2718 | case eEncodingT1: |
| 2719 | Rn = Bits32(opcode, 2, 0); |
| 2720 | Rm = Bits32(opcode, 5, 3); |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2721 | shift_t = SRType_LSL; |
| 2722 | shift_n = 0; |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2723 | break; |
| 2724 | case eEncodingT2: |
| 2725 | Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
| 2726 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2727 | shift_t = SRType_LSL; |
| 2728 | shift_n = 0; |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2729 | if (Rn < 8 && Rm < 8) |
| 2730 | return false; |
| 2731 | if (Rn == 15 || Rm == 15) |
| 2732 | return false; |
| 2733 | break; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2734 | case eEncodingA1: |
| 2735 | Rn = Bits32(opcode, 19, 16); |
| 2736 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 2737 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 2738 | break; |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2739 | default: |
| 2740 | return false; |
| 2741 | } |
| 2742 | // Read the register value from register Rn. |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2743 | uint32_t val1 = ReadCoreReg(Rn, &success); |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2744 | if (!success) |
| 2745 | return false; |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2746 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2747 | // Read the register value from register Rm. |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2748 | uint32_t val2 = ReadCoreReg(Rm, &success); |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2749 | if (!success) |
| 2750 | return false; |
| 2751 | |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 2752 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
| 2753 | AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1); |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 2754 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2755 | EmulateInstruction::Context context; |
| 2756 | context.type = EmulateInstruction::eContextImmediate; |
| 2757 | context.SetNoArgs(); |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 2758 | if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) |
| 2759 | return false; |
| 2760 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2761 | return true; |
| 2762 | } |
| 2763 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2764 | // Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, |
| 2765 | // shifting in copies of its sign bit, and writes the result to the destination register. It can |
| 2766 | // optionally update the condition flags based on the result. |
| 2767 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2768 | EmulateInstructionARM::EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2769 | { |
| 2770 | #if 0 |
| 2771 | // ARM pseudo code... |
| 2772 | if ConditionPassed() then |
| 2773 | EncodingSpecificOperations(); |
| 2774 | (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C); |
| 2775 | if d == 15 then // Can only occur for ARM encoding |
| 2776 | ALUWritePC(result); // setflags is always FALSE here |
| 2777 | else |
| 2778 | R[d] = result; |
| 2779 | if setflags then |
| 2780 | APSR.N = result<31>; |
| 2781 | APSR.Z = IsZeroBit(result); |
| 2782 | APSR.C = carry; |
| 2783 | // APSR.V unchanged |
| 2784 | #endif |
| 2785 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2786 | return EmulateShiftImm (opcode, encoding, SRType_ASR); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2787 | } |
| 2788 | |
| 2789 | // Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, |
| 2790 | // shifting in copies of its sign bit, and writes the result to the destination register. |
| 2791 | // The variable number of bits is read from the bottom byte of a register. It can optionally update |
| 2792 | // the condition flags based on the result. |
| 2793 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2794 | EmulateInstructionARM::EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2795 | { |
| 2796 | #if 0 |
| 2797 | // ARM pseudo code... |
| 2798 | if ConditionPassed() then |
| 2799 | EncodingSpecificOperations(); |
| 2800 | shift_n = UInt(R[m]<7:0>); |
| 2801 | (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C); |
| 2802 | R[d] = result; |
| 2803 | if setflags then |
| 2804 | APSR.N = result<31>; |
| 2805 | APSR.Z = IsZeroBit(result); |
| 2806 | APSR.C = carry; |
| 2807 | // APSR.V unchanged |
| 2808 | #endif |
| 2809 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2810 | return EmulateShiftReg (opcode, encoding, SRType_ASR); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2811 | } |
| 2812 | |
| 2813 | // Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, |
| 2814 | // shifting in zeros, and writes the result to the destination register. It can optionally |
| 2815 | // update the condition flags based on the result. |
| 2816 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2817 | EmulateInstructionARM::EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2818 | { |
| 2819 | #if 0 |
| 2820 | // ARM pseudo code... |
| 2821 | if ConditionPassed() then |
| 2822 | EncodingSpecificOperations(); |
| 2823 | (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C); |
| 2824 | if d == 15 then // Can only occur for ARM encoding |
| 2825 | ALUWritePC(result); // setflags is always FALSE here |
| 2826 | else |
| 2827 | R[d] = result; |
| 2828 | if setflags then |
| 2829 | APSR.N = result<31>; |
| 2830 | APSR.Z = IsZeroBit(result); |
| 2831 | APSR.C = carry; |
| 2832 | // APSR.V unchanged |
| 2833 | #endif |
| 2834 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2835 | return EmulateShiftImm (opcode, encoding, SRType_LSL); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2836 | } |
| 2837 | |
| 2838 | // Logical Shift Left (register) shifts a register value left by a variable number of bits, |
| 2839 | // shifting in zeros, and writes the result to the destination register. The variable number |
| 2840 | // of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2841 | // flags based on the result. |
| 2842 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2843 | EmulateInstructionARM::EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2844 | { |
| 2845 | #if 0 |
| 2846 | // ARM pseudo code... |
| 2847 | if ConditionPassed() then |
| 2848 | EncodingSpecificOperations(); |
| 2849 | shift_n = UInt(R[m]<7:0>); |
| 2850 | (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C); |
| 2851 | R[d] = result; |
| 2852 | if setflags then |
| 2853 | APSR.N = result<31>; |
| 2854 | APSR.Z = IsZeroBit(result); |
| 2855 | APSR.C = carry; |
| 2856 | // APSR.V unchanged |
| 2857 | #endif |
| 2858 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2859 | return EmulateShiftReg (opcode, encoding, SRType_LSL); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2860 | } |
| 2861 | |
| 2862 | // Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, |
| 2863 | // shifting in zeros, and writes the result to the destination register. It can optionally |
| 2864 | // update the condition flags based on the result. |
| 2865 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2866 | EmulateInstructionARM::EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2867 | { |
| 2868 | #if 0 |
| 2869 | // ARM pseudo code... |
| 2870 | if ConditionPassed() then |
| 2871 | EncodingSpecificOperations(); |
| 2872 | (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C); |
| 2873 | if d == 15 then // Can only occur for ARM encoding |
| 2874 | ALUWritePC(result); // setflags is always FALSE here |
| 2875 | else |
| 2876 | R[d] = result; |
| 2877 | if setflags then |
| 2878 | APSR.N = result<31>; |
| 2879 | APSR.Z = IsZeroBit(result); |
| 2880 | APSR.C = carry; |
| 2881 | // APSR.V unchanged |
| 2882 | #endif |
| 2883 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2884 | return EmulateShiftImm (opcode, encoding, SRType_LSR); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2885 | } |
| 2886 | |
| 2887 | // Logical Shift Right (register) shifts a register value right by a variable number of bits, |
| 2888 | // shifting in zeros, and writes the result to the destination register. The variable number |
| 2889 | // of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2890 | // flags based on the result. |
| 2891 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2892 | EmulateInstructionARM::EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2893 | { |
| 2894 | #if 0 |
| 2895 | // ARM pseudo code... |
| 2896 | if ConditionPassed() then |
| 2897 | EncodingSpecificOperations(); |
| 2898 | shift_n = UInt(R[m]<7:0>); |
| 2899 | (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C); |
| 2900 | R[d] = result; |
| 2901 | if setflags then |
| 2902 | APSR.N = result<31>; |
| 2903 | APSR.Z = IsZeroBit(result); |
| 2904 | APSR.C = carry; |
| 2905 | // APSR.V unchanged |
| 2906 | #endif |
| 2907 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2908 | return EmulateShiftReg (opcode, encoding, SRType_LSR); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2909 | } |
| 2910 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2911 | // Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. |
| 2912 | // The bits that are rotated off the right end are inserted into the vacated bit positions on the left. |
| 2913 | // It can optionally update the condition flags based on the result. |
| 2914 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2915 | EmulateInstructionARM::EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2916 | { |
| 2917 | #if 0 |
| 2918 | // ARM pseudo code... |
| 2919 | if ConditionPassed() then |
| 2920 | EncodingSpecificOperations(); |
| 2921 | (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C); |
| 2922 | if d == 15 then // Can only occur for ARM encoding |
| 2923 | ALUWritePC(result); // setflags is always FALSE here |
| 2924 | else |
| 2925 | R[d] = result; |
| 2926 | if setflags then |
| 2927 | APSR.N = result<31>; |
| 2928 | APSR.Z = IsZeroBit(result); |
| 2929 | APSR.C = carry; |
| 2930 | // APSR.V unchanged |
| 2931 | #endif |
| 2932 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2933 | return EmulateShiftImm (opcode, encoding, SRType_ROR); |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2934 | } |
| 2935 | |
| 2936 | // Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. |
| 2937 | // The bits that are rotated off the right end are inserted into the vacated bit positions on the left. |
| 2938 | // The variable number of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2939 | // flags based on the result. |
| 2940 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2941 | EmulateInstructionARM::EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2942 | { |
| 2943 | #if 0 |
| 2944 | // ARM pseudo code... |
| 2945 | if ConditionPassed() then |
| 2946 | EncodingSpecificOperations(); |
| 2947 | shift_n = UInt(R[m]<7:0>); |
| 2948 | (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C); |
| 2949 | R[d] = result; |
| 2950 | if setflags then |
| 2951 | APSR.N = result<31>; |
| 2952 | APSR.Z = IsZeroBit(result); |
| 2953 | APSR.C = carry; |
| 2954 | // APSR.V unchanged |
| 2955 | #endif |
| 2956 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2957 | return EmulateShiftReg (opcode, encoding, SRType_ROR); |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2958 | } |
| 2959 | |
| 2960 | // Rotate Right with Extend provides the value of the contents of a register shifted right by one place, |
| 2961 | // with the carry flag shifted into bit [31]. |
| 2962 | // |
| 2963 | // RRX can optionally update the condition flags based on the result. |
| 2964 | // In that case, bit [0] is shifted into the carry flag. |
| 2965 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2966 | EmulateInstructionARM::EmulateRRX (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2967 | { |
| 2968 | #if 0 |
| 2969 | // ARM pseudo code... |
| 2970 | if ConditionPassed() then |
| 2971 | EncodingSpecificOperations(); |
| 2972 | (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C); |
| 2973 | if d == 15 then // Can only occur for ARM encoding |
| 2974 | ALUWritePC(result); // setflags is always FALSE here |
| 2975 | else |
| 2976 | R[d] = result; |
| 2977 | if setflags then |
| 2978 | APSR.N = result<31>; |
| 2979 | APSR.Z = IsZeroBit(result); |
| 2980 | APSR.C = carry; |
| 2981 | // APSR.V unchanged |
| 2982 | #endif |
| 2983 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2984 | return EmulateShiftImm (opcode, encoding, SRType_RRX); |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2985 | } |
| 2986 | |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2987 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2988 | EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2989 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 2990 | assert(shift_type == SRType_ASR |
| 2991 | || shift_type == SRType_LSL |
| 2992 | || shift_type == SRType_LSR |
| 2993 | || shift_type == SRType_ROR |
| 2994 | || shift_type == SRType_RRX); |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2995 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2996 | bool success = false; |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2997 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 2998 | if (ConditionPassed(opcode)) |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2999 | { |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3000 | uint32_t Rd; // the destination register |
| 3001 | uint32_t Rm; // the first operand register |
| 3002 | uint32_t imm5; // encoding for the shift amount |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3003 | uint32_t carry; // the carry bit after the shift operation |
| 3004 | bool setflags; |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3005 | |
| 3006 | // Special case handling! |
| 3007 | // A8.6.139 ROR (immediate) -- Encoding T1 |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3008 | ARMEncoding use_encoding = encoding; |
| 3009 | if (shift_type == SRType_ROR && use_encoding == eEncodingT1) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3010 | { |
| 3011 | // Morph the T1 encoding from the ARM Architecture Manual into T2 encoding to |
| 3012 | // have the same decoding of bit fields as the other Thumb2 shift operations. |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3013 | use_encoding = eEncodingT2; |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3014 | } |
| 3015 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3016 | switch (use_encoding) { |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3017 | case eEncodingT1: |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3018 | // Due to the above special case handling! |
| 3019 | assert(shift_type != SRType_ROR); |
| 3020 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3021 | Rd = Bits32(opcode, 2, 0); |
| 3022 | Rm = Bits32(opcode, 5, 3); |
| 3023 | setflags = !InITBlock(); |
| 3024 | imm5 = Bits32(opcode, 10, 6); |
| 3025 | break; |
| 3026 | case eEncodingT2: |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3027 | // A8.6.141 RRX |
| 3028 | assert(shift_type != SRType_RRX); |
| 3029 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3030 | Rd = Bits32(opcode, 11, 8); |
| 3031 | Rm = Bits32(opcode, 3, 0); |
| 3032 | setflags = BitIsSet(opcode, 20); |
| 3033 | imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); |
| 3034 | if (BadReg(Rd) || BadReg(Rm)) |
| 3035 | return false; |
| 3036 | break; |
| 3037 | case eEncodingA1: |
| 3038 | Rd = Bits32(opcode, 15, 12); |
| 3039 | Rm = Bits32(opcode, 3, 0); |
| 3040 | setflags = BitIsSet(opcode, 20); |
| 3041 | imm5 = Bits32(opcode, 11, 7); |
| 3042 | break; |
| 3043 | default: |
| 3044 | return false; |
| 3045 | } |
| 3046 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3047 | // A8.6.139 ROR (immediate) |
| 3048 | if (shift_type == SRType_ROR && imm5 == 0) |
| 3049 | shift_type = SRType_RRX; |
| 3050 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3051 | // Get the first operand. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 3052 | uint32_t value = ReadCoreReg (Rm, &success); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3053 | if (!success) |
| 3054 | return false; |
| 3055 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 3056 | // Decode the shift amount if not RRX. |
| 3057 | uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3058 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 3059 | uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3060 | |
| 3061 | // The context specifies that an immediate is to be moved into Rd. |
| 3062 | EmulateInstruction::Context context; |
| 3063 | context.type = EmulateInstruction::eContextImmediate; |
| 3064 | context.SetNoArgs (); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3065 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 3066 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 3067 | return false; |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 3068 | } |
| 3069 | return true; |
| 3070 | } |
| 3071 | |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3072 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3073 | EmulateInstructionARM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3074 | { |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 3075 | assert(shift_type == SRType_ASR || shift_type == SRType_LSL || shift_type == SRType_LSR); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3076 | |
| 3077 | bool success = false; |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3078 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3079 | if (ConditionPassed(opcode)) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3080 | { |
| 3081 | uint32_t Rd; // the destination register |
| 3082 | uint32_t Rn; // the first operand register |
| 3083 | uint32_t Rm; // the register whose bottom byte contains the amount to shift by |
| 3084 | uint32_t carry; // the carry bit after the shift operation |
| 3085 | bool setflags; |
| 3086 | switch (encoding) { |
| 3087 | case eEncodingT1: |
| 3088 | Rd = Bits32(opcode, 2, 0); |
| 3089 | Rn = Rd; |
| 3090 | Rm = Bits32(opcode, 5, 3); |
| 3091 | setflags = !InITBlock(); |
| 3092 | break; |
| 3093 | case eEncodingT2: |
| 3094 | Rd = Bits32(opcode, 11, 8); |
| 3095 | Rn = Bits32(opcode, 19, 16); |
| 3096 | Rm = Bits32(opcode, 3, 0); |
| 3097 | setflags = BitIsSet(opcode, 20); |
| 3098 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 3099 | return false; |
| 3100 | break; |
| 3101 | case eEncodingA1: |
| 3102 | Rd = Bits32(opcode, 15, 12); |
| 3103 | Rn = Bits32(opcode, 3, 0); |
| 3104 | Rm = Bits32(opcode, 11, 8); |
| 3105 | setflags = BitIsSet(opcode, 20); |
| 3106 | if (Rd == 15 || Rn == 15 || Rm == 15) |
| 3107 | return false; |
| 3108 | break; |
| 3109 | default: |
| 3110 | return false; |
| 3111 | } |
| 3112 | |
| 3113 | // Get the first operand. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 3114 | uint32_t value = ReadCoreReg (Rn, &success); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3115 | if (!success) |
| 3116 | return false; |
| 3117 | // Get the Rm register content. |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 3118 | uint32_t val = ReadCoreReg (Rm, &success); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3119 | if (!success) |
| 3120 | return false; |
| 3121 | |
| 3122 | // Get the shift amount. |
| 3123 | uint32_t amt = Bits32(val, 7, 0); |
| 3124 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 3125 | uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3126 | |
| 3127 | // The context specifies that an immediate is to be moved into Rd. |
| 3128 | EmulateInstruction::Context context; |
| 3129 | context.type = EmulateInstruction::eContextImmediate; |
| 3130 | context.SetNoArgs (); |
| 3131 | |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 3132 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3133 | return false; |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 3134 | } |
| 3135 | return true; |
| 3136 | } |
| 3137 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3138 | // LDM loads multiple registers from consecutive memory locations, using an |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3139 | // address from a base register. Optionally the address just above the highest of those locations |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3140 | // can be written back to the base register. |
| 3141 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3142 | EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3143 | { |
| 3144 | #if 0 |
| 3145 | // ARM pseudo code... |
| 3146 | if ConditionPassed() |
| 3147 | EncodingSpecificOperations(); NullCheckIfThumbEE (n); |
| 3148 | address = R[n]; |
| 3149 | |
| 3150 | for i = 0 to 14 |
| 3151 | if registers<i> == '1' then |
| 3152 | R[i] = MemA[address, 4]; address = address + 4; |
| 3153 | if registers<15> == '1' then |
| 3154 | LoadWritePC (MemA[address, 4]); |
| 3155 | |
| 3156 | if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers); |
| 3157 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 3158 | |
| 3159 | #endif |
| 3160 | |
| 3161 | bool success = false; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3162 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3163 | if (ConditionPassed(opcode)) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3164 | { |
| 3165 | uint32_t n; |
| 3166 | uint32_t registers = 0; |
| 3167 | bool wback; |
| 3168 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3169 | switch (encoding) |
| 3170 | { |
| 3171 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3172 | // n = UInt(Rn); registers = '00000000':register_list; wback = (registers<n> == '0'); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3173 | n = Bits32 (opcode, 10, 8); |
| 3174 | registers = Bits32 (opcode, 7, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3175 | registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3176 | wback = BitIsClear (registers, n); |
| 3177 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 3178 | if (BitCount(registers) < 1) |
| 3179 | return false; |
| 3180 | break; |
| 3181 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3182 | // if W == '1' && Rn == '1101' then SEE POP; |
| 3183 | // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1'); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3184 | n = Bits32 (opcode, 19, 16); |
| 3185 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3186 | registers = registers & 0xdfff; // Make sure bit 13 is zero. |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3187 | wback = BitIsSet (opcode, 21); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3188 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3189 | // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3190 | if ((n == 15) |
| 3191 | || (BitCount (registers) < 2) |
| 3192 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 3193 | return false; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3194 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3195 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 3196 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3197 | return false; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3198 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3199 | // if wback && registers<n> == '1' then UNPREDICTABLE; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3200 | if (wback |
| 3201 | && BitIsSet (registers, n)) |
| 3202 | return false; |
| 3203 | break; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3204 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3205 | case eEncodingA1: |
| 3206 | n = Bits32 (opcode, 19, 16); |
| 3207 | registers = Bits32 (opcode, 15, 0); |
| 3208 | wback = BitIsSet (opcode, 21); |
| 3209 | if ((n == 15) |
| 3210 | || (BitCount (registers) < 1)) |
| 3211 | return false; |
| 3212 | break; |
| 3213 | default: |
| 3214 | return false; |
| 3215 | } |
| 3216 | |
| 3217 | int32_t offset = 0; |
| 3218 | const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3219 | if (!success) |
| 3220 | return false; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3221 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3222 | EmulateInstruction::Context context; |
| 3223 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 3224 | Register dwarf_reg; |
| 3225 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3226 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3227 | |
| 3228 | for (int i = 0; i < 14; ++i) |
| 3229 | { |
| 3230 | if (BitIsSet (registers, i)) |
| 3231 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3232 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3233 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3234 | if (wback && (n == 13)) // Pop Instruction |
| 3235 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 3236 | |
| 3237 | // R[i] = MemA [address, 4]; address = address + 4; |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3238 | uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3239 | if (!success) |
| 3240 | return false; |
| 3241 | |
| 3242 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 3243 | return false; |
| 3244 | |
| 3245 | offset += addr_byte_size; |
| 3246 | } |
| 3247 | } |
| 3248 | |
| 3249 | if (BitIsSet (registers, 15)) |
| 3250 | { |
| 3251 | //LoadWritePC (MemA [address, 4]); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3252 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3253 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3254 | uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3255 | if (!success) |
| 3256 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 3257 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3258 | if (!LoadWritePC(context, data)) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3259 | return false; |
| 3260 | } |
| 3261 | |
| 3262 | if (wback && BitIsClear (registers, n)) |
| 3263 | { |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3264 | // R[n] = R[n] + 4 * BitCount (registers) |
| 3265 | int32_t offset = addr_byte_size * BitCount (registers); |
| 3266 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3267 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3268 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3269 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset)) |
| 3270 | return false; |
| 3271 | } |
| 3272 | if (wback && BitIsSet (registers, n)) |
| 3273 | // R[n] bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3274 | return WriteBits32Unknown (n); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3275 | } |
| 3276 | return true; |
| 3277 | } |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3278 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3279 | // LDMDA loads multiple registers from consecutive memory locations using an address from a base register. |
| 3280 | // The consecutive memory locations end at this address and the address just below the lowest of those locations |
| 3281 | // can optionally be written back to the base register. |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3282 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3283 | EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3284 | { |
| 3285 | #if 0 |
| 3286 | // ARM pseudo code... |
| 3287 | if ConditionPassed() then |
| 3288 | EncodingSpecificOperations(); |
| 3289 | address = R[n] - 4*BitCount(registers) + 4; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3290 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3291 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3292 | if registers<i> == '1' then |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3293 | R[i] = MemA[address,4]; address = address + 4; |
| 3294 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3295 | if registers<15> == '1' then |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3296 | LoadWritePC(MemA[address,4]); |
| 3297 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3298 | if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); |
| 3299 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3300 | #endif |
| 3301 | |
| 3302 | bool success = false; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3303 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3304 | if (ConditionPassed(opcode)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3305 | { |
| 3306 | uint32_t n; |
| 3307 | uint32_t registers = 0; |
| 3308 | bool wback; |
| 3309 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3310 | |
| 3311 | // EncodingSpecificOperations(); |
| 3312 | switch (encoding) |
| 3313 | { |
| 3314 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3315 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3316 | n = Bits32 (opcode, 19, 16); |
| 3317 | registers = Bits32 (opcode, 15, 0); |
| 3318 | wback = BitIsSet (opcode, 21); |
| 3319 | |
| 3320 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3321 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3322 | return false; |
| 3323 | |
| 3324 | break; |
| 3325 | |
| 3326 | default: |
| 3327 | return false; |
| 3328 | } |
| 3329 | // address = R[n] - 4*BitCount(registers) + 4; |
| 3330 | |
| 3331 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3332 | addr_t Rn = ReadCoreReg (n, &success); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3333 | |
| 3334 | if (!success) |
| 3335 | return false; |
| 3336 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3337 | addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3338 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3339 | EmulateInstruction::Context context; |
| 3340 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 3341 | Register dwarf_reg; |
| 3342 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3343 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3344 | |
| 3345 | // for i = 0 to 14 |
| 3346 | for (int i = 0; i < 14; ++i) |
| 3347 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3348 | // if registers<i> == '1' then |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3349 | if (BitIsSet (registers, i)) |
| 3350 | { |
| 3351 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3352 | context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset)); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3353 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3354 | if (!success) |
| 3355 | return false; |
| 3356 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 3357 | return false; |
| 3358 | offset += addr_byte_size; |
| 3359 | } |
| 3360 | } |
| 3361 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3362 | // if registers<15> == '1' then |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3363 | // LoadWritePC(MemA[address,4]); |
| 3364 | if (BitIsSet (registers, 15)) |
| 3365 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3366 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3367 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3368 | if (!success) |
| 3369 | return false; |
Johnny Chen | 44c10f0 | 2011-02-11 19:37:03 +0000 | [diff] [blame] | 3370 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3371 | if (!LoadWritePC(context, data)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3372 | return false; |
| 3373 | } |
| 3374 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3375 | // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3376 | if (wback && BitIsClear (registers, n)) |
| 3377 | { |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3378 | if (!success) |
| 3379 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3380 | |
| 3381 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 3382 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3383 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3384 | addr_t addr = Rn + offset; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3385 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 3386 | return false; |
| 3387 | } |
| 3388 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3389 | // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3390 | if (wback && BitIsSet (registers, n)) |
| 3391 | return WriteBits32Unknown (n); |
| 3392 | } |
| 3393 | return true; |
| 3394 | } |
| 3395 | |
| 3396 | // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 3397 | // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can |
| 3398 | // be optionally written back to the base register. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3399 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3400 | EmulateInstructionARM::EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3401 | { |
| 3402 | #if 0 |
| 3403 | // ARM pseudo code... |
| 3404 | if ConditionPassed() then |
| 3405 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3406 | address = R[n] - 4*BitCount(registers); |
| 3407 | |
| 3408 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3409 | if registers<i> == '1' then |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3410 | R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3411 | if registers<15> == '1' then |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3412 | LoadWritePC(MemA[address,4]); |
| 3413 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3414 | if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); |
| 3415 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3416 | #endif |
| 3417 | |
| 3418 | bool success = false; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3419 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3420 | if (ConditionPassed(opcode)) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3421 | { |
| 3422 | uint32_t n; |
| 3423 | uint32_t registers = 0; |
| 3424 | bool wback; |
| 3425 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3426 | switch (encoding) |
| 3427 | { |
| 3428 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3429 | // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1'); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3430 | n = Bits32 (opcode, 19, 16); |
| 3431 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3432 | registers = registers & 0xdfff; // Make sure bit 13 is a zero. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3433 | wback = BitIsSet (opcode, 21); |
| 3434 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3435 | // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3436 | if ((n == 15) |
| 3437 | || (BitCount (registers) < 2) |
| 3438 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 3439 | return false; |
| 3440 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3441 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 3442 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3443 | return false; |
| 3444 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3445 | // if wback && registers<n> == '1' then UNPREDICTABLE; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3446 | if (wback && BitIsSet (registers, n)) |
| 3447 | return false; |
| 3448 | |
| 3449 | break; |
| 3450 | |
| 3451 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3452 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3453 | n = Bits32 (opcode, 19, 16); |
| 3454 | registers = Bits32 (opcode, 15, 0); |
| 3455 | wback = BitIsSet (opcode, 21); |
| 3456 | |
| 3457 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3458 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3459 | return false; |
| 3460 | |
| 3461 | break; |
| 3462 | |
| 3463 | default: |
| 3464 | return false; |
| 3465 | } |
| 3466 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3467 | // address = R[n] - 4*BitCount(registers); |
| 3468 | |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3469 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3470 | addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3471 | |
| 3472 | if (!success) |
| 3473 | return false; |
| 3474 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3475 | addr_t address = Rn - (addr_byte_size * BitCount (registers)); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3476 | EmulateInstruction::Context context; |
| 3477 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 3478 | Register dwarf_reg; |
| 3479 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3480 | context.SetRegisterPlusOffset (dwarf_reg, Rn - address); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3481 | |
| 3482 | for (int i = 0; i < 14; ++i) |
| 3483 | { |
| 3484 | if (BitIsSet (registers, i)) |
| 3485 | { |
| 3486 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3487 | context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset)); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3488 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3489 | if (!success) |
| 3490 | return false; |
| 3491 | |
| 3492 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 3493 | return false; |
| 3494 | |
| 3495 | offset += addr_byte_size; |
| 3496 | } |
| 3497 | } |
| 3498 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3499 | // if registers<15> == '1' then |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3500 | // LoadWritePC(MemA[address,4]); |
| 3501 | if (BitIsSet (registers, 15)) |
| 3502 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3503 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3504 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3505 | if (!success) |
| 3506 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 3507 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3508 | if (!LoadWritePC(context, data)) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3509 | return false; |
| 3510 | } |
| 3511 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3512 | // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3513 | if (wback && BitIsClear (registers, n)) |
| 3514 | { |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3515 | if (!success) |
| 3516 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3517 | |
| 3518 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 3519 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3520 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3521 | addr_t addr = Rn + offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3522 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 3523 | return false; |
| 3524 | } |
| 3525 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3526 | // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3527 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3528 | return WriteBits32Unknown (n); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3529 | } |
| 3530 | return true; |
| 3531 | } |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3532 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3533 | // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 3534 | // consecutive memory locations start just above this address, and thea ddress of the last of those locations can |
| 3535 | // optinoally be written back to the base register. |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3536 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3537 | EmulateInstructionARM::EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3538 | { |
| 3539 | #if 0 |
| 3540 | if ConditionPassed() then |
| 3541 | EncodingSpecificOperations(); |
| 3542 | address = R[n] + 4; |
| 3543 | |
| 3544 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3545 | if registers<i> == '1' then |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3546 | R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3547 | if registers<15> == '1' then |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3548 | LoadWritePC(MemA[address,4]); |
| 3549 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3550 | if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers); |
| 3551 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3552 | #endif |
| 3553 | |
| 3554 | bool success = false; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3555 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3556 | if (ConditionPassed(opcode)) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3557 | { |
| 3558 | uint32_t n; |
| 3559 | uint32_t registers = 0; |
| 3560 | bool wback; |
| 3561 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3562 | switch (encoding) |
| 3563 | { |
| 3564 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3565 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3566 | n = Bits32 (opcode, 19, 16); |
| 3567 | registers = Bits32 (opcode, 15, 0); |
| 3568 | wback = BitIsSet (opcode, 21); |
| 3569 | |
| 3570 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3571 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3572 | return false; |
| 3573 | |
| 3574 | break; |
| 3575 | default: |
| 3576 | return false; |
| 3577 | } |
| 3578 | // address = R[n] + 4; |
| 3579 | |
| 3580 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3581 | addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3582 | |
| 3583 | if (!success) |
| 3584 | return false; |
| 3585 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3586 | addr_t address = Rn + addr_byte_size; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3587 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3588 | EmulateInstruction::Context context; |
| 3589 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 3590 | Register dwarf_reg; |
| 3591 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3592 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3593 | |
| 3594 | for (int i = 0; i < 14; ++i) |
| 3595 | { |
| 3596 | if (BitIsSet (registers, i)) |
| 3597 | { |
| 3598 | // R[i] = MemA[address,4]; address = address + 4; |
| 3599 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3600 | context.SetRegisterPlusOffset (dwarf_reg, offset + addr_byte_size); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3601 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3602 | if (!success) |
| 3603 | return false; |
| 3604 | |
| 3605 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 3606 | return false; |
| 3607 | |
| 3608 | offset += addr_byte_size; |
| 3609 | } |
| 3610 | } |
| 3611 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3612 | // if registers<15> == '1' then |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3613 | // LoadWritePC(MemA[address,4]); |
| 3614 | if (BitIsSet (registers, 15)) |
| 3615 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3616 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3617 | uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3618 | if (!success) |
| 3619 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 3620 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3621 | if (!LoadWritePC(context, data)) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3622 | return false; |
| 3623 | } |
| 3624 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3625 | // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3626 | if (wback && BitIsClear (registers, n)) |
| 3627 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3628 | if (!success) |
| 3629 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3630 | |
| 3631 | offset = addr_byte_size * BitCount (registers); |
| 3632 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3633 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3634 | addr_t addr = Rn + offset; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3635 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 3636 | return false; |
| 3637 | } |
| 3638 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3639 | // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3640 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3641 | return WriteBits32Unknown (n); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3642 | } |
| 3643 | return true; |
| 3644 | } |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3645 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3646 | // Load Register (immediate) calculates an address from a base register value and |
| 3647 | // an immediate offset, loads a word from memory, and writes to a register. |
| 3648 | // LDR (immediate, Thumb) |
| 3649 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3650 | EmulateInstructionARM::EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3651 | { |
| 3652 | #if 0 |
| 3653 | // ARM pseudo code... |
| 3654 | if (ConditionPassed()) |
| 3655 | { |
| 3656 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 3657 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 3658 | address = if index then offset_addr else R[n]; |
| 3659 | data = MemU[address,4]; |
| 3660 | if wback then R[n] = offset_addr; |
| 3661 | if t == 15 then |
| 3662 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 3663 | elsif UnalignedSupport() || address<1:0> = '00' then |
| 3664 | R[t] = data; |
| 3665 | else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7 |
| 3666 | } |
| 3667 | #endif |
| 3668 | |
| 3669 | bool success = false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3670 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3671 | if (ConditionPassed(opcode)) |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3672 | { |
| 3673 | uint32_t Rt; // the destination register |
| 3674 | uint32_t Rn; // the base register |
| 3675 | uint32_t imm32; // the immediate offset used to form the address |
| 3676 | addr_t offset_addr; // the offset address |
| 3677 | addr_t address; // the calculated address |
| 3678 | uint32_t data; // the literal data value from memory load |
| 3679 | bool add, index, wback; |
| 3680 | switch (encoding) { |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3681 | case eEncodingT1: |
| 3682 | Rt = Bits32(opcode, 5, 3); |
| 3683 | Rn = Bits32(opcode, 2, 0); |
| 3684 | imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); |
| 3685 | // index = TRUE; add = TRUE; wback = FALSE |
| 3686 | add = true; |
| 3687 | index = true; |
| 3688 | wback = false; |
| 3689 | |
| 3690 | break; |
| 3691 | |
| 3692 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3693 | // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32); |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3694 | Rt = Bits32 (opcode, 10, 8); |
| 3695 | Rn = 13; |
| 3696 | imm32 = Bits32 (opcode, 7, 0) << 2; |
| 3697 | |
| 3698 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3699 | index = true; |
| 3700 | add = true; |
| 3701 | wback = false; |
| 3702 | |
| 3703 | break; |
| 3704 | |
| 3705 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3706 | // if Rn == '1111' then SEE LDR (literal); |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3707 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 3708 | Rt = Bits32 (opcode, 15, 12); |
| 3709 | Rn = Bits32 (opcode, 19, 16); |
| 3710 | imm32 = Bits32 (opcode, 11, 0); |
| 3711 | |
| 3712 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3713 | index = true; |
| 3714 | add = true; |
| 3715 | wback = false; |
| 3716 | |
| 3717 | // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 3718 | if ((Rt == 15) && InITBlock() && !LastInITBlock()) |
| 3719 | return false; |
| 3720 | |
| 3721 | break; |
| 3722 | |
| 3723 | case eEncodingT4: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3724 | // if Rn == '1111' then SEE LDR (literal); |
| 3725 | // if P == '1' && U == '1' && W == '0' then SEE LDRT; |
| 3726 | // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP; |
| 3727 | // if P == '0' && W == '0' then UNDEFINED; |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3728 | if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) |
| 3729 | return false; |
| 3730 | |
| 3731 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 3732 | Rt = Bits32 (opcode, 15, 12); |
| 3733 | Rn = Bits32 (opcode, 19, 16); |
| 3734 | imm32 = Bits32 (opcode, 7, 0); |
| 3735 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3736 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3737 | index = BitIsSet (opcode, 10); |
| 3738 | add = BitIsSet (opcode, 9); |
| 3739 | wback = BitIsSet (opcode, 8); |
| 3740 | |
| 3741 | // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
| 3742 | if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock())) |
| 3743 | return false; |
| 3744 | |
| 3745 | break; |
| 3746 | |
| 3747 | default: |
| 3748 | return false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3749 | } |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3750 | uint32_t base = ReadCoreReg (Rn, &success); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3751 | if (!success) |
| 3752 | return false; |
| 3753 | if (add) |
| 3754 | offset_addr = base + imm32; |
| 3755 | else |
| 3756 | offset_addr = base - imm32; |
| 3757 | |
| 3758 | address = (index ? offset_addr : base); |
| 3759 | |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3760 | Register base_reg; |
| 3761 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3762 | if (wback) |
| 3763 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3764 | EmulateInstruction::Context ctx; |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3765 | ctx.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 3766 | ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3767 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3768 | if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr)) |
| 3769 | return false; |
| 3770 | } |
| 3771 | |
| 3772 | // Prepare to write to the Rt register. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3773 | EmulateInstruction::Context context; |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3774 | context.type = EmulateInstruction::eContextRegisterLoad; |
| 3775 | context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3776 | |
| 3777 | // Read memory from the address. |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3778 | data = MemURead(context, address, 4, 0, &success); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3779 | if (!success) |
| 3780 | return false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3781 | |
| 3782 | if (Rt == 15) |
| 3783 | { |
| 3784 | if (Bits32(address, 1, 0) == 0) |
| 3785 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3786 | if (!LoadWritePC(context, data)) |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3787 | return false; |
| 3788 | } |
| 3789 | else |
| 3790 | return false; |
| 3791 | } |
| 3792 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 3793 | { |
| 3794 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 3795 | return false; |
| 3796 | } |
| 3797 | else |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 3798 | WriteBits32Unknown (Rt); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3799 | } |
| 3800 | return true; |
| 3801 | } |
| 3802 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3803 | // STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address |
| 3804 | // from a base register. The consecutive memory locations start at this address, and teh address just above the last |
| 3805 | // of those locations can optionally be written back to the base register. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3806 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3807 | EmulateInstructionARM::EmulateSTM (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3808 | { |
| 3809 | #if 0 |
| 3810 | if ConditionPassed() then |
| 3811 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3812 | address = R[n]; |
| 3813 | |
| 3814 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3815 | if registers<i> == '1' then |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3816 | if i == n && wback && i != LowestSetBit(registers) then |
| 3817 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 3818 | else |
| 3819 | MemA[address,4] = R[i]; |
| 3820 | address = address + 4; |
| 3821 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3822 | if registers<15> == '1' then // Only possible for encoding A1 |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3823 | MemA[address,4] = PCStoreValue(); |
| 3824 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3825 | #endif |
| 3826 | |
| 3827 | bool success = false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3828 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3829 | if (ConditionPassed(opcode)) |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3830 | { |
| 3831 | uint32_t n; |
| 3832 | uint32_t registers = 0; |
| 3833 | bool wback; |
| 3834 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3835 | |
| 3836 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3837 | switch (encoding) |
| 3838 | { |
| 3839 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3840 | // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3841 | n = Bits32 (opcode, 10, 8); |
| 3842 | registers = Bits32 (opcode, 7, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3843 | registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3844 | wback = true; |
| 3845 | |
| 3846 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 3847 | if (BitCount (registers) < 1) |
| 3848 | return false; |
| 3849 | |
| 3850 | break; |
| 3851 | |
| 3852 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3853 | // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1'); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3854 | n = Bits32 (opcode, 19, 16); |
| 3855 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3856 | registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3857 | wback = BitIsSet (opcode, 21); |
| 3858 | |
| 3859 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 3860 | if ((n == 15) || (BitCount (registers) < 2)) |
| 3861 | return false; |
| 3862 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3863 | // if wback && registers<n> == '1' then UNPREDICTABLE; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3864 | if (wback && BitIsSet (registers, n)) |
| 3865 | return false; |
| 3866 | |
| 3867 | break; |
| 3868 | |
| 3869 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3870 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3871 | n = Bits32 (opcode, 19, 16); |
| 3872 | registers = Bits32 (opcode, 15, 0); |
| 3873 | wback = BitIsSet (opcode, 21); |
| 3874 | |
| 3875 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3876 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3877 | return false; |
| 3878 | |
| 3879 | break; |
| 3880 | |
| 3881 | default: |
| 3882 | return false; |
| 3883 | } |
| 3884 | |
| 3885 | // address = R[n]; |
| 3886 | int32_t offset = 0; |
| 3887 | const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3888 | if (!success) |
| 3889 | return false; |
| 3890 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3891 | EmulateInstruction::Context context; |
| 3892 | context.type = EmulateInstruction::eContextRegisterStore; |
| 3893 | Register base_reg; |
| 3894 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3895 | |
| 3896 | // for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3897 | int lowest_set_bit = 14; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3898 | for (int i = 0; i < 14; ++i) |
| 3899 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3900 | // if registers<i> == '1' then |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3901 | if (BitIsSet (registers, i)) |
| 3902 | { |
| 3903 | if (i < lowest_set_bit) |
| 3904 | lowest_set_bit = i; |
| 3905 | // if i == n && wback && i != LowestSetBit(registers) then |
| 3906 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 3907 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 3908 | WriteBits32UnknownToMemory (address + offset); |
| 3909 | else |
| 3910 | { |
| 3911 | // MemA[address,4] = R[i]; |
| 3912 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 3913 | if (!success) |
| 3914 | return false; |
| 3915 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3916 | Register data_reg; |
| 3917 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 3918 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 3919 | if (!MemAWrite (context, address + offset, data, addr_byte_size)) |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3920 | return false; |
| 3921 | } |
| 3922 | |
| 3923 | // address = address + 4; |
| 3924 | offset += addr_byte_size; |
| 3925 | } |
| 3926 | } |
| 3927 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3928 | // if registers<15> == '1' then // Only possible for encoding A1 |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3929 | // MemA[address,4] = PCStoreValue(); |
| 3930 | if (BitIsSet (registers, 15)) |
| 3931 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3932 | Register pc_reg; |
| 3933 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 3934 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 3935 | const uint32_t pc = ReadCoreReg (PC_REG, &success); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3936 | if (!success) |
| 3937 | return false; |
| 3938 | |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 3939 | if (!MemAWrite (context, address + offset, pc, addr_byte_size)) |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3940 | return false; |
| 3941 | } |
| 3942 | |
| 3943 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3944 | if (wback) |
| 3945 | { |
| 3946 | offset = addr_byte_size * BitCount (registers); |
| 3947 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3948 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3949 | addr_t data = address + offset; |
| 3950 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3951 | return false; |
| 3952 | } |
| 3953 | } |
| 3954 | return true; |
| 3955 | } |
| 3956 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3957 | // STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address |
| 3958 | // from a base register. The consecutive memory locations end at this address, and the address just below the lowest |
| 3959 | // of those locations can optionally be written back to the base register. |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3960 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3961 | EmulateInstructionARM::EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3962 | { |
| 3963 | #if 0 |
| 3964 | if ConditionPassed() then |
| 3965 | EncodingSpecificOperations(); |
| 3966 | address = R[n] - 4*BitCount(registers) + 4; |
| 3967 | |
| 3968 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3969 | if registers<i> == '1' then |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3970 | if i == n && wback && i != LowestSetBit(registers) then |
| 3971 | MemA[address,4] = bits(32) UNKNOWN; |
| 3972 | else |
| 3973 | MemA[address,4] = R[i]; |
| 3974 | address = address + 4; |
| 3975 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3976 | if registers<15> == '1' then |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3977 | MemA[address,4] = PCStoreValue(); |
| 3978 | |
| 3979 | if wback then R[n] = R[n] - 4*BitCount(registers); |
| 3980 | #endif |
| 3981 | |
| 3982 | bool success = false; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3983 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 3984 | if (ConditionPassed(opcode)) |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3985 | { |
| 3986 | uint32_t n; |
| 3987 | uint32_t registers = 0; |
| 3988 | bool wback; |
| 3989 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3990 | |
| 3991 | // EncodingSpecificOperations(); |
| 3992 | switch (encoding) |
| 3993 | { |
| 3994 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 3995 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3996 | n = Bits32 (opcode, 19, 16); |
| 3997 | registers = Bits32 (opcode, 15, 0); |
| 3998 | wback = BitIsSet (opcode, 21); |
| 3999 | |
| 4000 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 4001 | if ((n == 15) || (BitCount (registers) < 1)) |
| 4002 | return false; |
| 4003 | break; |
| 4004 | default: |
| 4005 | return false; |
| 4006 | } |
| 4007 | |
| 4008 | // address = R[n] - 4*BitCount(registers) + 4; |
| 4009 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4010 | addr_t Rn = ReadCoreReg (n, &success); |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4011 | if (!success) |
| 4012 | return false; |
| 4013 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4014 | addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4015 | |
| 4016 | EmulateInstruction::Context context; |
| 4017 | context.type = EmulateInstruction::eContextRegisterStore; |
| 4018 | Register base_reg; |
| 4019 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4020 | |
| 4021 | // for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4022 | int lowest_bit_set = 14; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4023 | for (int i = 0; i < 14; ++i) |
| 4024 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4025 | // if registers<i> == '1' then |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4026 | if (BitIsSet (registers, i)) |
| 4027 | { |
| 4028 | if (i < lowest_bit_set) |
| 4029 | lowest_bit_set = i; |
| 4030 | //if i == n && wback && i != LowestSetBit(registers) then |
| 4031 | if ((i == n) && wback && (i != lowest_bit_set)) |
| 4032 | // MemA[address,4] = bits(32) UNKNOWN; |
| 4033 | WriteBits32UnknownToMemory (address + offset); |
| 4034 | else |
| 4035 | { |
| 4036 | // MemA[address,4] = R[i]; |
| 4037 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 4038 | if (!success) |
| 4039 | return false; |
| 4040 | |
| 4041 | Register data_reg; |
| 4042 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4043 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset)); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4044 | if (!MemAWrite (context, address + offset, data, addr_byte_size)) |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4045 | return false; |
| 4046 | } |
| 4047 | |
| 4048 | // address = address + 4; |
| 4049 | offset += addr_byte_size; |
| 4050 | } |
| 4051 | } |
| 4052 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4053 | // if registers<15> == '1' then |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4054 | // MemA[address,4] = PCStoreValue(); |
| 4055 | if (BitIsSet (registers, 15)) |
| 4056 | { |
| 4057 | Register pc_reg; |
| 4058 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 4059 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4060 | const uint32_t pc = ReadCoreReg (PC_REG, &success); |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4061 | if (!success) |
| 4062 | return false; |
| 4063 | |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4064 | if (!MemAWrite (context, address + offset, pc, addr_byte_size)) |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4065 | return false; |
| 4066 | } |
| 4067 | |
| 4068 | // if wback then R[n] = R[n] - 4*BitCount(registers); |
| 4069 | if (wback) |
| 4070 | { |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4071 | offset = (addr_byte_size * BitCount (registers)) * -1; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4072 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 4073 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4074 | addr_t data = Rn + offset; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4075 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 4076 | return false; |
| 4077 | } |
| 4078 | } |
| 4079 | return true; |
| 4080 | } |
| 4081 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4082 | // STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address |
| 4083 | // from a base register. The consecutive memory locations end just below this address, and the address of the first of |
| 4084 | // those locations can optionally be written back to the base register. |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4085 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4086 | EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4087 | { |
| 4088 | #if 0 |
| 4089 | if ConditionPassed() then |
| 4090 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4091 | address = R[n] - 4*BitCount(registers); |
| 4092 | |
| 4093 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4094 | if registers<i> == '1' then |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4095 | if i == n && wback && i != LowestSetBit(registers) then |
| 4096 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 4097 | else |
| 4098 | MemA[address,4] = R[i]; |
| 4099 | address = address + 4; |
| 4100 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4101 | if registers<15> == '1' then // Only possible for encoding A1 |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4102 | MemA[address,4] = PCStoreValue(); |
| 4103 | |
| 4104 | if wback then R[n] = R[n] - 4*BitCount(registers); |
| 4105 | #endif |
| 4106 | |
| 4107 | |
| 4108 | bool success = false; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4109 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4110 | if (ConditionPassed(opcode)) |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4111 | { |
| 4112 | uint32_t n; |
| 4113 | uint32_t registers = 0; |
| 4114 | bool wback; |
| 4115 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 4116 | |
| 4117 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4118 | switch (encoding) |
| 4119 | { |
| 4120 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4121 | // if W == '1' && Rn == '1101' then SEE PUSH; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4122 | if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13)) |
| 4123 | { |
| 4124 | // See PUSH |
| 4125 | } |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4126 | // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1'); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4127 | n = Bits32 (opcode, 19, 16); |
| 4128 | registers = Bits32 (opcode, 15, 0); |
| 4129 | registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. |
| 4130 | wback = BitIsSet (opcode, 21); |
| 4131 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 4132 | if ((n == 15) || BitCount (registers) < 2) |
| 4133 | return false; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4134 | // if wback && registers<n> == '1' then UNPREDICTABLE; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4135 | if (wback && BitIsSet (registers, n)) |
| 4136 | return false; |
| 4137 | break; |
| 4138 | |
| 4139 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4140 | // if W == '1' && Rn == '1101’ && BitCount(register_list) >= 2 then SEE PUSH; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4141 | if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2) |
| 4142 | { |
| 4143 | // See Push |
| 4144 | } |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4145 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4146 | n = Bits32 (opcode, 19, 16); |
| 4147 | registers = Bits32 (opcode, 15, 0); |
| 4148 | wback = BitIsSet (opcode, 21); |
| 4149 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 4150 | if ((n == 15) || BitCount (registers) < 1) |
| 4151 | return false; |
| 4152 | break; |
| 4153 | |
| 4154 | default: |
| 4155 | return false; |
| 4156 | } |
| 4157 | |
| 4158 | // address = R[n] - 4*BitCount(registers); |
| 4159 | |
| 4160 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4161 | addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4162 | if (!success) |
| 4163 | return false; |
| 4164 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4165 | addr_t address = Rn - (addr_byte_size * BitCount (registers)); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4166 | |
| 4167 | EmulateInstruction::Context context; |
| 4168 | context.type = EmulateInstruction::eContextRegisterStore; |
| 4169 | Register base_reg; |
| 4170 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4171 | |
| 4172 | // for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4173 | uint32_t lowest_set_bit = 14; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4174 | for (int i = 0; i < 14; ++i) |
| 4175 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4176 | // if registers<i> == '1' then |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4177 | if (BitIsSet (registers, i)) |
| 4178 | { |
| 4179 | if (i < lowest_set_bit) |
| 4180 | lowest_set_bit = i; |
| 4181 | // if i == n && wback && i != LowestSetBit(registers) then |
| 4182 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 4183 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 4184 | WriteBits32UnknownToMemory (address + offset); |
| 4185 | else |
| 4186 | { |
| 4187 | // MemA[address,4] = R[i]; |
| 4188 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 4189 | if (!success) |
| 4190 | return false; |
| 4191 | |
| 4192 | Register data_reg; |
| 4193 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4194 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset)); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4195 | if (!MemAWrite (context, address + offset, data, addr_byte_size)) |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4196 | return false; |
| 4197 | } |
| 4198 | |
| 4199 | // address = address + 4; |
| 4200 | offset += addr_byte_size; |
| 4201 | } |
| 4202 | } |
| 4203 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4204 | // if registers<15> == '1' then // Only possible for encoding A1 |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4205 | // MemA[address,4] = PCStoreValue(); |
| 4206 | if (BitIsSet (registers, 15)) |
| 4207 | { |
| 4208 | Register pc_reg; |
| 4209 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 4210 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4211 | const uint32_t pc = ReadCoreReg (PC_REG, &success); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4212 | if (!success) |
| 4213 | return false; |
| 4214 | |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4215 | if (!MemAWrite (context, address + offset, pc, addr_byte_size)) |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4216 | return false; |
| 4217 | } |
| 4218 | |
| 4219 | // if wback then R[n] = R[n] - 4*BitCount(registers); |
| 4220 | if (wback) |
| 4221 | { |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4222 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 4223 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 4224 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4225 | addr_t data = Rn + offset; |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4226 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 4227 | return false; |
| 4228 | } |
| 4229 | } |
| 4230 | return true; |
| 4231 | } |
| 4232 | |
| 4233 | // STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address |
| 4234 | // from a base register. The consecutive memory locations start just above this address, and the address of the last |
| 4235 | // of those locations can optionally be written back to the base register. |
| 4236 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4237 | EmulateInstructionARM::EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4238 | { |
| 4239 | #if 0 |
| 4240 | if ConditionPassed() then |
| 4241 | EncodingSpecificOperations(); |
| 4242 | address = R[n] + 4; |
| 4243 | |
| 4244 | for i = 0 to 14 |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4245 | if registers<i> == '1' then |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4246 | if i == n && wback && i != LowestSetBit(registers) then |
| 4247 | MemA[address,4] = bits(32) UNKNOWN; |
| 4248 | else |
| 4249 | MemA[address,4] = R[i]; |
| 4250 | address = address + 4; |
| 4251 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4252 | if registers<15> == '1' then |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4253 | MemA[address,4] = PCStoreValue(); |
| 4254 | |
| 4255 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 4256 | #endif |
| 4257 | |
| 4258 | bool success = false; |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4259 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4260 | if (ConditionPassed(opcode)) |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4261 | { |
| 4262 | uint32_t n; |
| 4263 | uint32_t registers = 0; |
| 4264 | bool wback; |
| 4265 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 4266 | |
| 4267 | // EncodingSpecificOperations(); |
| 4268 | switch (encoding) |
| 4269 | { |
| 4270 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4271 | // n = UInt(Rn); registers = register_list; wback = (W == '1'); |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4272 | n = Bits32 (opcode, 19, 16); |
| 4273 | registers = Bits32 (opcode, 15, 0); |
| 4274 | wback = BitIsSet (opcode, 21); |
| 4275 | |
| 4276 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 4277 | if ((n == 15) && (BitCount (registers) < 1)) |
| 4278 | return false; |
| 4279 | break; |
| 4280 | default: |
| 4281 | return false; |
| 4282 | } |
| 4283 | // address = R[n] + 4; |
| 4284 | |
| 4285 | int32_t offset = 0; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4286 | addr_t Rn = ReadCoreReg (n, &success); |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4287 | if (!success) |
| 4288 | return false; |
| 4289 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4290 | addr_t address = Rn + addr_byte_size; |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4291 | |
| 4292 | EmulateInstruction::Context context; |
| 4293 | context.type = EmulateInstruction::eContextRegisterStore; |
| 4294 | Register base_reg; |
| 4295 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4296 | |
| 4297 | uint32_t lowest_set_bit = 14; |
| 4298 | // for i = 0 to 14 |
| 4299 | for (int i = 0; i < 14; ++i) |
| 4300 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4301 | // if registers<i> == '1' then |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4302 | if (BitIsSet (registers, i)) |
| 4303 | { |
| 4304 | if (i < lowest_set_bit) |
| 4305 | lowest_set_bit = i; |
| 4306 | // if i == n && wback && i != LowestSetBit(registers) then |
| 4307 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 4308 | // MemA[address,4] = bits(32) UNKNOWN; |
| 4309 | WriteBits32UnknownToMemory (address + offset); |
| 4310 | // else |
| 4311 | else |
| 4312 | { |
| 4313 | // MemA[address,4] = R[i]; |
| 4314 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 4315 | if (!success) |
| 4316 | return false; |
| 4317 | |
| 4318 | Register data_reg; |
| 4319 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4320 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4321 | if (!MemAWrite (context, address + offset, data, addr_byte_size)) |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4322 | return false; |
| 4323 | } |
| 4324 | |
| 4325 | // address = address + 4; |
| 4326 | offset += addr_byte_size; |
| 4327 | } |
| 4328 | } |
| 4329 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4330 | // if registers<15> == '1' then |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4331 | // MemA[address,4] = PCStoreValue(); |
| 4332 | if (BitIsSet (registers, 15)) |
| 4333 | { |
| 4334 | Register pc_reg; |
| 4335 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 4336 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4337 | const uint32_t pc = ReadCoreReg (PC_REG, &success); |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4338 | if (!success) |
| 4339 | return false; |
| 4340 | |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4341 | if (!MemAWrite (context, address + offset, pc, addr_byte_size)) |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4342 | return false; |
| 4343 | } |
| 4344 | |
| 4345 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 4346 | if (wback) |
| 4347 | { |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4348 | offset = addr_byte_size * BitCount (registers); |
| 4349 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 4350 | context.SetImmediateSigned (offset); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4351 | addr_t data = Rn + offset; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4352 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 4353 | return false; |
| 4354 | } |
| 4355 | } |
| 4356 | return true; |
| 4357 | } |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4358 | |
| 4359 | // STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word |
| 4360 | // from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. |
| 4361 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4362 | EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4363 | { |
| 4364 | #if 0 |
| 4365 | if ConditionPassed() then |
| 4366 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4367 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 4368 | address = if index then offset_addr else R[n]; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4369 | if UnalignedSupport() || address<1:0> == '00' then |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4370 | MemU[address,4] = R[t]; |
| 4371 | else // Can only occur before ARMv7 |
| 4372 | MemU[address,4] = bits(32) UNKNOWN; |
| 4373 | if wback then R[n] = offset_addr; |
| 4374 | #endif |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4375 | |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4376 | bool success = false; |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4377 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4378 | if (ConditionPassed(opcode)) |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4379 | { |
| 4380 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 4381 | |
| 4382 | uint32_t t; |
| 4383 | uint32_t n; |
| 4384 | uint32_t imm32; |
| 4385 | bool index; |
| 4386 | bool add; |
| 4387 | bool wback; |
| 4388 | // EncodingSpecificOperations (); NullCheckIfThumbEE(n); |
| 4389 | switch (encoding) |
| 4390 | { |
| 4391 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4392 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32); |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4393 | t = Bits32 (opcode, 2, 0); |
| 4394 | n = Bits32 (opcode, 5, 3); |
| 4395 | imm32 = Bits32 (opcode, 10, 6) << 2; |
| 4396 | |
| 4397 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4398 | index = true; |
| 4399 | add = false; |
| 4400 | wback = false; |
| 4401 | break; |
| 4402 | |
| 4403 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4404 | // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32); |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4405 | t = Bits32 (opcode, 10, 8); |
| 4406 | n = 13; |
| 4407 | imm32 = Bits32 (opcode, 7, 0) << 2; |
| 4408 | |
| 4409 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4410 | index = true; |
| 4411 | add = true; |
| 4412 | wback = false; |
| 4413 | break; |
| 4414 | |
| 4415 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4416 | // if Rn == '1111' then UNDEFINED; |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4417 | if (Bits32 (opcode, 19, 16) == 15) |
| 4418 | return false; |
| 4419 | |
| 4420 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 4421 | t = Bits32 (opcode, 15, 12); |
| 4422 | n = Bits32 (opcode, 19, 16); |
| 4423 | imm32 = Bits32 (opcode, 11, 0); |
| 4424 | |
| 4425 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4426 | index = true; |
| 4427 | add = true; |
| 4428 | wback = false; |
| 4429 | |
| 4430 | // if t == 15 then UNPREDICTABLE; |
| 4431 | if (t == 15) |
| 4432 | return false; |
| 4433 | break; |
| 4434 | |
| 4435 | case eEncodingT4: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4436 | // if P == '1' && U == '1' && W == '0' then SEE STRT; |
| 4437 | // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH; |
| 4438 | // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4439 | if ((Bits32 (opcode, 19, 16) == 15) |
| 4440 | || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))) |
| 4441 | return false; |
| 4442 | |
| 4443 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 4444 | t = Bits32 (opcode, 15, 12); |
| 4445 | n = Bits32 (opcode, 19, 16); |
| 4446 | imm32 = Bits32 (opcode, 7, 0); |
| 4447 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4448 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4449 | index = BitIsSet (opcode, 10); |
| 4450 | add = BitIsSet (opcode, 9); |
| 4451 | wback = BitIsSet (opcode, 8); |
| 4452 | |
| 4453 | // if t == 15 || (wback && n == t) then UNPREDICTABLE; |
| 4454 | if ((t == 15) || (wback && (n == t))) |
| 4455 | return false; |
| 4456 | break; |
| 4457 | |
| 4458 | default: |
| 4459 | return false; |
| 4460 | } |
| 4461 | |
| 4462 | addr_t offset_addr; |
| 4463 | addr_t address; |
| 4464 | |
| 4465 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 4466 | uint32_t base_address = ReadCoreReg (n, &success); |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4467 | if (!success) |
| 4468 | return false; |
| 4469 | |
| 4470 | if (add) |
| 4471 | offset_addr = base_address + imm32; |
| 4472 | else |
| 4473 | offset_addr = base_address - imm32; |
| 4474 | |
| 4475 | // address = if index then offset_addr else R[n]; |
| 4476 | if (index) |
| 4477 | address = offset_addr; |
| 4478 | else |
| 4479 | address = base_address; |
| 4480 | |
| 4481 | EmulateInstruction::Context context; |
| 4482 | context.type = eContextRegisterStore; |
| 4483 | Register base_reg; |
| 4484 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4485 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4486 | // if UnalignedSupport() || address<1:0> == '00' then |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4487 | if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0))) |
| 4488 | { |
| 4489 | // MemU[address,4] = R[t]; |
| 4490 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 4491 | if (!success) |
| 4492 | return false; |
| 4493 | |
| 4494 | Register data_reg; |
| 4495 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4496 | int32_t offset = address - base_address; |
| 4497 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4498 | if (!MemUWrite (context, address, data, addr_byte_size)) |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4499 | return false; |
| 4500 | } |
| 4501 | else |
| 4502 | { |
| 4503 | // MemU[address,4] = bits(32) UNKNOWN; |
| 4504 | WriteBits32UnknownToMemory (address); |
| 4505 | } |
| 4506 | |
| 4507 | // if wback then R[n] = offset_addr; |
| 4508 | if (wback) |
| 4509 | { |
| 4510 | context.type = eContextRegisterLoad; |
| 4511 | context.SetAddress (offset_addr); |
| 4512 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 4513 | return false; |
| 4514 | } |
| 4515 | } |
| 4516 | return true; |
| 4517 | } |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4518 | |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4519 | // STR (Store Register) calculates an address from a base register value and an offset register value, stores a |
| 4520 | // word from a register to memory. The offset register value can optionally be shifted. |
| 4521 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4522 | EmulateInstructionARM::EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4523 | { |
| 4524 | #if 0 |
| 4525 | if ConditionPassed() then |
| 4526 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4527 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 4528 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 4529 | address = if index then offset_addr else R[n]; |
| 4530 | if t == 15 then // Only possible for encoding A1 |
| 4531 | data = PCStoreValue(); |
| 4532 | else |
| 4533 | data = R[t]; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4534 | if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4535 | MemU[address,4] = data; |
| 4536 | else // Can only occur before ARMv7 |
| 4537 | MemU[address,4] = bits(32) UNKNOWN; |
| 4538 | if wback then R[n] = offset_addr; |
| 4539 | #endif |
| 4540 | |
| 4541 | bool success = false; |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4542 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4543 | if (ConditionPassed(opcode)) |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4544 | { |
| 4545 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 4546 | |
| 4547 | uint32_t t; |
| 4548 | uint32_t n; |
| 4549 | uint32_t m; |
| 4550 | ARM_ShifterType shift_t; |
| 4551 | uint32_t shift_n; |
| 4552 | bool index; |
| 4553 | bool add; |
| 4554 | bool wback; |
| 4555 | |
| 4556 | // EncodingSpecificOperations (); NullCheckIfThumbEE(n); |
| 4557 | switch (encoding) |
| 4558 | { |
| 4559 | case eEncodingT1: |
| 4560 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 4561 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4562 | t = Bits32 (opcode, 2, 0); |
| 4563 | n = Bits32 (opcode, 5, 3); |
| 4564 | m = Bits32 (opcode, 8, 6); |
| 4565 | |
| 4566 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4567 | index = true; |
| 4568 | add = true; |
| 4569 | wback = false; |
| 4570 | |
| 4571 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 4572 | shift_t = SRType_LSL; |
| 4573 | shift_n = 0; |
| 4574 | break; |
| 4575 | |
| 4576 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4577 | // if Rn == '1111' then UNDEFINED; |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4578 | if (Bits32 (opcode, 19, 16) == 15) |
| 4579 | return false; |
| 4580 | |
| 4581 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4582 | t = Bits32 (opcode, 15, 12); |
| 4583 | n = Bits32 (opcode, 19, 16); |
| 4584 | m = Bits32 (opcode, 3, 0); |
| 4585 | |
| 4586 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4587 | index = true; |
| 4588 | add = true; |
| 4589 | wback = false; |
| 4590 | |
| 4591 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 4592 | shift_t = SRType_LSL; |
| 4593 | shift_n = Bits32 (opcode, 5, 4); |
| 4594 | |
| 4595 | // if t == 15 || BadReg(m) then UNPREDICTABLE; |
| 4596 | if ((t == 15) || (BadReg (m))) |
| 4597 | return false; |
| 4598 | break; |
| 4599 | |
| 4600 | case eEncodingA1: |
| 4601 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4602 | // if P == '0' && W == '1' then SEE STRT; |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4603 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4604 | t = Bits32 (opcode, 15, 12); |
| 4605 | n = Bits32 (opcode, 19, 16); |
| 4606 | m = Bits32 (opcode, 3, 0); |
| 4607 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4608 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4609 | index = BitIsSet (opcode, 24); |
| 4610 | add = BitIsSet (opcode, 23); |
| 4611 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 4612 | |
| 4613 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 4614 | uint32_t typ = Bits32 (opcode, 6, 5); |
| 4615 | uint32_t imm5 = Bits32 (opcode, 11, 7); |
| 4616 | shift_n = DecodeImmShift(typ, imm5, shift_t); |
| 4617 | |
| 4618 | // if m == 15 then UNPREDICTABLE; |
| 4619 | if (m == 15) |
| 4620 | return false; |
| 4621 | |
| 4622 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 4623 | if (wback && ((n == 15) || (n == t))) |
| 4624 | return false; |
| 4625 | |
| 4626 | break; |
| 4627 | } |
| 4628 | default: |
| 4629 | return false; |
| 4630 | } |
| 4631 | |
| 4632 | addr_t offset_addr; |
| 4633 | addr_t address; |
| 4634 | int32_t offset = 0; |
| 4635 | |
| 4636 | addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 4637 | if (!success) |
| 4638 | return false; |
| 4639 | |
| 4640 | uint32_t Rm_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 4641 | if (!success) |
| 4642 | return false; |
| 4643 | |
| 4644 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 4645 | offset = Shift (Rm_data, shift_t, shift_n, APSR_C); |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4646 | |
| 4647 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 4648 | if (add) |
| 4649 | offset_addr = base_address + offset; |
| 4650 | else |
| 4651 | offset_addr = base_address - offset; |
| 4652 | |
| 4653 | // address = if index then offset_addr else R[n]; |
| 4654 | if (index) |
| 4655 | address = offset_addr; |
| 4656 | else |
| 4657 | address = base_address; |
| 4658 | |
| 4659 | uint32_t data; |
| 4660 | // if t == 15 then // Only possible for encoding A1 |
| 4661 | if (t == 15) |
| 4662 | // data = PCStoreValue(); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 4663 | data = ReadCoreReg (PC_REG, &success); |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4664 | else |
| 4665 | // data = R[t]; |
| 4666 | data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 4667 | |
| 4668 | if (!success) |
| 4669 | return false; |
| 4670 | |
| 4671 | EmulateInstruction::Context context; |
| 4672 | context.type = eContextRegisterStore; |
| 4673 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4674 | // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4675 | if (UnalignedSupport () |
| 4676 | || (BitIsClear (address, 1) && BitIsClear (address, 0)) |
| 4677 | || CurrentInstrSet() == eModeARM) |
| 4678 | { |
| 4679 | // MemU[address,4] = data; |
| 4680 | |
| 4681 | Register base_reg; |
| 4682 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4683 | |
| 4684 | Register data_reg; |
| 4685 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4686 | |
| 4687 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address); |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4688 | if (!MemUWrite (context, address, data, addr_byte_size)) |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4689 | return false; |
| 4690 | |
| 4691 | } |
| 4692 | else |
| 4693 | // MemU[address,4] = bits(32) UNKNOWN; |
| 4694 | WriteBits32UnknownToMemory (address); |
| 4695 | |
| 4696 | // if wback then R[n] = offset_addr; |
| 4697 | if (wback) |
| 4698 | { |
| 4699 | context.type = eContextRegisterLoad; |
| 4700 | context.SetAddress (offset_addr); |
| 4701 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 4702 | return false; |
| 4703 | } |
| 4704 | |
| 4705 | } |
| 4706 | return true; |
| 4707 | } |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4708 | |
| 4709 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4710 | EmulateInstructionARM::EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4711 | { |
| 4712 | #if 0 |
| 4713 | if ConditionPassed() then |
| 4714 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4715 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 4716 | address = if index then offset_addr else R[n]; |
| 4717 | MemU[address,1] = R[t]<7:0>; |
| 4718 | if wback then R[n] = offset_addr; |
| 4719 | #endif |
| 4720 | |
| 4721 | |
| 4722 | bool success = false; |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4723 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4724 | if (ConditionPassed(opcode)) |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4725 | { |
| 4726 | uint32_t t; |
| 4727 | uint32_t n; |
| 4728 | uint32_t imm32; |
| 4729 | bool index; |
| 4730 | bool add; |
| 4731 | bool wback; |
| 4732 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4733 | switch (encoding) |
| 4734 | { |
| 4735 | case eEncodingT1: |
| 4736 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32); |
| 4737 | t = Bits32 (opcode, 2, 0); |
| 4738 | n = Bits32 (opcode, 5, 3); |
| 4739 | imm32 = Bits32 (opcode, 10, 6); |
| 4740 | |
| 4741 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4742 | index = true; |
| 4743 | add = true; |
| 4744 | wback = false; |
| 4745 | break; |
| 4746 | |
| 4747 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4748 | // if Rn == '1111' then UNDEFINED; |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4749 | if (Bits32 (opcode, 19, 16) == 15) |
| 4750 | return false; |
| 4751 | |
| 4752 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 4753 | t = Bits32 (opcode, 15, 12); |
| 4754 | n = Bits32 (opcode, 19, 16); |
| 4755 | imm32 = Bits32 (opcode, 11, 0); |
| 4756 | |
| 4757 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4758 | index = true; |
| 4759 | add = true; |
| 4760 | wback = false; |
| 4761 | |
| 4762 | // if BadReg(t) then UNPREDICTABLE; |
| 4763 | if (BadReg (t)) |
| 4764 | return false; |
| 4765 | break; |
| 4766 | |
| 4767 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4768 | // if P == '1' && U == '1' && W == '0' then SEE STRBT; |
| 4769 | // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4770 | if (Bits32 (opcode, 19, 16) == 15) |
| 4771 | return false; |
| 4772 | |
| 4773 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 4774 | t = Bits32 (opcode, 15, 12); |
| 4775 | n = Bits32 (opcode, 19, 16); |
| 4776 | imm32 = Bits32 (opcode, 7, 0); |
| 4777 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4778 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4779 | index = BitIsSet (opcode, 10); |
| 4780 | add = BitIsSet (opcode, 9); |
| 4781 | wback = BitIsSet (opcode, 8); |
| 4782 | |
| 4783 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE |
| 4784 | if ((BadReg (t)) || (wback && (n == t))) |
| 4785 | return false; |
| 4786 | break; |
| 4787 | |
| 4788 | default: |
| 4789 | return false; |
| 4790 | } |
| 4791 | |
| 4792 | addr_t offset_addr; |
| 4793 | addr_t address; |
| 4794 | addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 4795 | if (!success) |
| 4796 | return false; |
| 4797 | |
| 4798 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 4799 | if (add) |
| 4800 | offset_addr = base_address + imm32; |
| 4801 | else |
| 4802 | offset_addr = base_address - imm32; |
| 4803 | |
| 4804 | // address = if index then offset_addr else R[n]; |
| 4805 | if (index) |
| 4806 | address = offset_addr; |
| 4807 | else |
| 4808 | address = base_address; |
| 4809 | |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4810 | // MemU[address,1] = R[t]<7:0> |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4811 | Register base_reg; |
| 4812 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4813 | |
| 4814 | Register data_reg; |
| 4815 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4816 | |
| 4817 | EmulateInstruction::Context context; |
| 4818 | context.type = eContextRegisterStore; |
| 4819 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address); |
| 4820 | |
| 4821 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 4822 | if (!success) |
| 4823 | return false; |
| 4824 | |
| 4825 | data = Bits32 (data, 7, 0); |
| 4826 | |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 4827 | if (!MemUWrite (context, address, data, 1)) |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4828 | return false; |
| 4829 | |
| 4830 | // if wback then R[n] = offset_addr; |
| 4831 | if (wback) |
| 4832 | { |
| 4833 | context.type = eContextRegisterLoad; |
| 4834 | context.SetAddress (offset_addr); |
| 4835 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 4836 | return false; |
| 4837 | } |
| 4838 | |
| 4839 | } |
| 4840 | |
| 4841 | return true; |
| 4842 | } |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4843 | |
| 4844 | // STRH (register) calculates an address from a base register value and an offset register value, and stores a |
| 4845 | // halfword from a register to memory. The offset register alue can be shifted left by 0, 1, 2, or 3 bits. |
| 4846 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4847 | EmulateInstructionARM::EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4848 | { |
| 4849 | #if 0 |
| 4850 | if ConditionPassed() then |
| 4851 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4852 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 4853 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 4854 | address = if index then offset_addr else R[n]; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4855 | if UnalignedSupport() || address<0> == '0' then |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4856 | MemU[address,2] = R[t]<15:0>; |
| 4857 | else // Can only occur before ARMv7 |
| 4858 | MemU[address,2] = bits(16) UNKNOWN; |
| 4859 | if wback then R[n] = offset_addr; |
| 4860 | #endif |
| 4861 | |
| 4862 | bool success = false; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4863 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 4864 | if (ConditionPassed(opcode)) |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4865 | { |
| 4866 | uint32_t t; |
| 4867 | uint32_t n; |
| 4868 | uint32_t m; |
| 4869 | bool index; |
| 4870 | bool add; |
| 4871 | bool wback; |
| 4872 | ARM_ShifterType shift_t; |
| 4873 | uint32_t shift_n; |
| 4874 | |
| 4875 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4876 | switch (encoding) |
| 4877 | { |
| 4878 | case eEncodingT1: |
| 4879 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 4880 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4881 | t = Bits32 (opcode, 2, 0); |
| 4882 | n = Bits32 (opcode, 5, 3); |
| 4883 | m = Bits32 (opcode, 8, 6); |
| 4884 | |
| 4885 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4886 | index = true; |
| 4887 | add = true; |
| 4888 | wback = false; |
| 4889 | |
| 4890 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 4891 | shift_t = SRType_LSL; |
| 4892 | shift_n = 0; |
| 4893 | |
| 4894 | break; |
| 4895 | |
| 4896 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4897 | // if Rn == '1111' then UNDEFINED; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4898 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4899 | t = Bits32 (opcode, 15, 12); |
| 4900 | n = Bits32 (opcode, 19, 16); |
| 4901 | m = Bits32 (opcode, 3, 0); |
| 4902 | if (n == 15) |
| 4903 | return false; |
| 4904 | |
| 4905 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4906 | index = true; |
| 4907 | add = true; |
| 4908 | wback = false; |
| 4909 | |
| 4910 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 4911 | shift_t = SRType_LSL; |
| 4912 | shift_n = Bits32 (opcode, 5, 4); |
| 4913 | |
| 4914 | // if BadReg(t) || BadReg(m) then UNPREDICTABLE; |
| 4915 | if (BadReg (t) || BadReg (m)) |
| 4916 | return false; |
| 4917 | |
| 4918 | break; |
| 4919 | |
| 4920 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4921 | // if P == '0' && W == '1' then SEE STRHT; |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4922 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 4923 | t = Bits32 (opcode, 15, 12); |
| 4924 | n = Bits32 (opcode, 19, 16); |
| 4925 | m = Bits32 (opcode, 3, 0); |
| 4926 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4927 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4928 | index = BitIsSet (opcode, 24); |
| 4929 | add = BitIsSet (opcode, 23); |
| 4930 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 4931 | |
| 4932 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 4933 | shift_t = SRType_LSL; |
| 4934 | shift_n = 0; |
| 4935 | |
| 4936 | // if t == 15 || m == 15 then UNPREDICTABLE; |
| 4937 | if ((t == 15) || (m == 15)) |
| 4938 | return false; |
| 4939 | |
| 4940 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 4941 | if (wback && ((n == 15) || (n == t))) |
| 4942 | return false; |
| 4943 | |
| 4944 | break; |
| 4945 | |
| 4946 | default: |
| 4947 | return false; |
| 4948 | } |
| 4949 | |
| 4950 | uint32_t Rm = ReadCoreReg (m, &success); |
| 4951 | if (!success) |
| 4952 | return false; |
| 4953 | |
| 4954 | uint32_t Rn = ReadCoreReg (n, &success); |
| 4955 | if (!success) |
| 4956 | return false; |
| 4957 | |
| 4958 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 4959 | uint32_t offset = Shift (Rm, shift_t, shift_n, APSR_C); |
| 4960 | |
| 4961 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 4962 | addr_t offset_addr; |
| 4963 | if (add) |
| 4964 | offset_addr = Rn + offset; |
| 4965 | else |
| 4966 | offset_addr = Rn - offset; |
| 4967 | |
| 4968 | // address = if index then offset_addr else R[n]; |
| 4969 | addr_t address; |
| 4970 | if (index) |
| 4971 | address = offset_addr; |
| 4972 | else |
| 4973 | address = Rn; |
| 4974 | |
| 4975 | EmulateInstruction::Context context; |
| 4976 | context.type = eContextRegisterStore; |
| 4977 | Register base_reg; |
| 4978 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4979 | Register offset_reg; |
| 4980 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 4981 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 4982 | // if UnalignedSupport() || address<0> == '0' then |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 4983 | if (UnalignedSupport() || BitIsClear (address, 0)) |
| 4984 | { |
| 4985 | // MemU[address,2] = R[t]<15:0>; |
| 4986 | uint32_t Rt = ReadCoreReg (t, &success); |
| 4987 | if (!success) |
| 4988 | return false; |
| 4989 | |
| 4990 | EmulateInstruction::Context context; |
| 4991 | context.type = eContextRegisterStore; |
| 4992 | Register base_reg; |
| 4993 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4994 | Register offset_reg; |
| 4995 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 4996 | Register data_reg; |
| 4997 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4998 | context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg); |
| 4999 | |
| 5000 | if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2)) |
| 5001 | return false; |
| 5002 | } |
| 5003 | else // Can only occur before ARMv7 |
| 5004 | { |
| 5005 | // MemU[address,2] = bits(16) UNKNOWN; |
| 5006 | } |
| 5007 | |
| 5008 | // if wback then R[n] = offset_addr; |
| 5009 | if (wback) |
| 5010 | { |
| 5011 | context.type = eContextAdjustBaseRegister; |
| 5012 | context.SetAddress (offset_addr); |
| 5013 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 5014 | return false; |
| 5015 | } |
| 5016 | } |
| 5017 | |
| 5018 | return true; |
| 5019 | } |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 5020 | |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5021 | // Add with Carry (immediate) adds an immediate value and the carry flag value to a register value, |
| 5022 | // and writes the result to the destination register. It can optionally update the condition flags |
| 5023 | // based on the result. |
| 5024 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5025 | EmulateInstructionARM::EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5026 | { |
| 5027 | #if 0 |
| 5028 | // ARM pseudo code... |
| 5029 | if ConditionPassed() then |
| 5030 | EncodingSpecificOperations(); |
| 5031 | (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C); |
| 5032 | if d == 15 then // Can only occur for ARM encoding |
| 5033 | ALUWritePC(result); // setflags is always FALSE here |
| 5034 | else |
| 5035 | R[d] = result; |
| 5036 | if setflags then |
| 5037 | APSR.N = result<31>; |
| 5038 | APSR.Z = IsZeroBit(result); |
| 5039 | APSR.C = carry; |
| 5040 | APSR.V = overflow; |
| 5041 | #endif |
| 5042 | |
| 5043 | bool success = false; |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5044 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5045 | if (ConditionPassed(opcode)) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5046 | { |
| 5047 | uint32_t Rd, Rn; |
| 5048 | uint32_t imm32; // the immediate value to be added to the value obtained from Rn |
| 5049 | bool setflags; |
| 5050 | switch (encoding) |
| 5051 | { |
| 5052 | case eEncodingT1: |
| 5053 | Rd = Bits32(opcode, 11, 8); |
| 5054 | Rn = Bits32(opcode, 19, 16); |
| 5055 | setflags = BitIsSet(opcode, 20); |
| 5056 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 5057 | if (BadReg(Rd) || BadReg(Rn)) |
| 5058 | return false; |
| 5059 | break; |
| 5060 | case eEncodingA1: |
| 5061 | Rd = Bits32(opcode, 15, 12); |
| 5062 | Rn = Bits32(opcode, 19, 16); |
| 5063 | setflags = BitIsSet(opcode, 20); |
| 5064 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 5065 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5066 | if (Rd == 15 && setflags) |
| 5067 | return false; |
| 5068 | break; |
| 5069 | default: |
| 5070 | return false; |
| 5071 | } |
| 5072 | |
| 5073 | // Read the first operand. |
| 5074 | int32_t val1 = ReadCoreReg(Rn, &success); |
| 5075 | if (!success) |
| 5076 | return false; |
| 5077 | |
| 5078 | AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C); |
| 5079 | |
| 5080 | EmulateInstruction::Context context; |
| 5081 | context.type = EmulateInstruction::eContextImmediate; |
| 5082 | context.SetNoArgs (); |
| 5083 | |
| 5084 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 5085 | return false; |
| 5086 | } |
| 5087 | return true; |
| 5088 | } |
| 5089 | |
| 5090 | // Add with Carry (register) adds a register value, the carry flag value, and an optionally-shifted |
| 5091 | // register value, and writes the result to the destination register. It can optionally update the |
| 5092 | // condition flags based on the result. |
| 5093 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5094 | EmulateInstructionARM::EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5095 | { |
| 5096 | #if 0 |
| 5097 | // ARM pseudo code... |
| 5098 | if ConditionPassed() then |
| 5099 | EncodingSpecificOperations(); |
| 5100 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 5101 | (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C); |
| 5102 | if d == 15 then // Can only occur for ARM encoding |
| 5103 | ALUWritePC(result); // setflags is always FALSE here |
| 5104 | else |
| 5105 | R[d] = result; |
| 5106 | if setflags then |
| 5107 | APSR.N = result<31>; |
| 5108 | APSR.Z = IsZeroBit(result); |
| 5109 | APSR.C = carry; |
| 5110 | APSR.V = overflow; |
| 5111 | #endif |
| 5112 | |
| 5113 | bool success = false; |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5114 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5115 | if (ConditionPassed(opcode)) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5116 | { |
| 5117 | uint32_t Rd, Rn, Rm; |
| 5118 | ARM_ShifterType shift_t; |
| 5119 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 5120 | bool setflags; |
| 5121 | switch (encoding) |
| 5122 | { |
| 5123 | case eEncodingT1: |
| 5124 | Rd = Rn = Bits32(opcode, 2, 0); |
| 5125 | Rm = Bits32(opcode, 5, 3); |
| 5126 | setflags = !InITBlock(); |
| 5127 | shift_t = SRType_LSL; |
| 5128 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 5129 | break; |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5130 | case eEncodingT2: |
| 5131 | Rd = Bits32(opcode, 11, 8); |
| 5132 | Rn = Bits32(opcode, 19, 16); |
| 5133 | Rm = Bits32(opcode, 3, 0); |
| 5134 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 5135 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5136 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 5137 | return false; |
| 5138 | break; |
| 5139 | case eEncodingA1: |
| 5140 | Rd = Bits32(opcode, 15, 12); |
| 5141 | Rn = Bits32(opcode, 19, 16); |
| 5142 | Rm = Bits32(opcode, 3, 0); |
| 5143 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 5144 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5145 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5146 | if (Rd == 15 && setflags) |
| 5147 | return false; |
| 5148 | break; |
| 5149 | default: |
| 5150 | return false; |
| 5151 | } |
| 5152 | |
| 5153 | // Read the first operand. |
| 5154 | int32_t val1 = ReadCoreReg(Rn, &success); |
| 5155 | if (!success) |
| 5156 | return false; |
| 5157 | |
| 5158 | // Read the second operand. |
| 5159 | int32_t val2 = ReadCoreReg(Rm, &success); |
| 5160 | if (!success) |
| 5161 | return false; |
| 5162 | |
| 5163 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
| 5164 | AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C); |
| 5165 | |
| 5166 | EmulateInstruction::Context context; |
| 5167 | context.type = EmulateInstruction::eContextImmediate; |
| 5168 | context.SetNoArgs (); |
| 5169 | |
| 5170 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 5171 | return false; |
| 5172 | } |
| 5173 | return true; |
| 5174 | } |
| 5175 | |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 5176 | // This instruction adds an immediate value to the PC value to form a PC-relative address, |
| 5177 | // and writes the result to the destination register. |
| 5178 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5179 | EmulateInstructionARM::EmulateADR (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 5180 | { |
| 5181 | #if 0 |
| 5182 | // ARM pseudo code... |
| 5183 | if ConditionPassed() then |
| 5184 | EncodingSpecificOperations(); |
| 5185 | result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32); |
| 5186 | if d == 15 then // Can only occur for ARM encodings |
| 5187 | ALUWritePC(result); |
| 5188 | else |
| 5189 | R[d] = result; |
| 5190 | #endif |
| 5191 | |
| 5192 | bool success = false; |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 5193 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5194 | if (ConditionPassed(opcode)) |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 5195 | { |
| 5196 | uint32_t Rd; |
| 5197 | uint32_t imm32; // the immediate value to be added/subtracted to/from the PC |
| 5198 | bool add; |
| 5199 | switch (encoding) |
| 5200 | { |
| 5201 | case eEncodingT1: |
| 5202 | Rd = Bits32(opcode, 10, 8); |
| 5203 | imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32) |
| 5204 | break; |
| 5205 | case eEncodingT2: |
| 5206 | case eEncodingT3: |
| 5207 | Rd = Bits32(opcode, 11, 8); |
| 5208 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 5209 | add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB |
| 5210 | if (BadReg(Rd)) |
| 5211 | return false; |
| 5212 | break; |
| 5213 | case eEncodingA1: |
| 5214 | case eEncodingA2: |
| 5215 | Rd = Bits32(opcode, 15, 12); |
| 5216 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 5217 | add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB |
| 5218 | break; |
| 5219 | default: |
| 5220 | return false; |
| 5221 | } |
| 5222 | |
| 5223 | // Read the PC value. |
| 5224 | uint32_t pc = ReadCoreReg(PC_REG, &success); |
| 5225 | if (!success) |
| 5226 | return false; |
| 5227 | |
| 5228 | uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32); |
| 5229 | |
| 5230 | EmulateInstruction::Context context; |
| 5231 | context.type = EmulateInstruction::eContextImmediate; |
| 5232 | context.SetNoArgs (); |
| 5233 | |
| 5234 | if (!WriteCoreReg(context, result, Rd)) |
| 5235 | return false; |
| 5236 | } |
| 5237 | return true; |
| 5238 | } |
| 5239 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5240 | // This instruction performs a bitwise AND of a register value and an immediate value, and writes the result |
| 5241 | // to the destination register. It can optionally update the condition flags based on the result. |
| 5242 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5243 | EmulateInstructionARM::EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5244 | { |
| 5245 | #if 0 |
| 5246 | // ARM pseudo code... |
| 5247 | if ConditionPassed() then |
| 5248 | EncodingSpecificOperations(); |
| 5249 | result = R[n] AND imm32; |
| 5250 | if d == 15 then // Can only occur for ARM encoding |
| 5251 | ALUWritePC(result); // setflags is always FALSE here |
| 5252 | else |
| 5253 | R[d] = result; |
| 5254 | if setflags then |
| 5255 | APSR.N = result<31>; |
| 5256 | APSR.Z = IsZeroBit(result); |
| 5257 | APSR.C = carry; |
| 5258 | // APSR.V unchanged |
| 5259 | #endif |
| 5260 | |
| 5261 | bool success = false; |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5262 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5263 | if (ConditionPassed(opcode)) |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5264 | { |
| 5265 | uint32_t Rd, Rn; |
| 5266 | uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn |
| 5267 | bool setflags; |
| 5268 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 5269 | switch (encoding) |
| 5270 | { |
| 5271 | case eEncodingT1: |
| 5272 | Rd = Bits32(opcode, 11, 8); |
| 5273 | Rn = Bits32(opcode, 19, 16); |
| 5274 | setflags = BitIsSet(opcode, 20); |
| 5275 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 5276 | // if Rd == '1111' && S == '1' then SEE TST (immediate); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5277 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5278 | return EmulateTSTImm(opcode, eEncodingT1); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5279 | if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) |
| 5280 | return false; |
| 5281 | break; |
| 5282 | case eEncodingA1: |
| 5283 | Rd = Bits32(opcode, 15, 12); |
| 5284 | Rn = Bits32(opcode, 19, 16); |
| 5285 | setflags = BitIsSet(opcode, 20); |
| 5286 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
| 5287 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5288 | if (Rd == 15 && setflags) |
| 5289 | return false; |
| 5290 | break; |
| 5291 | default: |
| 5292 | return false; |
| 5293 | } |
| 5294 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5295 | // Read the first operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5296 | uint32_t val1 = ReadCoreReg(Rn, &success); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5297 | if (!success) |
| 5298 | return false; |
| 5299 | |
| 5300 | uint32_t result = val1 & imm32; |
| 5301 | |
| 5302 | EmulateInstruction::Context context; |
| 5303 | context.type = EmulateInstruction::eContextImmediate; |
| 5304 | context.SetNoArgs (); |
| 5305 | |
| 5306 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 5307 | return false; |
| 5308 | } |
| 5309 | return true; |
| 5310 | } |
| 5311 | |
| 5312 | // This instruction performs a bitwise AND of a register value and an optionally-shifted register value, |
| 5313 | // and writes the result to the destination register. It can optionally update the condition flags |
| 5314 | // based on the result. |
| 5315 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5316 | EmulateInstructionARM::EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5317 | { |
| 5318 | #if 0 |
| 5319 | // ARM pseudo code... |
| 5320 | if ConditionPassed() then |
| 5321 | EncodingSpecificOperations(); |
| 5322 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 5323 | result = R[n] AND shifted; |
| 5324 | if d == 15 then // Can only occur for ARM encoding |
| 5325 | ALUWritePC(result); // setflags is always FALSE here |
| 5326 | else |
| 5327 | R[d] = result; |
| 5328 | if setflags then |
| 5329 | APSR.N = result<31>; |
| 5330 | APSR.Z = IsZeroBit(result); |
| 5331 | APSR.C = carry; |
| 5332 | // APSR.V unchanged |
| 5333 | #endif |
| 5334 | |
| 5335 | bool success = false; |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5336 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5337 | if (ConditionPassed(opcode)) |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5338 | { |
| 5339 | uint32_t Rd, Rn, Rm; |
| 5340 | ARM_ShifterType shift_t; |
| 5341 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 5342 | bool setflags; |
| 5343 | uint32_t carry; |
| 5344 | switch (encoding) |
| 5345 | { |
| 5346 | case eEncodingT1: |
| 5347 | Rd = Rn = Bits32(opcode, 2, 0); |
| 5348 | Rm = Bits32(opcode, 5, 3); |
| 5349 | setflags = !InITBlock(); |
| 5350 | shift_t = SRType_LSL; |
| 5351 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 5352 | break; |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5353 | case eEncodingT2: |
| 5354 | Rd = Bits32(opcode, 11, 8); |
| 5355 | Rn = Bits32(opcode, 19, 16); |
| 5356 | Rm = Bits32(opcode, 3, 0); |
| 5357 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 5358 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 5359 | // if Rd == '1111' && S == '1' then SEE TST (register); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5360 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5361 | return EmulateTSTReg(opcode, eEncodingT2); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5362 | if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm)) |
| 5363 | return false; |
| 5364 | break; |
| 5365 | case eEncodingA1: |
| 5366 | Rd = Bits32(opcode, 15, 12); |
| 5367 | Rn = Bits32(opcode, 19, 16); |
| 5368 | Rm = Bits32(opcode, 3, 0); |
| 5369 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 5370 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5371 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5372 | if (Rd == 15 && setflags) |
| 5373 | return false; |
| 5374 | break; |
| 5375 | default: |
| 5376 | return false; |
| 5377 | } |
| 5378 | |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5379 | // Read the first operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5380 | uint32_t val1 = ReadCoreReg(Rn, &success); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5381 | if (!success) |
| 5382 | return false; |
| 5383 | |
| 5384 | // Read the second operand. |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 5385 | uint32_t val2 = ReadCoreReg(Rm, &success); |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 5386 | if (!success) |
| 5387 | return false; |
| 5388 | |
| 5389 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
| 5390 | uint32_t result = val1 & shifted; |
| 5391 | |
| 5392 | EmulateInstruction::Context context; |
| 5393 | context.type = EmulateInstruction::eContextImmediate; |
| 5394 | context.SetNoArgs (); |
| 5395 | |
| 5396 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 5397 | return false; |
| 5398 | } |
| 5399 | return true; |
| 5400 | } |
| 5401 | |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5402 | // Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an |
| 5403 | // immediate value, and writes the result to the destination register. It can optionally update the |
| 5404 | // condition flags based on the result. |
| 5405 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5406 | EmulateInstructionARM::EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5407 | { |
| 5408 | #if 0 |
| 5409 | // ARM pseudo code... |
| 5410 | if ConditionPassed() then |
| 5411 | EncodingSpecificOperations(); |
| 5412 | result = R[n] AND NOT(imm32); |
| 5413 | if d == 15 then // Can only occur for ARM encoding |
| 5414 | ALUWritePC(result); // setflags is always FALSE here |
| 5415 | else |
| 5416 | R[d] = result; |
| 5417 | if setflags then |
| 5418 | APSR.N = result<31>; |
| 5419 | APSR.Z = IsZeroBit(result); |
| 5420 | APSR.C = carry; |
| 5421 | // APSR.V unchanged |
| 5422 | #endif |
| 5423 | |
| 5424 | bool success = false; |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5425 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5426 | if (ConditionPassed(opcode)) |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5427 | { |
| 5428 | uint32_t Rd, Rn; |
| 5429 | uint32_t imm32; // the immediate value to be bitwise inverted and ANDed to the value obtained from Rn |
| 5430 | bool setflags; |
| 5431 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 5432 | switch (encoding) |
| 5433 | { |
| 5434 | case eEncodingT1: |
| 5435 | Rd = Bits32(opcode, 11, 8); |
| 5436 | Rn = Bits32(opcode, 19, 16); |
| 5437 | setflags = BitIsSet(opcode, 20); |
| 5438 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
| 5439 | if (BadReg(Rd) || BadReg(Rn)) |
| 5440 | return false; |
| 5441 | break; |
| 5442 | case eEncodingA1: |
| 5443 | Rd = Bits32(opcode, 15, 12); |
| 5444 | Rn = Bits32(opcode, 19, 16); |
| 5445 | setflags = BitIsSet(opcode, 20); |
| 5446 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5447 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5448 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5449 | if (Rd == 15 && setflags) |
| 5450 | return false; |
| 5451 | break; |
| 5452 | default: |
| 5453 | return false; |
| 5454 | } |
| 5455 | |
| 5456 | // Read the first operand. |
| 5457 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 5458 | if (!success) |
| 5459 | return false; |
| 5460 | |
| 5461 | uint32_t result = val1 & ~imm32; |
| 5462 | |
| 5463 | EmulateInstruction::Context context; |
| 5464 | context.type = EmulateInstruction::eContextImmediate; |
| 5465 | context.SetNoArgs (); |
| 5466 | |
| 5467 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 5468 | return false; |
| 5469 | } |
| 5470 | return true; |
| 5471 | } |
| 5472 | |
| 5473 | // Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an |
| 5474 | // optionally-shifted register value, and writes the result to the destination register. |
| 5475 | // It can optionally update the condition flags based on the result. |
| 5476 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5477 | EmulateInstructionARM::EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5478 | { |
| 5479 | #if 0 |
| 5480 | // ARM pseudo code... |
| 5481 | if ConditionPassed() then |
| 5482 | EncodingSpecificOperations(); |
| 5483 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 5484 | result = R[n] AND NOT(shifted); |
| 5485 | if d == 15 then // Can only occur for ARM encoding |
| 5486 | ALUWritePC(result); // setflags is always FALSE here |
| 5487 | else |
| 5488 | R[d] = result; |
| 5489 | if setflags then |
| 5490 | APSR.N = result<31>; |
| 5491 | APSR.Z = IsZeroBit(result); |
| 5492 | APSR.C = carry; |
| 5493 | // APSR.V unchanged |
| 5494 | #endif |
| 5495 | |
| 5496 | bool success = false; |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5497 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5498 | if (ConditionPassed(opcode)) |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5499 | { |
| 5500 | uint32_t Rd, Rn, Rm; |
| 5501 | ARM_ShifterType shift_t; |
| 5502 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 5503 | bool setflags; |
| 5504 | uint32_t carry; |
| 5505 | switch (encoding) |
| 5506 | { |
| 5507 | case eEncodingT1: |
| 5508 | Rd = Rn = Bits32(opcode, 2, 0); |
| 5509 | Rm = Bits32(opcode, 5, 3); |
| 5510 | setflags = !InITBlock(); |
| 5511 | shift_t = SRType_LSL; |
| 5512 | shift_n = 0; |
| 5513 | break; |
| 5514 | case eEncodingT2: |
| 5515 | Rd = Bits32(opcode, 11, 8); |
| 5516 | Rn = Bits32(opcode, 19, 16); |
| 5517 | Rm = Bits32(opcode, 3, 0); |
| 5518 | setflags = BitIsSet(opcode, 20); |
| 5519 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
| 5520 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 5521 | return false; |
| 5522 | break; |
| 5523 | case eEncodingA1: |
| 5524 | Rd = Bits32(opcode, 15, 12); |
| 5525 | Rn = Bits32(opcode, 19, 16); |
| 5526 | Rm = Bits32(opcode, 3, 0); |
| 5527 | setflags = BitIsSet(opcode, 20); |
| 5528 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5529 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 5530 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 5531 | if (Rd == 15 && setflags) |
| 5532 | return false; |
| 5533 | break; |
| 5534 | default: |
| 5535 | return false; |
| 5536 | } |
| 5537 | |
| 5538 | // Read the first operand. |
| 5539 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 5540 | if (!success) |
| 5541 | return false; |
| 5542 | |
| 5543 | // Read the second operand. |
| 5544 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 5545 | if (!success) |
| 5546 | return false; |
| 5547 | |
| 5548 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
| 5549 | uint32_t result = val1 & ~shifted; |
| 5550 | |
| 5551 | EmulateInstruction::Context context; |
| 5552 | context.type = EmulateInstruction::eContextImmediate; |
| 5553 | context.SetNoArgs (); |
| 5554 | |
| 5555 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 5556 | return false; |
| 5557 | } |
| 5558 | return true; |
| 5559 | } |
| 5560 | |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5561 | // LDR (immediate, ARM) calculates an address from a base register value and an immediate offset, loads a word |
Johnny Chen | e92b27c | 2011-02-18 01:26:39 +0000 | [diff] [blame] | 5562 | // from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5563 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5564 | EmulateInstructionARM::EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5565 | { |
| 5566 | #if 0 |
| 5567 | if ConditionPassed() then |
| 5568 | EncodingSpecificOperations(); |
| 5569 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 5570 | address = if index then offset_addr else R[n]; |
| 5571 | data = MemU[address,4]; |
| 5572 | if wback then R[n] = offset_addr; |
| 5573 | if t == 15 then |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5574 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 5575 | elsif UnalignedSupport() || address<1:0> = '00' then |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5576 | R[t] = data; |
| 5577 | else // Can only apply before ARMv7 |
| 5578 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 5579 | #endif |
| 5580 | |
| 5581 | bool success = false; |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5582 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5583 | if (ConditionPassed(opcode)) |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5584 | { |
| 5585 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 5586 | |
| 5587 | uint32_t t; |
| 5588 | uint32_t n; |
| 5589 | uint32_t imm32; |
| 5590 | bool index; |
| 5591 | bool add; |
| 5592 | bool wback; |
| 5593 | |
| 5594 | switch (encoding) |
| 5595 | { |
| 5596 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5597 | // if Rn == '1111' then SEE LDR (literal); |
| 5598 | // if P == '0' && W == '1' then SEE LDRT; |
| 5599 | // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP; |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5600 | // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 5601 | t = Bits32 (opcode, 15, 12); |
| 5602 | n = Bits32 (opcode, 19, 16); |
| 5603 | imm32 = Bits32 (opcode, 11, 0); |
| 5604 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5605 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
| 5606 | index = BitIsSet (opcode, 24); |
| 5607 | add = BitIsSet (opcode, 23); |
| 5608 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5609 | |
| 5610 | // if wback && n == t then UNPREDICTABLE; |
| 5611 | if (wback && (n == t)) |
| 5612 | return false; |
| 5613 | |
| 5614 | break; |
| 5615 | |
| 5616 | default: |
| 5617 | return false; |
| 5618 | } |
| 5619 | |
| 5620 | addr_t address; |
| 5621 | addr_t offset_addr; |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 5622 | addr_t base_address = ReadCoreReg (n, &success); |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5623 | if (!success) |
| 5624 | return false; |
| 5625 | |
| 5626 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 5627 | if (add) |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 5628 | offset_addr = base_address + imm32; |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5629 | else |
| 5630 | offset_addr = base_address - imm32; |
| 5631 | |
| 5632 | // address = if index then offset_addr else R[n]; |
| 5633 | if (index) |
| 5634 | address = offset_addr; |
| 5635 | else |
| 5636 | address = base_address; |
| 5637 | |
| 5638 | // data = MemU[address,4]; |
| 5639 | |
| 5640 | Register base_reg; |
| 5641 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 5642 | |
| 5643 | EmulateInstruction::Context context; |
| 5644 | context.type = eContextRegisterLoad; |
| 5645 | context.SetRegisterPlusOffset (base_reg, address - base_address); |
| 5646 | |
| 5647 | uint64_t data = MemURead (context, address, addr_byte_size, 0, &success); |
| 5648 | if (!success) |
| 5649 | return false; |
| 5650 | |
| 5651 | // if wback then R[n] = offset_addr; |
| 5652 | if (wback) |
| 5653 | { |
| 5654 | context.type = eContextAdjustBaseRegister; |
| 5655 | context.SetAddress (offset_addr); |
| 5656 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 5657 | return false; |
| 5658 | } |
| 5659 | |
| 5660 | // if t == 15 then |
| 5661 | if (t == 15) |
| 5662 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5663 | // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5664 | if (BitIsClear (address, 1) && BitIsClear (address, 0)) |
| 5665 | { |
| 5666 | // LoadWritePC (data); |
| 5667 | context.type = eContextRegisterLoad; |
| 5668 | context.SetRegisterPlusOffset (base_reg, address - base_address); |
| 5669 | LoadWritePC (context, data); |
| 5670 | } |
| 5671 | else |
| 5672 | return false; |
| 5673 | } |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5674 | // elsif UnalignedSupport() || address<1:0> = '00' then |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 5675 | else if (UnalignedSupport() || (BitIsClear (address, 1) && BitIsClear (address, 0))) |
| 5676 | { |
| 5677 | // R[t] = data; |
| 5678 | context.type = eContextRegisterLoad; |
| 5679 | context.SetRegisterPlusOffset (base_reg, address - base_address); |
| 5680 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 5681 | return false; |
| 5682 | } |
| 5683 | // else // Can only apply before ARMv7 |
| 5684 | else |
| 5685 | { |
| 5686 | // R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 5687 | data = ROR (data, Bits32 (address, 1, 0)); |
| 5688 | context.type = eContextRegisterLoad; |
| 5689 | context.SetImmediate (data); |
| 5690 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 5691 | return false; |
| 5692 | } |
| 5693 | |
| 5694 | } |
| 5695 | return true; |
| 5696 | } |
| 5697 | |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5698 | // LDR (register) calculates an address from a base register value and an offset register value, loads a word |
| 5699 | // from memory, and writes it to a resgister. The offset register value can optionally be shifted. |
| 5700 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5701 | EmulateInstructionARM::EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5702 | { |
| 5703 | #if 0 |
| 5704 | if ConditionPassed() then |
| 5705 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 5706 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 5707 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 5708 | address = if index then offset_addr else R[n]; |
| 5709 | data = MemU[address,4]; |
| 5710 | if wback then R[n] = offset_addr; |
| 5711 | if t == 15 then |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5712 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 5713 | elsif UnalignedSupport() || address<1:0> = '00' then |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5714 | R[t] = data; |
| 5715 | else // Can only apply before ARMv7 |
| 5716 | if CurrentInstrSet() == InstrSet_ARM then |
| 5717 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 5718 | else |
| 5719 | R[t] = bits(32) UNKNOWN; |
| 5720 | #endif |
| 5721 | |
| 5722 | bool success = false; |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5723 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5724 | if (ConditionPassed(opcode)) |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5725 | { |
| 5726 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 5727 | |
| 5728 | uint32_t t; |
| 5729 | uint32_t n; |
| 5730 | uint32_t m; |
| 5731 | bool index; |
| 5732 | bool add; |
| 5733 | bool wback; |
| 5734 | ARM_ShifterType shift_t; |
| 5735 | uint32_t shift_n; |
| 5736 | |
| 5737 | switch (encoding) |
| 5738 | { |
| 5739 | case eEncodingT1: |
| 5740 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 5741 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 5742 | t = Bits32 (opcode, 2, 0); |
| 5743 | n = Bits32 (opcode, 5, 3); |
| 5744 | m = Bits32 (opcode, 8, 6); |
| 5745 | |
| 5746 | // index = TRUE; add = TRUE; wback = FALSE; |
| 5747 | index = true; |
| 5748 | add = true; |
| 5749 | wback = false; |
| 5750 | |
| 5751 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 5752 | shift_t = SRType_LSL; |
| 5753 | shift_n = 0; |
| 5754 | |
| 5755 | break; |
| 5756 | |
| 5757 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5758 | // if Rn == '1111' then SEE LDR (literal); |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5759 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 5760 | t = Bits32 (opcode, 15, 12); |
| 5761 | n = Bits32 (opcode, 19, 16); |
| 5762 | m = Bits32 (opcode, 3, 0); |
| 5763 | |
| 5764 | // index = TRUE; add = TRUE; wback = FALSE; |
| 5765 | index = true; |
| 5766 | add = true; |
| 5767 | wback = false; |
| 5768 | |
| 5769 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 5770 | shift_t = SRType_LSL; |
| 5771 | shift_n = Bits32 (opcode, 5, 4); |
| 5772 | |
| 5773 | // if BadReg(m) then UNPREDICTABLE; |
| 5774 | if (BadReg (m)) |
| 5775 | return false; |
| 5776 | |
| 5777 | // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 5778 | if ((t == 15) && InITBlock() && !LastInITBlock()) |
| 5779 | return false; |
| 5780 | |
| 5781 | break; |
| 5782 | |
| 5783 | case eEncodingA1: |
| 5784 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5785 | // if P == '0' && W == '1' then SEE LDRT; |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5786 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 5787 | t = Bits32 (opcode, 15, 12); |
| 5788 | n = Bits32 (opcode, 19, 16); |
| 5789 | m = Bits32 (opcode, 3, 0); |
| 5790 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5791 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5792 | index = BitIsSet (opcode, 24); |
| 5793 | add = BitIsSet (opcode, 23); |
| 5794 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 5795 | |
| 5796 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 5797 | uint32_t type = Bits32 (opcode, 6, 5); |
| 5798 | uint32_t imm5 = Bits32 (opcode, 11, 7); |
| 5799 | shift_n = DecodeImmShift (type, imm5, shift_t); |
| 5800 | |
| 5801 | // if m == 15 then UNPREDICTABLE; |
| 5802 | if (m == 15) |
| 5803 | return false; |
| 5804 | |
| 5805 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 5806 | if (wback && ((n == 15) || (n == t))) |
| 5807 | return false; |
| 5808 | } |
| 5809 | break; |
| 5810 | |
| 5811 | |
| 5812 | default: |
| 5813 | return false; |
| 5814 | } |
| 5815 | |
| 5816 | uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 5817 | if (!success) |
| 5818 | return false; |
| 5819 | |
| 5820 | uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 5821 | if (!success) |
| 5822 | return false; |
| 5823 | |
| 5824 | addr_t offset_addr; |
| 5825 | addr_t address; |
| 5826 | |
| 5827 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); -- Note "The APSR is an application level alias for the CPSR". |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 5828 | addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_opcode_cpsr, APSR_C)); |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5829 | |
| 5830 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 5831 | if (add) |
| 5832 | offset_addr = Rn + offset; |
| 5833 | else |
| 5834 | offset_addr = Rn - offset; |
| 5835 | |
| 5836 | // address = if index then offset_addr else R[n]; |
| 5837 | if (index) |
| 5838 | address = offset_addr; |
| 5839 | else |
| 5840 | address = Rn; |
| 5841 | |
| 5842 | // data = MemU[address,4]; |
| 5843 | Register base_reg; |
| 5844 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 5845 | |
| 5846 | EmulateInstruction::Context context; |
| 5847 | context.type = eContextRegisterLoad; |
| 5848 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 5849 | |
| 5850 | uint64_t data = MemURead (context, address, addr_byte_size, 0, &success); |
| 5851 | if (!success) |
| 5852 | return false; |
| 5853 | |
| 5854 | // if wback then R[n] = offset_addr; |
| 5855 | if (wback) |
| 5856 | { |
| 5857 | context.type = eContextAdjustBaseRegister; |
| 5858 | context.SetAddress (offset_addr); |
| 5859 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 5860 | return false; |
| 5861 | } |
| 5862 | |
| 5863 | // if t == 15 then |
| 5864 | if (t == 15) |
| 5865 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5866 | // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5867 | if (BitIsClear (address, 1) && BitIsClear (address, 0)) |
| 5868 | { |
| 5869 | context.type = eContextRegisterLoad; |
| 5870 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 5871 | LoadWritePC (context, data); |
| 5872 | } |
| 5873 | else |
| 5874 | return false; |
| 5875 | } |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5876 | // elsif UnalignedSupport() || address<1:0> = '00' then |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 5877 | else if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0))) |
| 5878 | { |
| 5879 | // R[t] = data; |
| 5880 | context.type = eContextRegisterLoad; |
| 5881 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 5882 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 5883 | return false; |
| 5884 | } |
| 5885 | else // Can only apply before ARMv7 |
| 5886 | { |
| 5887 | // if CurrentInstrSet() == InstrSet_ARM then |
| 5888 | if (CurrentInstrSet () == eModeARM) |
| 5889 | { |
| 5890 | // R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 5891 | data = ROR (data, Bits32 (address, 1, 0)); |
| 5892 | context.type = eContextRegisterLoad; |
| 5893 | context.SetImmediate (data); |
| 5894 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 5895 | return false; |
| 5896 | } |
| 5897 | else |
| 5898 | { |
| 5899 | // R[t] = bits(32) UNKNOWN; |
| 5900 | WriteBits32Unknown (t); |
| 5901 | } |
| 5902 | } |
| 5903 | } |
| 5904 | return true; |
| 5905 | } |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5906 | |
| 5907 | // LDRB (immediate, Thumb) |
| 5908 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5909 | EmulateInstructionARM::EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5910 | { |
| 5911 | #if 0 |
| 5912 | if ConditionPassed() then |
| 5913 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 5914 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 5915 | address = if index then offset_addr else R[n]; |
| 5916 | R[t] = ZeroExtend(MemU[address,1], 32); |
| 5917 | if wback then R[n] = offset_addr; |
| 5918 | #endif |
| 5919 | |
| 5920 | bool success = false; |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5921 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 5922 | if (ConditionPassed(opcode)) |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5923 | { |
| 5924 | uint32_t t; |
| 5925 | uint32_t n; |
| 5926 | uint32_t imm32; |
| 5927 | bool index; |
| 5928 | bool add; |
| 5929 | bool wback; |
| 5930 | |
| 5931 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 5932 | switch (encoding) |
| 5933 | { |
| 5934 | case eEncodingT1: |
| 5935 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32); |
| 5936 | t = Bits32 (opcode, 2, 0); |
| 5937 | n = Bits32 (opcode, 5, 3); |
| 5938 | imm32 = Bits32 (opcode, 10, 6); |
| 5939 | |
| 5940 | // index = TRUE; add = TRUE; wback = FALSE; |
| 5941 | index = true; |
| 5942 | add = true; |
| 5943 | wback= false; |
| 5944 | |
| 5945 | break; |
| 5946 | |
| 5947 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5948 | // if Rt == '1111' then SEE PLD; |
| 5949 | // if Rn == '1111' then SEE LDRB (literal); |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5950 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 5951 | t = Bits32 (opcode, 15, 12); |
| 5952 | n = Bits32 (opcode, 19, 16); |
| 5953 | imm32 = Bits32 (opcode, 11, 0); |
| 5954 | |
| 5955 | // index = TRUE; add = TRUE; wback = FALSE; |
| 5956 | index = true; |
| 5957 | add = true; |
| 5958 | wback = false; |
| 5959 | |
| 5960 | // if t == 13 then UNPREDICTABLE; |
| 5961 | if (t == 13) |
| 5962 | return false; |
| 5963 | |
| 5964 | break; |
| 5965 | |
| 5966 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5967 | // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD; |
| 5968 | // if Rn == '1111' then SEE LDRB (literal); |
| 5969 | // if P == '1' && U == '1' && W == '0' then SEE LDRBT; |
| 5970 | // if P == '0' && W == '0' then UNDEFINED; |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5971 | if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) |
| 5972 | return false; |
| 5973 | |
| 5974 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 5975 | t = Bits32 (opcode, 15, 12); |
| 5976 | n = Bits32 (opcode, 19, 16); |
| 5977 | imm32 = Bits32 (opcode, 7, 0); |
| 5978 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 5979 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 5980 | index = BitIsSet (opcode, 10); |
| 5981 | add = BitIsSet (opcode, 9); |
| 5982 | wback = BitIsSet (opcode, 8); |
| 5983 | |
| 5984 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE; |
| 5985 | if (BadReg (t) || (wback && (n == t))) |
| 5986 | return false; |
| 5987 | |
| 5988 | break; |
| 5989 | |
| 5990 | default: |
| 5991 | return false; |
| 5992 | } |
| 5993 | |
| 5994 | uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 5995 | if (!success) |
| 5996 | return false; |
| 5997 | |
| 5998 | addr_t address; |
| 5999 | addr_t offset_addr; |
| 6000 | |
| 6001 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 6002 | if (add) |
| 6003 | offset_addr = Rn + imm32; |
| 6004 | else |
| 6005 | offset_addr = Rn - imm32; |
| 6006 | |
| 6007 | // address = if index then offset_addr else R[n]; |
| 6008 | if (index) |
| 6009 | address = offset_addr; |
| 6010 | else |
| 6011 | address = Rn; |
| 6012 | |
| 6013 | // R[t] = ZeroExtend(MemU[address,1], 32); |
| 6014 | Register base_reg; |
| 6015 | Register data_reg; |
| 6016 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 6017 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 6018 | |
| 6019 | EmulateInstruction::Context context; |
| 6020 | context.type = eContextRegisterLoad; |
| 6021 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); |
| 6022 | |
| 6023 | uint64_t data = MemURead (context, address, 1, 0, &success); |
| 6024 | if (!success) |
| 6025 | return false; |
| 6026 | |
| 6027 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6028 | return false; |
| 6029 | |
| 6030 | // if wback then R[n] = offset_addr; |
| 6031 | if (wback) |
| 6032 | { |
| 6033 | context.type = eContextAdjustBaseRegister; |
| 6034 | context.SetAddress (offset_addr); |
| 6035 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 6036 | return false; |
| 6037 | } |
| 6038 | } |
| 6039 | return true; |
| 6040 | } |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6041 | |
| 6042 | // LDRB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, |
| 6043 | // zero-extends it to form a 32-bit word and writes it to a register. |
| 6044 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6045 | EmulateInstructionARM::EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6046 | { |
| 6047 | #if 0 |
| 6048 | if ConditionPassed() then |
| 6049 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 6050 | base = Align(PC,4); |
| 6051 | address = if add then (base + imm32) else (base - imm32); |
| 6052 | R[t] = ZeroExtend(MemU[address,1], 32); |
| 6053 | #endif |
| 6054 | |
| 6055 | bool success = false; |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6056 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6057 | if (ConditionPassed(opcode)) |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6058 | { |
| 6059 | uint32_t t; |
| 6060 | uint32_t imm32; |
| 6061 | bool add; |
| 6062 | switch (encoding) |
| 6063 | { |
| 6064 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6065 | // if Rt == '1111' then SEE PLD; |
| 6066 | // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6067 | t = Bits32 (opcode, 15, 12); |
| 6068 | imm32 = Bits32 (opcode, 11, 0); |
| 6069 | add = BitIsSet (opcode, 23); |
| 6070 | |
| 6071 | // if t == 13 then UNPREDICTABLE; |
| 6072 | if (t == 13) |
| 6073 | return false; |
| 6074 | |
| 6075 | break; |
| 6076 | |
| 6077 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6078 | // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6079 | t = Bits32 (opcode, 15, 12); |
| 6080 | imm32 = Bits32 (opcode, 11, 0); |
| 6081 | add = BitIsSet (opcode, 23); |
| 6082 | |
| 6083 | // if t == 15 then UNPREDICTABLE; |
| 6084 | if (t == 15) |
| 6085 | return false; |
| 6086 | break; |
| 6087 | |
| 6088 | default: |
| 6089 | return false; |
| 6090 | } |
| 6091 | |
| 6092 | // base = Align(PC,4); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 6093 | uint32_t pc_val = ReadCoreReg (PC_REG, &success); |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 6094 | if (!success) |
| 6095 | return false; |
| 6096 | |
| 6097 | uint32_t base = AlignPC (pc_val); |
| 6098 | |
| 6099 | addr_t address; |
| 6100 | // address = if add then (base + imm32) else (base - imm32); |
| 6101 | if (add) |
| 6102 | address = base + imm32; |
| 6103 | else |
| 6104 | address = base - imm32; |
| 6105 | |
| 6106 | // R[t] = ZeroExtend(MemU[address,1], 32); |
| 6107 | EmulateInstruction::Context context; |
| 6108 | context.type = eContextRelativeBranchImmediate; |
| 6109 | context.SetImmediate (address - base); |
| 6110 | |
| 6111 | uint64_t data = MemURead (context, address, 1, 0, &success); |
| 6112 | if (!success) |
| 6113 | return false; |
| 6114 | |
| 6115 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6116 | return false; |
| 6117 | } |
| 6118 | return true; |
| 6119 | } |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6120 | |
| 6121 | // LDRB (register) calculates an address from a base register value and an offset rigister value, loads a byte from |
| 6122 | // memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can |
| 6123 | // optionally be shifted. |
| 6124 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6125 | EmulateInstructionARM::EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6126 | { |
| 6127 | #if 0 |
| 6128 | if ConditionPassed() then |
| 6129 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6130 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 6131 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 6132 | address = if index then offset_addr else R[n]; |
| 6133 | R[t] = ZeroExtend(MemU[address,1],32); |
| 6134 | if wback then R[n] = offset_addr; |
| 6135 | #endif |
| 6136 | |
| 6137 | bool success = false; |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6138 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6139 | if (ConditionPassed(opcode)) |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6140 | { |
| 6141 | uint32_t t; |
| 6142 | uint32_t n; |
| 6143 | uint32_t m; |
| 6144 | bool index; |
| 6145 | bool add; |
| 6146 | bool wback; |
| 6147 | ARM_ShifterType shift_t; |
| 6148 | uint32_t shift_n; |
| 6149 | |
| 6150 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6151 | switch (encoding) |
| 6152 | { |
| 6153 | case eEncodingT1: |
| 6154 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6155 | t = Bits32 (opcode, 2, 0); |
| 6156 | n = Bits32 (opcode, 5, 3); |
| 6157 | m = Bits32 (opcode, 8, 6); |
| 6158 | |
| 6159 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6160 | index = true; |
| 6161 | add = true; |
| 6162 | wback = false; |
| 6163 | |
| 6164 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 6165 | shift_t = SRType_LSL; |
| 6166 | shift_n = 0; |
| 6167 | break; |
| 6168 | |
| 6169 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6170 | // if Rt == '1111' then SEE PLD; |
| 6171 | // if Rn == '1111' then SEE LDRB (literal); |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6172 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6173 | t = Bits32 (opcode, 15, 12); |
| 6174 | n = Bits32 (opcode, 19, 16); |
| 6175 | m = Bits32 (opcode, 3, 0); |
| 6176 | |
| 6177 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6178 | index = true; |
| 6179 | add = true; |
| 6180 | wback = false; |
| 6181 | |
| 6182 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 6183 | shift_t = SRType_LSL; |
| 6184 | shift_n = Bits32 (opcode, 5, 4); |
| 6185 | |
| 6186 | // if t == 13 || BadReg(m) then UNPREDICTABLE; |
| 6187 | if ((t == 13) || BadReg (m)) |
| 6188 | return false; |
| 6189 | break; |
| 6190 | |
| 6191 | case eEncodingA1: |
| 6192 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6193 | // if P == '0' && W == '1' then SEE LDRBT; |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6194 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6195 | t = Bits32 (opcode, 15, 12); |
| 6196 | n = Bits32 (opcode, 19, 16); |
| 6197 | m = Bits32 (opcode, 3, 0); |
| 6198 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6199 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 6200 | index = BitIsSet (opcode, 24); |
| 6201 | add = BitIsSet (opcode, 23); |
| 6202 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 6203 | |
| 6204 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 6205 | uint32_t type = Bits32 (opcode, 6, 5); |
| 6206 | uint32_t imm5 = Bits32 (opcode, 11, 7); |
| 6207 | shift_n = DecodeImmShift (type, imm5, shift_t); |
| 6208 | |
| 6209 | // if t == 15 || m == 15 then UNPREDICTABLE; |
| 6210 | if ((t == 15) || (m == 15)) |
| 6211 | return false; |
| 6212 | |
| 6213 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 6214 | if (wback && ((n == 15) || (n == t))) |
| 6215 | return false; |
| 6216 | } |
| 6217 | break; |
| 6218 | |
| 6219 | default: |
| 6220 | return false; |
| 6221 | } |
| 6222 | |
| 6223 | addr_t offset_addr; |
| 6224 | addr_t address; |
| 6225 | |
| 6226 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 6227 | uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 6228 | if (!success) |
| 6229 | return false; |
| 6230 | |
| 6231 | addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C); |
| 6232 | |
| 6233 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 6234 | uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 6235 | if (!success) |
| 6236 | return false; |
| 6237 | |
| 6238 | if (add) |
| 6239 | offset_addr = Rn + offset; |
| 6240 | else |
| 6241 | offset_addr = Rn - offset; |
| 6242 | |
| 6243 | // address = if index then offset_addr else R[n]; |
| 6244 | if (index) |
| 6245 | address = offset_addr; |
| 6246 | else |
| 6247 | address = Rn; |
| 6248 | |
| 6249 | // R[t] = ZeroExtend(MemU[address,1],32); |
| 6250 | Register base_reg; |
| 6251 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 6252 | |
| 6253 | EmulateInstruction::Context context; |
| 6254 | context.type = eContextRegisterLoad; |
| 6255 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 6256 | |
| 6257 | uint64_t data = MemURead (context, address, 1, 0, &success); |
| 6258 | if (!success) |
| 6259 | return false; |
| 6260 | |
| 6261 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6262 | return false; |
| 6263 | |
| 6264 | // if wback then R[n] = offset_addr; |
| 6265 | if (wback) |
| 6266 | { |
| 6267 | context.type = eContextAdjustBaseRegister; |
| 6268 | context.SetAddress (offset_addr); |
| 6269 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 6270 | return false; |
| 6271 | } |
| 6272 | } |
| 6273 | return true; |
| 6274 | } |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6275 | |
| 6276 | // LDRH (immediate, Thumb) calculates an address from a base register value and an immediate offset, loads a |
| 6277 | // halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, |
| 6278 | // post-indexed, or pre-indexed addressing. |
| 6279 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6280 | EmulateInstructionARM::EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6281 | { |
| 6282 | #if 0 |
| 6283 | if ConditionPassed() then |
| 6284 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6285 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 6286 | address = if index then offset_addr else R[n]; |
| 6287 | data = MemU[address,2]; |
| 6288 | if wback then R[n] = offset_addr; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6289 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6290 | R[t] = ZeroExtend(data, 32); |
| 6291 | else // Can only apply before ARMv7 |
| 6292 | R[t] = bits(32) UNKNOWN; |
| 6293 | #endif |
| 6294 | |
| 6295 | |
| 6296 | bool success = false; |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6297 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6298 | if (ConditionPassed(opcode)) |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6299 | { |
| 6300 | uint32_t t; |
| 6301 | uint32_t n; |
| 6302 | uint32_t imm32; |
| 6303 | bool index; |
| 6304 | bool add; |
| 6305 | bool wback; |
| 6306 | |
| 6307 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6308 | switch (encoding) |
| 6309 | { |
| 6310 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6311 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32); |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6312 | t = Bits32 (opcode, 2, 0); |
| 6313 | n = Bits32 (opcode, 5, 3); |
| 6314 | imm32 = Bits32 (opcode, 10, 6) << 1; |
| 6315 | |
| 6316 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6317 | index = true; |
| 6318 | add = true; |
| 6319 | wback = false; |
| 6320 | |
| 6321 | break; |
| 6322 | |
| 6323 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6324 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
| 6325 | // if Rn == '1111' then SEE LDRH (literal); |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6326 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 6327 | t = Bits32 (opcode, 15, 12); |
| 6328 | n = Bits32 (opcode, 19, 16); |
| 6329 | imm32 = Bits32 (opcode, 11, 0); |
| 6330 | |
| 6331 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6332 | index = true; |
| 6333 | add = true; |
| 6334 | wback = false; |
| 6335 | |
| 6336 | // if t == 13 then UNPREDICTABLE; |
| 6337 | if (t == 13) |
| 6338 | return false; |
| 6339 | break; |
| 6340 | |
| 6341 | case eEncodingT3: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6342 | // if Rn == '1111' then SEE LDRH (literal); |
| 6343 | // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints"; |
| 6344 | // if P == '1' && U == '1' && W == '0' then SEE LDRHT; |
| 6345 | // if P == '0' && W == '0' then UNDEFINED; |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6346 | if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) |
| 6347 | return false; |
| 6348 | |
| 6349 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 6350 | t = Bits32 (opcode, 15, 12); |
| 6351 | n = Bits32 (opcode, 19, 16); |
| 6352 | imm32 = Bits32 (opcode, 7, 0); |
| 6353 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6354 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6355 | index = BitIsSet (opcode, 10); |
| 6356 | add = BitIsSet (opcode, 9); |
| 6357 | wback = BitIsSet (opcode, 8); |
| 6358 | |
| 6359 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE; |
| 6360 | if (BadReg (t) || (wback && (n == t))) |
| 6361 | return false; |
| 6362 | break; |
| 6363 | |
| 6364 | default: |
| 6365 | return false; |
| 6366 | } |
| 6367 | |
| 6368 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 6369 | uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 6370 | if (!success) |
| 6371 | return false; |
| 6372 | |
| 6373 | addr_t offset_addr; |
| 6374 | addr_t address; |
| 6375 | |
| 6376 | if (add) |
| 6377 | offset_addr = Rn + imm32; |
| 6378 | else |
| 6379 | offset_addr = Rn - imm32; |
| 6380 | |
| 6381 | // address = if index then offset_addr else R[n]; |
| 6382 | if (index) |
| 6383 | address = offset_addr; |
| 6384 | else |
| 6385 | address = Rn; |
| 6386 | |
| 6387 | // data = MemU[address,2]; |
| 6388 | Register base_reg; |
| 6389 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 6390 | |
| 6391 | EmulateInstruction::Context context; |
| 6392 | context.type = eContextRegisterLoad; |
| 6393 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 6394 | |
| 6395 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 6396 | if (!success) |
| 6397 | return false; |
| 6398 | |
| 6399 | // if wback then R[n] = offset_addr; |
| 6400 | if (wback) |
| 6401 | { |
| 6402 | context.type = eContextAdjustBaseRegister; |
| 6403 | context.SetAddress (offset_addr); |
| 6404 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 6405 | return false; |
| 6406 | } |
| 6407 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6408 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 6409 | if (UnalignedSupport () || BitIsClear (address, 0)) |
| 6410 | { |
| 6411 | // R[t] = ZeroExtend(data, 32); |
| 6412 | context.type = eContextRegisterLoad; |
| 6413 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 6414 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6415 | return false; |
| 6416 | } |
| 6417 | else // Can only apply before ARMv7 |
| 6418 | { |
| 6419 | // R[t] = bits(32) UNKNOWN; |
| 6420 | WriteBits32Unknown (t); |
| 6421 | } |
| 6422 | } |
| 6423 | return true; |
| 6424 | } |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 6425 | |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6426 | // LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory, |
| 6427 | // zero-extends it to form a 32-bit word, and writes it to a register. |
| 6428 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6429 | EmulateInstructionARM::EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6430 | { |
| 6431 | #if 0 |
| 6432 | if ConditionPassed() then |
| 6433 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 6434 | base = Align(PC,4); |
| 6435 | address = if add then (base + imm32) else (base - imm32); |
| 6436 | data = MemU[address,2]; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6437 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6438 | R[t] = ZeroExtend(data, 32); |
| 6439 | else // Can only apply before ARMv7 |
| 6440 | R[t] = bits(32) UNKNOWN; |
| 6441 | #endif |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6442 | |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6443 | bool success = false; |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6444 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6445 | if (ConditionPassed(opcode)) |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6446 | { |
| 6447 | uint32_t t; |
| 6448 | uint32_t imm32; |
| 6449 | bool add; |
| 6450 | |
| 6451 | // EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 6452 | switch (encoding) |
| 6453 | { |
| 6454 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6455 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
| 6456 | // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6457 | t = Bits32 (opcode, 15, 12); |
| 6458 | imm32 = Bits32 (opcode, 11, 0); |
| 6459 | add = BitIsSet (opcode, 23); |
| 6460 | |
| 6461 | // if t == 13 then UNPREDICTABLE; |
| 6462 | if (t == 13) |
| 6463 | return false; |
| 6464 | |
| 6465 | break; |
| 6466 | |
| 6467 | case eEncodingA1: |
| 6468 | { |
| 6469 | uint32_t imm4H = Bits32 (opcode, 11, 8); |
| 6470 | uint32_t imm4L = Bits32 (opcode, 3, 0); |
| 6471 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6472 | // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6473 | t = Bits32 (opcode, 15, 12); |
Caroline Tice | 40b1a6c | 2011-03-03 00:07:02 +0000 | [diff] [blame] | 6474 | imm32 = (imm4H << 4) | imm4L; |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6475 | add = BitIsSet (opcode, 23); |
| 6476 | |
| 6477 | // if t == 15 then UNPREDICTABLE; |
| 6478 | if (t == 15) |
| 6479 | return false; |
| 6480 | break; |
| 6481 | } |
| 6482 | |
| 6483 | default: |
| 6484 | return false; |
| 6485 | } |
| 6486 | |
| 6487 | // base = Align(PC,4); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 6488 | uint64_t pc_value = ReadCoreReg (PC_REG, &success); |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6489 | if (!success) |
| 6490 | return false; |
| 6491 | |
| 6492 | addr_t base = AlignPC (pc_value); |
| 6493 | addr_t address; |
| 6494 | |
| 6495 | // address = if add then (base + imm32) else (base - imm32); |
| 6496 | if (add) |
| 6497 | address = base + imm32; |
| 6498 | else |
| 6499 | address = base - imm32; |
| 6500 | |
| 6501 | // data = MemU[address,2]; |
| 6502 | Register base_reg; |
| 6503 | base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 6504 | |
| 6505 | EmulateInstruction::Context context; |
| 6506 | context.type = eContextRegisterLoad; |
| 6507 | context.SetRegisterPlusOffset (base_reg, address - base); |
| 6508 | |
| 6509 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 6510 | if (!success) |
| 6511 | return false; |
| 6512 | |
| 6513 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6514 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 6515 | if (UnalignedSupport () || BitIsClear (address, 0)) |
| 6516 | { |
| 6517 | // R[t] = ZeroExtend(data, 32); |
| 6518 | context.type = eContextRegisterLoad; |
| 6519 | context.SetRegisterPlusOffset (base_reg, address - base); |
| 6520 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6521 | return false; |
| 6522 | |
| 6523 | } |
| 6524 | else // Can only apply before ARMv7 |
| 6525 | { |
| 6526 | // R[t] = bits(32) UNKNOWN; |
| 6527 | WriteBits32Unknown (t); |
| 6528 | } |
| 6529 | } |
| 6530 | return true; |
| 6531 | } |
| 6532 | |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6533 | // LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword |
| 6534 | // from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can |
| 6535 | // be shifted left by 0, 1, 2, or 3 bits. |
| 6536 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6537 | EmulateInstructionARM::EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6538 | { |
| 6539 | #if 0 |
| 6540 | if ConditionPassed() then |
| 6541 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6542 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 6543 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 6544 | address = if index then offset_addr else R[n]; |
| 6545 | data = MemU[address,2]; |
| 6546 | if wback then R[n] = offset_addr; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6547 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6548 | R[t] = ZeroExtend(data, 32); |
| 6549 | else // Can only apply before ARMv7 |
| 6550 | R[t] = bits(32) UNKNOWN; |
| 6551 | #endif |
| 6552 | |
| 6553 | bool success = false; |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6554 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6555 | if (ConditionPassed(opcode)) |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6556 | { |
| 6557 | uint32_t t; |
| 6558 | uint32_t n; |
| 6559 | uint32_t m; |
| 6560 | bool index; |
| 6561 | bool add; |
| 6562 | bool wback; |
| 6563 | ARM_ShifterType shift_t; |
| 6564 | uint32_t shift_n; |
| 6565 | |
| 6566 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6567 | switch (encoding) |
| 6568 | { |
| 6569 | case eEncodingT1: |
| 6570 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 6571 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6572 | t = Bits32 (opcode, 2, 0); |
| 6573 | n = Bits32 (opcode, 5, 3); |
| 6574 | m = Bits32 (opcode, 8, 6); |
| 6575 | |
| 6576 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6577 | index = true; |
| 6578 | add = true; |
| 6579 | wback = false; |
| 6580 | |
| 6581 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 6582 | shift_t = SRType_LSL; |
| 6583 | shift_n = 0; |
| 6584 | |
| 6585 | break; |
| 6586 | |
| 6587 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6588 | // if Rn == '1111' then SEE LDRH (literal); |
| 6589 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6590 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6591 | t = Bits32 (opcode, 15, 12); |
| 6592 | n = Bits32 (opcode, 19, 16); |
| 6593 | m = Bits32 (opcode, 3, 0); |
| 6594 | |
| 6595 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6596 | index = true; |
| 6597 | add = true; |
| 6598 | wback = false; |
| 6599 | |
| 6600 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 6601 | shift_t = SRType_LSL; |
| 6602 | shift_n = Bits32 (opcode, 5, 4); |
| 6603 | |
| 6604 | // if t == 13 || BadReg(m) then UNPREDICTABLE; |
| 6605 | if ((t == 13) || BadReg (m)) |
| 6606 | return false; |
| 6607 | break; |
| 6608 | |
| 6609 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6610 | // if P == '0' && W == '1' then SEE LDRHT; |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6611 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6612 | t = Bits32 (opcode, 15, 12); |
| 6613 | n = Bits32 (opcode, 19, 16); |
| 6614 | m = Bits32 (opcode, 3, 0); |
| 6615 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6616 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6617 | index = BitIsSet (opcode, 24); |
| 6618 | add = BitIsSet (opcode, 23); |
| 6619 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 6620 | |
| 6621 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 6622 | shift_t = SRType_LSL; |
| 6623 | shift_n = 0; |
| 6624 | |
| 6625 | // if t == 15 || m == 15 then UNPREDICTABLE; |
| 6626 | if ((t == 15) || (m == 15)) |
| 6627 | return false; |
| 6628 | |
| 6629 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 6630 | if (wback && ((n == 15) || (n == t))) |
| 6631 | return false; |
| 6632 | |
| 6633 | break; |
| 6634 | |
| 6635 | default: |
| 6636 | return false; |
| 6637 | } |
| 6638 | |
| 6639 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 6640 | |
| 6641 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 6642 | if (!success) |
| 6643 | return false; |
| 6644 | |
| 6645 | addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C); |
| 6646 | |
| 6647 | addr_t offset_addr; |
| 6648 | addr_t address; |
| 6649 | |
| 6650 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 6651 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 6652 | if (!success) |
| 6653 | return false; |
| 6654 | |
| 6655 | if (add) |
| 6656 | offset_addr = Rn + offset; |
| 6657 | else |
| 6658 | offset_addr = Rn - offset; |
| 6659 | |
| 6660 | // address = if index then offset_addr else R[n]; |
| 6661 | if (index) |
| 6662 | address = offset_addr; |
| 6663 | else |
| 6664 | address = Rn; |
| 6665 | |
| 6666 | // data = MemU[address,2]; |
| 6667 | Register base_reg; |
| 6668 | Register offset_reg; |
| 6669 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 6670 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 6671 | |
| 6672 | EmulateInstruction::Context context; |
| 6673 | context.type = eContextRegisterLoad; |
| 6674 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 6675 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 6676 | if (!success) |
| 6677 | return false; |
| 6678 | |
| 6679 | // if wback then R[n] = offset_addr; |
| 6680 | if (wback) |
| 6681 | { |
| 6682 | context.type = eContextAdjustBaseRegister; |
| 6683 | context.SetAddress (offset_addr); |
| 6684 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 6685 | return false; |
| 6686 | } |
| 6687 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6688 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6689 | if (UnalignedSupport() || BitIsClear (address, 0)) |
| 6690 | { |
| 6691 | // R[t] = ZeroExtend(data, 32); |
| 6692 | context.type = eContextRegisterLoad; |
| 6693 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 6694 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 6695 | return false; |
| 6696 | } |
| 6697 | else // Can only apply before ARMv7 |
| 6698 | { |
| 6699 | // R[t] = bits(32) UNKNOWN; |
| 6700 | WriteBits32Unknown (t); |
| 6701 | } |
| 6702 | } |
| 6703 | return true; |
| 6704 | } |
| 6705 | |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6706 | // LDRSB (immediate) calculates an address from a base register value and an immediate offset, loads a byte from |
| 6707 | // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, |
| 6708 | // or pre-indexed addressing. |
| 6709 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6710 | EmulateInstructionARM::EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6711 | { |
| 6712 | #if 0 |
| 6713 | if ConditionPassed() then |
| 6714 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6715 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 6716 | address = if index then offset_addr else R[n]; |
| 6717 | R[t] = SignExtend(MemU[address,1], 32); |
| 6718 | if wback then R[n] = offset_addr; |
| 6719 | #endif |
| 6720 | |
| 6721 | bool success = false; |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6722 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6723 | if (ConditionPassed(opcode)) |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6724 | { |
| 6725 | uint32_t t; |
| 6726 | uint32_t n; |
| 6727 | uint32_t imm32; |
| 6728 | bool index; |
| 6729 | bool add; |
| 6730 | bool wback; |
| 6731 | |
| 6732 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6733 | switch (encoding) |
| 6734 | { |
| 6735 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6736 | // if Rt == '1111' then SEE PLI; |
| 6737 | // if Rn == '1111' then SEE LDRSB (literal); |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6738 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 6739 | t = Bits32 (opcode, 15, 12); |
| 6740 | n = Bits32 (opcode, 19, 16); |
| 6741 | imm32 = Bits32 (opcode, 11, 0); |
| 6742 | |
| 6743 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6744 | index = true; |
| 6745 | add = true; |
| 6746 | wback = false; |
| 6747 | |
| 6748 | // if t == 13 then UNPREDICTABLE; |
| 6749 | if (t == 13) |
| 6750 | return false; |
| 6751 | |
| 6752 | break; |
| 6753 | |
| 6754 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6755 | // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI; |
| 6756 | // if Rn == '1111' then SEE LDRSB (literal); |
| 6757 | // if P == '1' && U == '1' && W == '0' then SEE LDRSBT; |
| 6758 | // if P == '0' && W == '0' then UNDEFINED; |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6759 | if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) |
| 6760 | return false; |
| 6761 | |
| 6762 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 6763 | t = Bits32 (opcode, 15, 12); |
| 6764 | n = Bits32 (opcode, 19, 16); |
| 6765 | imm32 = Bits32 (opcode, 7, 0); |
| 6766 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6767 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6768 | index = BitIsSet (opcode, 10); |
| 6769 | add = BitIsSet (opcode, 9); |
| 6770 | wback = BitIsSet (opcode, 8); |
| 6771 | |
| 6772 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6773 | if (((t == 13) || ((t == 15) |
| 6774 | && (BitIsClear (opcode, 10) || BitIsSet (opcode, 9) || BitIsSet (opcode, 8)))) |
| 6775 | || (wback && (n == t))) |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6776 | return false; |
| 6777 | |
| 6778 | break; |
| 6779 | |
| 6780 | case eEncodingA1: |
| 6781 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6782 | // if Rn == '1111' then SEE LDRSB (literal); |
| 6783 | // if P == '0' && W == '1' then SEE LDRSBT; |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6784 | // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); |
| 6785 | t = Bits32 (opcode, 15, 12); |
| 6786 | n = Bits32 (opcode, 19, 16); |
| 6787 | |
| 6788 | uint32_t imm4H = Bits32 (opcode, 11, 8); |
| 6789 | uint32_t imm4L = Bits32 (opcode, 3, 0); |
Caroline Tice | 40b1a6c | 2011-03-03 00:07:02 +0000 | [diff] [blame] | 6790 | imm32 = (imm4H << 4) | imm4L; |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6791 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6792 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6793 | index = BitIsSet (opcode, 24); |
| 6794 | add = BitIsSet (opcode, 23); |
| 6795 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 6796 | |
| 6797 | // if t == 15 || (wback && n == t) then UNPREDICTABLE; |
| 6798 | if ((t == 15) || (wback && (n == t))) |
| 6799 | return false; |
| 6800 | |
| 6801 | break; |
| 6802 | } |
| 6803 | |
| 6804 | default: |
| 6805 | return false; |
| 6806 | } |
| 6807 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6808 | uint64_t Rn = ReadCoreReg (n, &success); |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 6809 | if (!success) |
| 6810 | return false; |
| 6811 | |
| 6812 | addr_t offset_addr; |
| 6813 | addr_t address; |
| 6814 | |
| 6815 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 6816 | if (add) |
| 6817 | offset_addr = Rn + imm32; |
| 6818 | else |
| 6819 | offset_addr = Rn - imm32; |
| 6820 | |
| 6821 | // address = if index then offset_addr else R[n]; |
| 6822 | if (index) |
| 6823 | address = offset_addr; |
| 6824 | else |
| 6825 | address = Rn; |
| 6826 | |
| 6827 | // R[t] = SignExtend(MemU[address,1], 32); |
| 6828 | Register base_reg; |
| 6829 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 6830 | |
| 6831 | EmulateInstruction::Context context; |
| 6832 | context.type = eContextRegisterLoad; |
| 6833 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 6834 | |
| 6835 | uint64_t unsigned_data = MemURead (context, address, 1, 0, &success); |
| 6836 | if (!success) |
| 6837 | return false; |
| 6838 | |
| 6839 | int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); |
| 6840 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 6841 | return false; |
| 6842 | |
| 6843 | // if wback then R[n] = offset_addr; |
| 6844 | if (wback) |
| 6845 | { |
| 6846 | context.type = eContextAdjustBaseRegister; |
| 6847 | context.SetAddress (offset_addr); |
| 6848 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 6849 | return false; |
| 6850 | } |
| 6851 | } |
| 6852 | |
| 6853 | return true; |
| 6854 | } |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 6855 | |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6856 | // LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, |
| 6857 | // sign-extends it to form a 32-bit word, and writes tit to a register. |
| 6858 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6859 | EmulateInstructionARM::EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6860 | { |
| 6861 | #if 0 |
| 6862 | if ConditionPassed() then |
| 6863 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 6864 | base = Align(PC,4); |
| 6865 | address = if add then (base + imm32) else (base - imm32); |
| 6866 | R[t] = SignExtend(MemU[address,1], 32); |
| 6867 | #endif |
| 6868 | |
| 6869 | bool success = false; |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6870 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6871 | if (ConditionPassed(opcode)) |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6872 | { |
| 6873 | uint32_t t; |
| 6874 | uint32_t imm32; |
| 6875 | bool add; |
| 6876 | |
| 6877 | // EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 6878 | switch (encoding) |
| 6879 | { |
| 6880 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6881 | // if Rt == '1111' then SEE PLI; |
| 6882 | // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6883 | t = Bits32 (opcode, 15, 12); |
| 6884 | imm32 = Bits32 (opcode, 11, 0); |
| 6885 | add = BitIsSet (opcode, 23); |
| 6886 | |
| 6887 | // if t == 13 then UNPREDICTABLE; |
| 6888 | if (t == 13) |
| 6889 | return false; |
| 6890 | |
| 6891 | break; |
| 6892 | |
| 6893 | case eEncodingA1: |
| 6894 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6895 | // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6896 | t = Bits32 (opcode, 15, 12); |
| 6897 | uint32_t imm4H = Bits32 (opcode, 11, 8); |
| 6898 | uint32_t imm4L = Bits32 (opcode, 3, 0); |
Caroline Tice | 40b1a6c | 2011-03-03 00:07:02 +0000 | [diff] [blame] | 6899 | imm32 = (imm4H << 4) | imm4L; |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6900 | add = BitIsSet (opcode, 23); |
| 6901 | |
| 6902 | // if t == 15 then UNPREDICTABLE; |
| 6903 | if (t == 15) |
| 6904 | return false; |
| 6905 | |
| 6906 | break; |
| 6907 | } |
| 6908 | |
| 6909 | default: |
| 6910 | return false; |
| 6911 | } |
| 6912 | |
| 6913 | // base = Align(PC,4); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 6914 | uint64_t pc_value = ReadCoreReg (PC_REG, &success); |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 6915 | if (!success) |
| 6916 | return false; |
| 6917 | uint64_t base = AlignPC (pc_value); |
| 6918 | |
| 6919 | // address = if add then (base + imm32) else (base - imm32); |
| 6920 | addr_t address; |
| 6921 | if (add) |
| 6922 | address = base + imm32; |
| 6923 | else |
| 6924 | address = base - imm32; |
| 6925 | |
| 6926 | // R[t] = SignExtend(MemU[address,1], 32); |
| 6927 | Register base_reg; |
| 6928 | base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 6929 | |
| 6930 | EmulateInstruction::Context context; |
| 6931 | context.type = eContextRegisterLoad; |
| 6932 | context.SetRegisterPlusOffset (base_reg, address - base); |
| 6933 | |
| 6934 | uint64_t unsigned_data = MemURead (context, address, 1, 0, &success); |
| 6935 | if (!success) |
| 6936 | return false; |
| 6937 | |
| 6938 | int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); |
| 6939 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 6940 | return false; |
| 6941 | } |
| 6942 | return true; |
| 6943 | } |
| 6944 | |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 6945 | // LDRSB (register) calculates an address from a base register value and an offset register value, loadsa byte from |
| 6946 | // memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be |
| 6947 | // shifted left by 0, 1, 2, or 3 bits. |
| 6948 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6949 | EmulateInstructionARM::EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 6950 | { |
| 6951 | #if 0 |
| 6952 | if ConditionPassed() then |
| 6953 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6954 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 6955 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 6956 | address = if index then offset_addr else R[n]; |
| 6957 | R[t] = SignExtend(MemU[address,1], 32); |
| 6958 | if wback then R[n] = offset_addr; |
| 6959 | #endif |
| 6960 | |
| 6961 | bool success = false; |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 6962 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 6963 | if (ConditionPassed(opcode)) |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 6964 | { |
| 6965 | uint32_t t; |
| 6966 | uint32_t n; |
| 6967 | uint32_t m; |
| 6968 | bool index; |
| 6969 | bool add; |
| 6970 | bool wback; |
| 6971 | ARM_ShifterType shift_t; |
| 6972 | uint32_t shift_n; |
| 6973 | |
| 6974 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 6975 | switch (encoding) |
| 6976 | { |
| 6977 | case eEncodingT1: |
| 6978 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6979 | t = Bits32 (opcode, 2, 0); |
| 6980 | n = Bits32 (opcode, 5, 3); |
| 6981 | m = Bits32 (opcode, 8, 6); |
| 6982 | |
| 6983 | // index = TRUE; add = TRUE; wback = FALSE; |
| 6984 | index = true; |
| 6985 | add = true; |
| 6986 | wback = false; |
| 6987 | |
| 6988 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 6989 | shift_t = SRType_LSL; |
| 6990 | shift_n = 0; |
| 6991 | |
| 6992 | break; |
| 6993 | |
| 6994 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 6995 | // if Rt == '1111' then SEE PLI; |
| 6996 | // if Rn == '1111' then SEE LDRSB (literal); |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 6997 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 6998 | t = Bits32 (opcode, 15, 12); |
| 6999 | n = Bits32 (opcode, 19, 16); |
| 7000 | m = Bits32 (opcode, 3, 0); |
| 7001 | |
| 7002 | // index = TRUE; add = TRUE; wback = FALSE; |
| 7003 | index = true; |
| 7004 | add = true; |
| 7005 | wback = false; |
| 7006 | |
| 7007 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 7008 | shift_t = SRType_LSL; |
| 7009 | shift_n = Bits32 (opcode, 5, 4); |
| 7010 | |
| 7011 | // if t == 13 || BadReg(m) then UNPREDICTABLE; |
| 7012 | if ((t == 13) || BadReg (m)) |
| 7013 | return false; |
| 7014 | break; |
| 7015 | |
| 7016 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7017 | // if P == '0' && W == '1' then SEE LDRSBT; |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 7018 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 7019 | t = Bits32 (opcode, 15, 12); |
| 7020 | n = Bits32 (opcode, 19, 16); |
| 7021 | m = Bits32 (opcode, 3, 0); |
| 7022 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7023 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 7024 | index = BitIsSet (opcode, 24); |
| 7025 | add = BitIsSet (opcode, 23); |
| 7026 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 7027 | |
| 7028 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 7029 | shift_t = SRType_LSL; |
| 7030 | shift_n = 0; |
| 7031 | |
| 7032 | // if t == 15 || m == 15 then UNPREDICTABLE; |
| 7033 | if ((t == 15) || (m == 15)) |
| 7034 | return false; |
| 7035 | |
| 7036 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 7037 | if (wback && ((n == 15) || (n == t))) |
| 7038 | return false; |
| 7039 | break; |
| 7040 | |
| 7041 | default: |
| 7042 | return false; |
| 7043 | } |
| 7044 | |
| 7045 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7046 | if (!success) |
| 7047 | return false; |
| 7048 | |
| 7049 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 7050 | addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C); |
| 7051 | |
| 7052 | addr_t offset_addr; |
| 7053 | addr_t address; |
| 7054 | |
| 7055 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 7056 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 7057 | if (!success) |
| 7058 | return false; |
| 7059 | |
| 7060 | if (add) |
| 7061 | offset_addr = Rn + offset; |
| 7062 | else |
| 7063 | offset_addr = Rn - offset; |
| 7064 | |
| 7065 | // address = if index then offset_addr else R[n]; |
| 7066 | if (index) |
| 7067 | address = offset_addr; |
| 7068 | else |
| 7069 | address = Rn; |
| 7070 | |
| 7071 | // R[t] = SignExtend(MemU[address,1], 32); |
| 7072 | Register base_reg; |
| 7073 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 7074 | Register offset_reg; |
| 7075 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7076 | |
| 7077 | EmulateInstruction::Context context; |
| 7078 | context.type = eContextRegisterLoad; |
| 7079 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 7080 | |
| 7081 | uint64_t unsigned_data = MemURead (context, address, 1, 0, &success); |
| 7082 | if (!success) |
| 7083 | return false; |
| 7084 | |
| 7085 | int64_t signed_data = llvm::SignExtend64<8>(unsigned_data); |
| 7086 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 7087 | return false; |
| 7088 | |
| 7089 | // if wback then R[n] = offset_addr; |
| 7090 | if (wback) |
| 7091 | { |
| 7092 | context.type = eContextAdjustBaseRegister; |
| 7093 | context.SetAddress (offset_addr); |
| 7094 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 7095 | return false; |
| 7096 | } |
| 7097 | } |
| 7098 | return true; |
| 7099 | } |
| 7100 | |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7101 | // LDRSH (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from |
| 7102 | // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or |
| 7103 | // pre-indexed addressing. |
| 7104 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7105 | EmulateInstructionARM::EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7106 | { |
| 7107 | #if 0 |
| 7108 | if ConditionPassed() then |
| 7109 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 7110 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 7111 | address = if index then offset_addr else R[n]; |
| 7112 | data = MemU[address,2]; |
| 7113 | if wback then R[n] = offset_addr; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7114 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7115 | R[t] = SignExtend(data, 32); |
| 7116 | else // Can only apply before ARMv7 |
| 7117 | R[t] = bits(32) UNKNOWN; |
| 7118 | #endif |
| 7119 | |
| 7120 | bool success = false; |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7121 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7122 | if (ConditionPassed(opcode)) |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7123 | { |
| 7124 | uint32_t t; |
| 7125 | uint32_t n; |
| 7126 | uint32_t imm32; |
| 7127 | bool index; |
| 7128 | bool add; |
| 7129 | bool wback; |
| 7130 | |
| 7131 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 7132 | switch (encoding) |
| 7133 | { |
| 7134 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7135 | // if Rn == '1111' then SEE LDRSH (literal); |
| 7136 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7137 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 7138 | t = Bits32 (opcode, 15, 12); |
| 7139 | n = Bits32 (opcode, 19, 16); |
| 7140 | imm32 = Bits32 (opcode, 11, 0); |
| 7141 | |
| 7142 | // index = TRUE; add = TRUE; wback = FALSE; |
| 7143 | index = true; |
| 7144 | add = true; |
| 7145 | wback = false; |
| 7146 | |
| 7147 | // if t == 13 then UNPREDICTABLE; |
| 7148 | if (t == 13) |
| 7149 | return false; |
| 7150 | |
| 7151 | break; |
| 7152 | |
| 7153 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7154 | // if Rn == '1111' then SEE LDRSH (literal); |
| 7155 | // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints"; |
| 7156 | // if P == '1' && U == '1' && W == '0' then SEE LDRSHT; |
| 7157 | // if P == '0' && W == '0' then UNDEFINED; |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7158 | if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) |
| 7159 | return false; |
| 7160 | |
| 7161 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 7162 | t = Bits32 (opcode, 15, 12); |
| 7163 | n = Bits32 (opcode, 19, 16); |
| 7164 | imm32 = Bits32 (opcode, 7, 0); |
| 7165 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7166 | // index = (P == '1'); add = (U == '1'); wback = (W == '1'); |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7167 | index = BitIsSet (opcode, 10); |
| 7168 | add = BitIsSet (opcode, 9); |
| 7169 | wback = BitIsSet (opcode, 8); |
| 7170 | |
| 7171 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE; |
| 7172 | if (BadReg (t) || (wback && (n == t))) |
| 7173 | return false; |
| 7174 | |
| 7175 | break; |
| 7176 | |
| 7177 | case eEncodingA1: |
| 7178 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7179 | // if Rn == '1111' then SEE LDRSH (literal); |
| 7180 | // if P == '0' && W == '1' then SEE LDRSHT; |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7181 | // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); |
| 7182 | t = Bits32 (opcode, 15, 12); |
| 7183 | n = Bits32 (opcode, 19, 16); |
| 7184 | uint32_t imm4H = Bits32 (opcode, 11,8); |
| 7185 | uint32_t imm4L = Bits32 (opcode, 3, 0); |
Caroline Tice | 40b1a6c | 2011-03-03 00:07:02 +0000 | [diff] [blame] | 7186 | imm32 = (imm4H << 4) | imm4L; |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7187 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7188 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7189 | index = BitIsSet (opcode, 24); |
| 7190 | add = BitIsSet (opcode, 23); |
| 7191 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 7192 | |
| 7193 | // if t == 15 || (wback && n == t) then UNPREDICTABLE; |
| 7194 | if ((t == 15) || (wback && (n == t))) |
| 7195 | return false; |
| 7196 | |
| 7197 | break; |
| 7198 | } |
| 7199 | |
| 7200 | default: |
| 7201 | return false; |
| 7202 | } |
| 7203 | |
| 7204 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 7205 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 7206 | if (!success) |
| 7207 | return false; |
| 7208 | |
| 7209 | addr_t offset_addr; |
| 7210 | if (add) |
| 7211 | offset_addr = Rn + imm32; |
| 7212 | else |
| 7213 | offset_addr = Rn - imm32; |
| 7214 | |
| 7215 | // address = if index then offset_addr else R[n]; |
| 7216 | addr_t address; |
| 7217 | if (index) |
| 7218 | address = offset_addr; |
| 7219 | else |
| 7220 | address = Rn; |
| 7221 | |
| 7222 | // data = MemU[address,2]; |
| 7223 | Register base_reg; |
| 7224 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 7225 | |
| 7226 | EmulateInstruction::Context context; |
| 7227 | context.type = eContextRegisterLoad; |
| 7228 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 7229 | |
| 7230 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 7231 | if (!success) |
| 7232 | return false; |
| 7233 | |
| 7234 | // if wback then R[n] = offset_addr; |
| 7235 | if (wback) |
| 7236 | { |
| 7237 | context.type = eContextAdjustBaseRegister; |
| 7238 | context.SetAddress (offset_addr); |
| 7239 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 7240 | return false; |
| 7241 | } |
| 7242 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7243 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 7244 | if (UnalignedSupport() || BitIsClear (address, 0)) |
| 7245 | { |
| 7246 | // R[t] = SignExtend(data, 32); |
| 7247 | int64_t signed_data = llvm::SignExtend64<16>(data); |
| 7248 | context.type = eContextRegisterLoad; |
| 7249 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 7250 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 7251 | return false; |
| 7252 | } |
| 7253 | else // Can only apply before ARMv7 |
| 7254 | { |
| 7255 | // R[t] = bits(32) UNKNOWN; |
| 7256 | WriteBits32Unknown (t); |
| 7257 | } |
| 7258 | } |
| 7259 | return true; |
| 7260 | } |
| 7261 | |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7262 | // LDRSH (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, |
| 7263 | // sign-extends it to from a 32-bit word, and writes it to a register. |
| 7264 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7265 | EmulateInstructionARM::EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7266 | { |
| 7267 | #if 0 |
| 7268 | if ConditionPassed() then |
| 7269 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 7270 | base = Align(PC,4); |
| 7271 | address = if add then (base + imm32) else (base - imm32); |
| 7272 | data = MemU[address,2]; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7273 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7274 | R[t] = SignExtend(data, 32); |
| 7275 | else // Can only apply before ARMv7 |
| 7276 | R[t] = bits(32) UNKNOWN; |
| 7277 | #endif |
| 7278 | |
| 7279 | bool success = false; |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7280 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7281 | if (ConditionPassed(opcode)) |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7282 | { |
| 7283 | uint32_t t; |
| 7284 | uint32_t imm32; |
| 7285 | bool add; |
| 7286 | |
| 7287 | // EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 7288 | switch (encoding) |
| 7289 | { |
| 7290 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7291 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
| 7292 | // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7293 | t = Bits32 (opcode, 15, 12); |
| 7294 | imm32 = Bits32 (opcode, 11, 0); |
| 7295 | add = BitIsSet (opcode, 23); |
| 7296 | |
| 7297 | // if t == 13 then UNPREDICTABLE; |
| 7298 | if (t == 13) |
| 7299 | return false; |
| 7300 | |
| 7301 | break; |
| 7302 | |
| 7303 | case eEncodingA1: |
| 7304 | { |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7305 | // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7306 | t = Bits32 (opcode, 15, 12); |
| 7307 | uint32_t imm4H = Bits32 (opcode, 11, 8); |
| 7308 | uint32_t imm4L = Bits32 (opcode, 3, 0); |
Caroline Tice | 40b1a6c | 2011-03-03 00:07:02 +0000 | [diff] [blame] | 7309 | imm32 = (imm4H << 4) | imm4L; |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7310 | add = BitIsSet (opcode, 23); |
| 7311 | |
| 7312 | // if t == 15 then UNPREDICTABLE; |
| 7313 | if (t == 15) |
| 7314 | return false; |
| 7315 | |
| 7316 | break; |
| 7317 | } |
| 7318 | default: |
| 7319 | return false; |
| 7320 | } |
| 7321 | |
| 7322 | // base = Align(PC,4); |
Caroline Tice | 8d681f5 | 2011-03-17 23:50:16 +0000 | [diff] [blame] | 7323 | uint64_t pc_value = ReadCoreReg (PC_REG, &success); |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7324 | if (!success) |
| 7325 | return false; |
| 7326 | |
| 7327 | uint64_t base = AlignPC (pc_value); |
| 7328 | |
| 7329 | addr_t address; |
| 7330 | // address = if add then (base + imm32) else (base - imm32); |
| 7331 | if (add) |
| 7332 | address = base + imm32; |
| 7333 | else |
| 7334 | address = base - imm32; |
| 7335 | |
| 7336 | // data = MemU[address,2]; |
| 7337 | Register base_reg; |
| 7338 | base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 7339 | |
| 7340 | EmulateInstruction::Context context; |
| 7341 | context.type = eContextRegisterLoad; |
| 7342 | context.SetRegisterPlusOffset (base_reg, imm32); |
| 7343 | |
| 7344 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 7345 | if (!success) |
| 7346 | return false; |
| 7347 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7348 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 7349 | if (UnalignedSupport() || BitIsClear (address, 0)) |
| 7350 | { |
| 7351 | // R[t] = SignExtend(data, 32); |
| 7352 | int64_t signed_data = llvm::SignExtend64<16>(data); |
| 7353 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 7354 | return false; |
| 7355 | } |
| 7356 | else // Can only apply before ARMv7 |
| 7357 | { |
| 7358 | // R[t] = bits(32) UNKNOWN; |
| 7359 | WriteBits32Unknown (t); |
| 7360 | } |
| 7361 | } |
| 7362 | return true; |
| 7363 | } |
| 7364 | |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7365 | // LDRSH (register) calculates an address from a base register value and an offset register value, loads a halfword |
| 7366 | // from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be |
| 7367 | // shifted left by 0, 1, 2, or 3 bits. |
| 7368 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7369 | EmulateInstructionARM::EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7370 | { |
| 7371 | #if 0 |
| 7372 | if ConditionPassed() then |
| 7373 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 7374 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 7375 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 7376 | address = if index then offset_addr else R[n]; |
| 7377 | data = MemU[address,2]; |
| 7378 | if wback then R[n] = offset_addr; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7379 | if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7380 | R[t] = SignExtend(data, 32); |
| 7381 | else // Can only apply before ARMv7 |
| 7382 | R[t] = bits(32) UNKNOWN; |
| 7383 | #endif |
| 7384 | |
| 7385 | bool success = false; |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7386 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7387 | if (ConditionPassed(opcode)) |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7388 | { |
| 7389 | uint32_t t; |
| 7390 | uint32_t n; |
| 7391 | uint32_t m; |
| 7392 | bool index; |
| 7393 | bool add; |
| 7394 | bool wback; |
| 7395 | ARM_ShifterType shift_t; |
| 7396 | uint32_t shift_n; |
| 7397 | |
| 7398 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 7399 | switch (encoding) |
| 7400 | { |
| 7401 | case eEncodingT1: |
| 7402 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 7403 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 7404 | t = Bits32 (opcode, 2, 0); |
| 7405 | n = Bits32 (opcode, 5, 3); |
| 7406 | m = Bits32 (opcode, 8, 6); |
| 7407 | |
| 7408 | // index = TRUE; add = TRUE; wback = FALSE; |
| 7409 | index = true; |
| 7410 | add = true; |
| 7411 | wback = false; |
| 7412 | |
| 7413 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 7414 | shift_t = SRType_LSL; |
| 7415 | shift_n = 0; |
| 7416 | |
| 7417 | break; |
| 7418 | |
| 7419 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7420 | // if Rn == '1111' then SEE LDRSH (literal); |
| 7421 | // if Rt == '1111' then SEE "Unallocated memory hints"; |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7422 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 7423 | t = Bits32 (opcode, 15, 12); |
| 7424 | n = Bits32 (opcode, 19, 16); |
| 7425 | m = Bits32 (opcode, 3, 0); |
| 7426 | |
| 7427 | // index = TRUE; add = TRUE; wback = FALSE; |
| 7428 | index = true; |
| 7429 | add = true; |
| 7430 | wback = false; |
| 7431 | |
| 7432 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 7433 | shift_t = SRType_LSL; |
| 7434 | shift_n = Bits32 (opcode, 5, 4); |
| 7435 | |
| 7436 | // if t == 13 || BadReg(m) then UNPREDICTABLE; |
| 7437 | if ((t == 13) || BadReg (m)) |
| 7438 | return false; |
| 7439 | |
| 7440 | break; |
| 7441 | |
| 7442 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7443 | // if P == '0' && W == '1' then SEE LDRSHT; |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7444 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 7445 | t = Bits32 (opcode, 15, 12); |
| 7446 | n = Bits32 (opcode, 19, 16); |
| 7447 | m = Bits32 (opcode, 3, 0); |
| 7448 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7449 | // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7450 | index = BitIsSet (opcode, 24); |
| 7451 | add = BitIsSet (opcode, 23); |
| 7452 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 7453 | |
| 7454 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 7455 | shift_t = SRType_LSL; |
| 7456 | shift_n = 0; |
| 7457 | |
| 7458 | // if t == 15 || m == 15 then UNPREDICTABLE; |
| 7459 | if ((t == 15) || (m == 15)) |
| 7460 | return false; |
| 7461 | |
| 7462 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 7463 | if (wback && ((n == 15) || (n == t))) |
| 7464 | return false; |
| 7465 | |
| 7466 | break; |
| 7467 | |
| 7468 | default: |
| 7469 | break; |
| 7470 | } |
| 7471 | |
| 7472 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7473 | if (!success) |
| 7474 | return false; |
| 7475 | |
| 7476 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 7477 | if (!success) |
| 7478 | return false; |
| 7479 | |
| 7480 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 7481 | addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C); |
| 7482 | |
| 7483 | addr_t offset_addr; |
| 7484 | addr_t address; |
| 7485 | |
| 7486 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 7487 | if (add) |
| 7488 | offset_addr = Rn + offset; |
| 7489 | else |
| 7490 | offset_addr = Rn - offset; |
| 7491 | |
| 7492 | // address = if index then offset_addr else R[n]; |
| 7493 | if (index) |
| 7494 | address = offset_addr; |
| 7495 | else |
| 7496 | address = Rn; |
| 7497 | |
| 7498 | // data = MemU[address,2]; |
| 7499 | Register base_reg; |
| 7500 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 7501 | |
| 7502 | Register offset_reg; |
| 7503 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7504 | |
| 7505 | EmulateInstruction::Context context; |
| 7506 | context.type = eContextRegisterLoad; |
| 7507 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 7508 | |
| 7509 | uint64_t data = MemURead (context, address, 2, 0, &success); |
| 7510 | if (!success) |
| 7511 | return false; |
| 7512 | |
| 7513 | // if wback then R[n] = offset_addr; |
| 7514 | if (wback) |
| 7515 | { |
| 7516 | context.type = eContextAdjustBaseRegister; |
| 7517 | context.SetAddress (offset_addr); |
| 7518 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 7519 | return false; |
| 7520 | } |
| 7521 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7522 | // if UnalignedSupport() || address<0> = '0' then |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7523 | if (UnalignedSupport() || BitIsClear (address, 0)) |
| 7524 | { |
| 7525 | // R[t] = SignExtend(data, 32); |
| 7526 | context.type = eContextRegisterLoad; |
| 7527 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 7528 | |
| 7529 | int64_t signed_data = llvm::SignExtend64<16>(data); |
| 7530 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data)) |
| 7531 | return false; |
| 7532 | } |
| 7533 | else // Can only apply before ARMv7 |
| 7534 | { |
| 7535 | // R[t] = bits(32) UNKNOWN; |
| 7536 | WriteBits32Unknown (t); |
| 7537 | } |
| 7538 | } |
| 7539 | return true; |
| 7540 | } |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7541 | |
| 7542 | // SXTB extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination |
| 7543 | // register. You can specifiy a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. |
| 7544 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7545 | EmulateInstructionARM::EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7546 | { |
| 7547 | #if 0 |
| 7548 | if ConditionPassed() then |
| 7549 | EncodingSpecificOperations(); |
| 7550 | rotated = ROR(R[m], rotation); |
| 7551 | R[d] = SignExtend(rotated<7:0>, 32); |
| 7552 | #endif |
| 7553 | |
| 7554 | bool success = false; |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7555 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7556 | if (ConditionPassed(opcode)) |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7557 | { |
| 7558 | uint32_t d; |
| 7559 | uint32_t m; |
| 7560 | uint32_t rotation; |
| 7561 | |
| 7562 | // EncodingSpecificOperations(); |
| 7563 | switch (encoding) |
| 7564 | { |
| 7565 | case eEncodingT1: |
| 7566 | // d = UInt(Rd); m = UInt(Rm); rotation = 0; |
| 7567 | d = Bits32 (opcode, 2, 0); |
| 7568 | m = Bits32 (opcode, 5, 3); |
| 7569 | rotation = 0; |
| 7570 | |
| 7571 | break; |
| 7572 | |
| 7573 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7574 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7575 | d = Bits32 (opcode, 11, 8); |
| 7576 | m = Bits32 (opcode, 3, 0); |
| 7577 | rotation = Bits32 (opcode, 5, 4) << 3; |
| 7578 | |
| 7579 | // if BadReg(d) || BadReg(m) then UNPREDICTABLE; |
| 7580 | if (BadReg (d) || BadReg (m)) |
| 7581 | return false; |
| 7582 | |
| 7583 | break; |
| 7584 | |
| 7585 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7586 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7587 | d = Bits32 (opcode, 15, 12); |
| 7588 | m = Bits32 (opcode, 3, 0); |
| 7589 | rotation = Bits32 (opcode, 11, 10) << 3; |
| 7590 | |
| 7591 | // if d == 15 || m == 15 then UNPREDICTABLE; |
| 7592 | if ((d == 15) || (m == 15)) |
| 7593 | return false; |
| 7594 | |
| 7595 | break; |
| 7596 | |
| 7597 | default: |
| 7598 | return false; |
| 7599 | } |
| 7600 | |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7601 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7602 | if (!success) |
| 7603 | return false; |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7604 | |
| 7605 | // rotated = ROR(R[m], rotation); |
| 7606 | uint64_t rotated = ROR (Rm, rotation); |
| 7607 | |
| 7608 | // R[d] = SignExtend(rotated<7:0>, 32); |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7609 | int64_t data = llvm::SignExtend64<8>(rotated); |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7610 | |
| 7611 | Register source_reg; |
| 7612 | source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7613 | |
| 7614 | EmulateInstruction::Context context; |
| 7615 | context.type = eContextRegisterLoad; |
| 7616 | context.SetRegister (source_reg); |
| 7617 | |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7618 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data)) |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 7619 | return false; |
| 7620 | } |
| 7621 | return true; |
| 7622 | } |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 7623 | |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7624 | // SXTH extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination |
| 7625 | // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. |
| 7626 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7627 | EmulateInstructionARM::EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7628 | { |
| 7629 | #if 0 |
| 7630 | if ConditionPassed() then |
| 7631 | EncodingSpecificOperations(); |
| 7632 | rotated = ROR(R[m], rotation); |
| 7633 | R[d] = SignExtend(rotated<15:0>, 32); |
| 7634 | #endif |
| 7635 | |
| 7636 | bool success = false; |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7637 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7638 | if (ConditionPassed(opcode)) |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7639 | { |
| 7640 | uint32_t d; |
| 7641 | uint32_t m; |
| 7642 | uint32_t rotation; |
| 7643 | |
| 7644 | // EncodingSpecificOperations(); |
| 7645 | switch (encoding) |
| 7646 | { |
| 7647 | case eEncodingT1: |
| 7648 | // d = UInt(Rd); m = UInt(Rm); rotation = 0; |
| 7649 | d = Bits32 (opcode, 2, 0); |
| 7650 | m = Bits32 (opcode, 5, 3); |
| 7651 | rotation = 0; |
| 7652 | |
| 7653 | break; |
| 7654 | |
| 7655 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7656 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7657 | d = Bits32 (opcode, 11, 8); |
| 7658 | m = Bits32 (opcode, 3, 0); |
| 7659 | rotation = Bits32 (opcode, 5, 4) << 3; |
| 7660 | |
| 7661 | // if BadReg(d) || BadReg(m) then UNPREDICTABLE; |
| 7662 | if (BadReg (d) || BadReg (m)) |
| 7663 | return false; |
| 7664 | |
| 7665 | break; |
| 7666 | |
| 7667 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7668 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7669 | d = Bits32 (opcode, 15, 12); |
| 7670 | m = Bits32 (opcode, 3, 0); |
| 7671 | rotation = Bits32 (opcode, 11, 10) << 3; |
| 7672 | |
| 7673 | // if d == 15 || m == 15 then UNPREDICTABLE; |
| 7674 | if ((d == 15) || (m == 15)) |
| 7675 | return false; |
| 7676 | |
| 7677 | break; |
| 7678 | |
| 7679 | default: |
| 7680 | return false; |
| 7681 | } |
| 7682 | |
| 7683 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7684 | if (!success) |
| 7685 | return false; |
| 7686 | |
| 7687 | // rotated = ROR(R[m], rotation); |
| 7688 | uint64_t rotated = ROR (Rm, rotation); |
| 7689 | |
| 7690 | // R[d] = SignExtend(rotated<15:0>, 32); |
| 7691 | Register source_reg; |
| 7692 | source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7693 | |
| 7694 | EmulateInstruction::Context context; |
| 7695 | context.type = eContextRegisterLoad; |
| 7696 | context.SetRegister (source_reg); |
| 7697 | |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7698 | int64_t data = llvm::SignExtend64<16> (rotated); |
| 7699 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data)) |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 7700 | return false; |
| 7701 | } |
| 7702 | |
| 7703 | return true; |
| 7704 | } |
| 7705 | |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7706 | // UXTB extracts an 8-bit value from a register, zero-extneds it to 32 bits, and writes the result to the destination |
| 7707 | // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. |
| 7708 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7709 | EmulateInstructionARM::EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7710 | { |
| 7711 | #if 0 |
| 7712 | if ConditionPassed() then |
| 7713 | EncodingSpecificOperations(); |
| 7714 | rotated = ROR(R[m], rotation); |
| 7715 | R[d] = ZeroExtend(rotated<7:0>, 32); |
| 7716 | #endif |
| 7717 | |
| 7718 | bool success = false; |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7719 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7720 | if (ConditionPassed(opcode)) |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7721 | { |
| 7722 | uint32_t d; |
| 7723 | uint32_t m; |
| 7724 | uint32_t rotation; |
| 7725 | |
| 7726 | // EncodingSpecificOperations(); |
| 7727 | switch (encoding) |
| 7728 | { |
| 7729 | case eEncodingT1: |
| 7730 | // d = UInt(Rd); m = UInt(Rm); rotation = 0; |
| 7731 | d = Bits32 (opcode, 2, 0); |
| 7732 | m = Bits32 (opcode, 5, 3); |
| 7733 | rotation = 0; |
| 7734 | |
| 7735 | break; |
| 7736 | |
| 7737 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7738 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7739 | d = Bits32 (opcode, 11, 8); |
| 7740 | m = Bits32 (opcode, 3, 0); |
| 7741 | rotation = Bits32 (opcode, 5, 4) << 3; |
| 7742 | |
| 7743 | // if BadReg(d) || BadReg(m) then UNPREDICTABLE; |
| 7744 | if (BadReg (d) || BadReg (m)) |
| 7745 | return false; |
| 7746 | |
| 7747 | break; |
| 7748 | |
| 7749 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7750 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 7751 | d = Bits32 (opcode, 15, 12); |
| 7752 | m = Bits32 (opcode, 3, 0); |
| 7753 | rotation = Bits32 (opcode, 11, 10) << 3; |
| 7754 | |
| 7755 | // if d == 15 || m == 15 then UNPREDICTABLE; |
| 7756 | if ((d == 15) || (m == 15)) |
| 7757 | return false; |
| 7758 | |
| 7759 | break; |
| 7760 | |
| 7761 | default: |
| 7762 | return false; |
| 7763 | } |
| 7764 | |
| 7765 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7766 | if (!success) |
| 7767 | return false; |
| 7768 | |
| 7769 | // rotated = ROR(R[m], rotation); |
| 7770 | uint64_t rotated = ROR (Rm, rotation); |
| 7771 | |
| 7772 | // R[d] = ZeroExtend(rotated<7:0>, 32); |
| 7773 | Register source_reg; |
| 7774 | source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7775 | |
| 7776 | EmulateInstruction::Context context; |
| 7777 | context.type = eContextRegisterLoad; |
| 7778 | context.SetRegister (source_reg); |
| 7779 | |
| 7780 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 7, 0))) |
| 7781 | return false; |
| 7782 | } |
| 7783 | return true; |
| 7784 | } |
| 7785 | |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7786 | // UXTH extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination |
| 7787 | // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. |
| 7788 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7789 | EmulateInstructionARM::EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7790 | { |
| 7791 | #if 0 |
| 7792 | if ConditionPassed() then |
| 7793 | EncodingSpecificOperations(); |
| 7794 | rotated = ROR(R[m], rotation); |
| 7795 | R[d] = ZeroExtend(rotated<15:0>, 32); |
| 7796 | #endif |
| 7797 | |
| 7798 | bool success = false; |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7799 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7800 | if (ConditionPassed(opcode)) |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7801 | { |
| 7802 | uint32_t d; |
| 7803 | uint32_t m; |
| 7804 | uint32_t rotation; |
| 7805 | |
| 7806 | switch (encoding) |
| 7807 | { |
| 7808 | case eEncodingT1: |
| 7809 | // d = UInt(Rd); m = UInt(Rm); rotation = 0; |
| 7810 | d = Bits32 (opcode, 2, 0); |
| 7811 | m = Bits32 (opcode, 5, 3); |
| 7812 | rotation = 0; |
| 7813 | |
| 7814 | break; |
| 7815 | |
| 7816 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7817 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7818 | d = Bits32 (opcode, 11, 8); |
| 7819 | m = Bits32 (opcode, 3, 0); |
| 7820 | rotation = Bits32 (opcode, 5, 4) << 3; |
| 7821 | |
| 7822 | // if BadReg(d) || BadReg(m) then UNPREDICTABLE; |
| 7823 | if (BadReg (d) || BadReg (m)) |
| 7824 | return false; |
| 7825 | |
| 7826 | break; |
| 7827 | |
| 7828 | case eEncodingA1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7829 | // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 7830 | d = Bits32 (opcode, 15, 12); |
| 7831 | m = Bits32 (opcode, 3, 0); |
| 7832 | rotation = Bits32 (opcode, 11, 10) << 3; |
| 7833 | |
| 7834 | // if d == 15 || m == 15 then UNPREDICTABLE; |
| 7835 | if ((d == 15) || (m == 15)) |
| 7836 | return false; |
| 7837 | |
| 7838 | break; |
| 7839 | |
| 7840 | default: |
| 7841 | return false; |
| 7842 | } |
| 7843 | |
| 7844 | uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 7845 | if (!success) |
| 7846 | return false; |
| 7847 | |
| 7848 | // rotated = ROR(R[m], rotation); |
| 7849 | uint64_t rotated = ROR (Rm, rotation); |
| 7850 | |
| 7851 | // R[d] = ZeroExtend(rotated<15:0>, 32); |
| 7852 | Register source_reg; |
| 7853 | source_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 7854 | |
| 7855 | EmulateInstruction::Context context; |
| 7856 | context.type = eContextRegisterLoad; |
| 7857 | context.SetRegister (source_reg); |
| 7858 | |
| 7859 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 15, 0))) |
| 7860 | return false; |
| 7861 | } |
| 7862 | return true; |
| 7863 | } |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7864 | |
| 7865 | // RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the following |
| 7866 | // word respectively. |
| 7867 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7868 | EmulateInstructionARM::EmulateRFE (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7869 | { |
| 7870 | #if 0 |
| 7871 | if ConditionPassed() then |
| 7872 | EncodingSpecificOperations(); |
| 7873 | if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then |
| 7874 | UNPREDICTABLE; |
| 7875 | else |
| 7876 | address = if increment then R[n] else R[n]-8; |
| 7877 | if wordhigher then address = address+4; |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7878 | CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE); |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7879 | BranchWritePC(MemA[address,4]); |
| 7880 | if wback then R[n] = if increment then R[n]+8 else R[n]-8; |
| 7881 | #endif |
| 7882 | |
| 7883 | bool success = false; |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7884 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 7885 | if (ConditionPassed(opcode)) |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7886 | { |
| 7887 | uint32_t n; |
| 7888 | bool wback; |
| 7889 | bool increment; |
| 7890 | bool wordhigher; |
| 7891 | |
| 7892 | // EncodingSpecificOperations(); |
| 7893 | switch (encoding) |
| 7894 | { |
| 7895 | case eEncodingT1: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7896 | // n = UInt(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE; |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7897 | n = Bits32 (opcode, 19, 16); |
| 7898 | wback = BitIsSet (opcode, 21); |
| 7899 | increment = false; |
| 7900 | wordhigher = false; |
| 7901 | |
| 7902 | // if n == 15 then UNPREDICTABLE; |
| 7903 | if (n == 15) |
| 7904 | return false; |
| 7905 | |
| 7906 | // if InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 7907 | if (InITBlock() && !LastInITBlock()) |
| 7908 | return false; |
| 7909 | |
| 7910 | break; |
| 7911 | |
| 7912 | case eEncodingT2: |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7913 | // n = UInt(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE; |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7914 | n = Bits32 (opcode, 19, 16); |
| 7915 | wback = BitIsSet (opcode, 21); |
| 7916 | increment = true; |
| 7917 | wordhigher = false; |
| 7918 | |
| 7919 | // if n == 15 then UNPREDICTABLE; |
| 7920 | if (n == 15) |
| 7921 | return false; |
| 7922 | |
| 7923 | // if InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 7924 | if (InITBlock() && !LastInITBlock()) |
| 7925 | return false; |
| 7926 | |
| 7927 | break; |
| 7928 | |
| 7929 | case eEncodingA1: |
| 7930 | // n = UInt(Rn); |
| 7931 | n = Bits32 (opcode, 19, 16); |
| 7932 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7933 | // wback = (W == '1'); inc = (U == '1'); wordhigher = (P == U); |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7934 | wback = BitIsSet (opcode, 21); |
| 7935 | increment = BitIsSet (opcode, 23); |
| 7936 | wordhigher = (Bit32 (opcode, 24) == Bit32 (opcode, 23)); |
| 7937 | |
| 7938 | // if n == 15 then UNPREDICTABLE; |
| 7939 | if (n == 15) |
| 7940 | return false; |
| 7941 | |
| 7942 | break; |
| 7943 | |
| 7944 | default: |
| 7945 | return false; |
| 7946 | } |
| 7947 | |
| 7948 | // if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then |
| 7949 | if (!CurrentModeIsPrivileged ()) |
| 7950 | // UNPREDICTABLE; |
| 7951 | return false; |
| 7952 | else |
| 7953 | { |
| 7954 | uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 7955 | if (!success) |
| 7956 | return false; |
| 7957 | |
| 7958 | addr_t address; |
| 7959 | // address = if increment then R[n] else R[n]-8; |
| 7960 | if (increment) |
| 7961 | address = Rn; |
| 7962 | else |
| 7963 | address = Rn - 8; |
| 7964 | |
| 7965 | // if wordhigher then address = address+4; |
| 7966 | if (wordhigher) |
| 7967 | address = address + 4; |
| 7968 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 7969 | // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE); |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 7970 | Register base_reg; |
| 7971 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 7972 | |
| 7973 | EmulateInstruction::Context context; |
| 7974 | context.type = eContextReturnFromException; |
| 7975 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 7976 | |
| 7977 | uint64_t data = MemARead (context, address + 4, 4, 0, &success); |
| 7978 | if (!success) |
| 7979 | return false; |
| 7980 | |
| 7981 | CPSRWriteByInstr (data, 15, true); |
| 7982 | |
| 7983 | // BranchWritePC(MemA[address,4]); |
| 7984 | uint64_t data2 = MemARead (context, address, 4, 0, &success); |
| 7985 | if (!success) |
| 7986 | return false; |
| 7987 | |
| 7988 | BranchWritePC (context, data2); |
| 7989 | |
| 7990 | // if wback then R[n] = if increment then R[n]+8 else R[n]-8; |
| 7991 | if (wback) |
| 7992 | { |
| 7993 | context.type = eContextAdjustBaseRegister; |
| 7994 | if (increment) |
| 7995 | { |
| 7996 | context.SetOffset (8); |
| 7997 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + 8)) |
| 7998 | return false; |
| 7999 | } |
| 8000 | else |
| 8001 | { |
| 8002 | context.SetOffset (-8); |
| 8003 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn - 8)) |
| 8004 | return false; |
| 8005 | } |
| 8006 | } // if wback |
| 8007 | } |
| 8008 | } // if ConditionPassed() |
| 8009 | return true; |
| 8010 | } |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 8011 | |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8012 | // Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value, |
| 8013 | // and writes the result to the destination register. It can optionally update the condition flags based on |
| 8014 | // the result. |
| 8015 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8016 | EmulateInstructionARM::EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8017 | { |
| 8018 | #if 0 |
| 8019 | // ARM pseudo code... |
| 8020 | if ConditionPassed() then |
| 8021 | EncodingSpecificOperations(); |
| 8022 | result = R[n] EOR imm32; |
| 8023 | if d == 15 then // Can only occur for ARM encoding |
| 8024 | ALUWritePC(result); // setflags is always FALSE here |
| 8025 | else |
| 8026 | R[d] = result; |
| 8027 | if setflags then |
| 8028 | APSR.N = result<31>; |
| 8029 | APSR.Z = IsZeroBit(result); |
| 8030 | APSR.C = carry; |
| 8031 | // APSR.V unchanged |
| 8032 | #endif |
| 8033 | |
| 8034 | bool success = false; |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8035 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8036 | if (ConditionPassed(opcode)) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8037 | { |
| 8038 | uint32_t Rd, Rn; |
| 8039 | uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn |
| 8040 | bool setflags; |
| 8041 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 8042 | switch (encoding) |
| 8043 | { |
| 8044 | case eEncodingT1: |
| 8045 | Rd = Bits32(opcode, 11, 8); |
| 8046 | Rn = Bits32(opcode, 19, 16); |
| 8047 | setflags = BitIsSet(opcode, 20); |
| 8048 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
| 8049 | // if Rd == '1111' && S == '1' then SEE TEQ (immediate); |
| 8050 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8051 | return EmulateTEQImm (opcode, eEncodingT1); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8052 | if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) |
| 8053 | return false; |
| 8054 | break; |
| 8055 | case eEncodingA1: |
| 8056 | Rd = Bits32(opcode, 15, 12); |
| 8057 | Rn = Bits32(opcode, 19, 16); |
| 8058 | setflags = BitIsSet(opcode, 20); |
| 8059 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
| 8060 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8061 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8062 | if (Rd == 15 && setflags) |
| 8063 | return false; |
| 8064 | break; |
| 8065 | default: |
| 8066 | return false; |
| 8067 | } |
| 8068 | |
| 8069 | // Read the first operand. |
| 8070 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8071 | if (!success) |
| 8072 | return false; |
| 8073 | |
| 8074 | uint32_t result = val1 ^ imm32; |
| 8075 | |
| 8076 | EmulateInstruction::Context context; |
| 8077 | context.type = EmulateInstruction::eContextImmediate; |
| 8078 | context.SetNoArgs (); |
| 8079 | |
| 8080 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 8081 | return false; |
| 8082 | } |
| 8083 | return true; |
| 8084 | } |
| 8085 | |
| 8086 | // Bitwise Exclusive OR (register) performs a bitwise exclusive OR of a register value and an |
| 8087 | // optionally-shifted register value, and writes the result to the destination register. |
| 8088 | // It can optionally update the condition flags based on the result. |
| 8089 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8090 | EmulateInstructionARM::EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8091 | { |
| 8092 | #if 0 |
| 8093 | // ARM pseudo code... |
| 8094 | if ConditionPassed() then |
| 8095 | EncodingSpecificOperations(); |
| 8096 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 8097 | result = R[n] EOR shifted; |
| 8098 | if d == 15 then // Can only occur for ARM encoding |
| 8099 | ALUWritePC(result); // setflags is always FALSE here |
| 8100 | else |
| 8101 | R[d] = result; |
| 8102 | if setflags then |
| 8103 | APSR.N = result<31>; |
| 8104 | APSR.Z = IsZeroBit(result); |
| 8105 | APSR.C = carry; |
| 8106 | // APSR.V unchanged |
| 8107 | #endif |
| 8108 | |
| 8109 | bool success = false; |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8110 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8111 | if (ConditionPassed(opcode)) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8112 | { |
| 8113 | uint32_t Rd, Rn, Rm; |
| 8114 | ARM_ShifterType shift_t; |
| 8115 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 8116 | bool setflags; |
| 8117 | uint32_t carry; |
| 8118 | switch (encoding) |
| 8119 | { |
| 8120 | case eEncodingT1: |
| 8121 | Rd = Rn = Bits32(opcode, 2, 0); |
| 8122 | Rm = Bits32(opcode, 5, 3); |
| 8123 | setflags = !InITBlock(); |
| 8124 | shift_t = SRType_LSL; |
| 8125 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8126 | break; |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8127 | case eEncodingT2: |
| 8128 | Rd = Bits32(opcode, 11, 8); |
| 8129 | Rn = Bits32(opcode, 19, 16); |
| 8130 | Rm = Bits32(opcode, 3, 0); |
| 8131 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 8132 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
| 8133 | // if Rd == '1111' && S == '1' then SEE TEQ (register); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8134 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8135 | return EmulateTEQReg (opcode, eEncodingT1); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8136 | if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm)) |
| 8137 | return false; |
| 8138 | break; |
| 8139 | case eEncodingA1: |
| 8140 | Rd = Bits32(opcode, 15, 12); |
| 8141 | Rn = Bits32(opcode, 19, 16); |
| 8142 | Rm = Bits32(opcode, 3, 0); |
| 8143 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 8144 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8145 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8146 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8147 | if (Rd == 15 && setflags) |
| 8148 | return false; |
| 8149 | break; |
| 8150 | default: |
| 8151 | return false; |
| 8152 | } |
| 8153 | |
| 8154 | // Read the first operand. |
| 8155 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8156 | if (!success) |
| 8157 | return false; |
| 8158 | |
| 8159 | // Read the second operand. |
| 8160 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 8161 | if (!success) |
| 8162 | return false; |
| 8163 | |
| 8164 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
| 8165 | uint32_t result = val1 ^ shifted; |
| 8166 | |
| 8167 | EmulateInstruction::Context context; |
| 8168 | context.type = EmulateInstruction::eContextImmediate; |
| 8169 | context.SetNoArgs (); |
| 8170 | |
| 8171 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 8172 | return false; |
| 8173 | } |
| 8174 | return true; |
| 8175 | } |
| 8176 | |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8177 | // Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and |
| 8178 | // writes the result to the destination register. It can optionally update the condition flags based |
| 8179 | // on the result. |
| 8180 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8181 | EmulateInstructionARM::EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8182 | { |
| 8183 | #if 0 |
| 8184 | // ARM pseudo code... |
| 8185 | if ConditionPassed() then |
| 8186 | EncodingSpecificOperations(); |
| 8187 | result = R[n] OR imm32; |
| 8188 | if d == 15 then // Can only occur for ARM encoding |
| 8189 | ALUWritePC(result); // setflags is always FALSE here |
| 8190 | else |
| 8191 | R[d] = result; |
| 8192 | if setflags then |
| 8193 | APSR.N = result<31>; |
| 8194 | APSR.Z = IsZeroBit(result); |
| 8195 | APSR.C = carry; |
| 8196 | // APSR.V unchanged |
| 8197 | #endif |
| 8198 | |
| 8199 | bool success = false; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8200 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8201 | if (ConditionPassed(opcode)) |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8202 | { |
| 8203 | uint32_t Rd, Rn; |
| 8204 | uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn |
| 8205 | bool setflags; |
| 8206 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 8207 | switch (encoding) |
| 8208 | { |
| 8209 | case eEncodingT1: |
| 8210 | Rd = Bits32(opcode, 11, 8); |
| 8211 | Rn = Bits32(opcode, 19, 16); |
| 8212 | setflags = BitIsSet(opcode, 20); |
| 8213 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 8214 | // if Rn == '1111' then SEE MOV (immediate); |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8215 | if (Rn == 15) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8216 | return EmulateMOVRdImm (opcode, eEncodingT2); |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8217 | if (BadReg(Rd) || Rn == 13) |
| 8218 | return false; |
| 8219 | break; |
| 8220 | case eEncodingA1: |
| 8221 | Rd = Bits32(opcode, 15, 12); |
| 8222 | Rn = Bits32(opcode, 19, 16); |
| 8223 | setflags = BitIsSet(opcode, 20); |
| 8224 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
| 8225 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8226 | if (Rd == 15 && setflags) |
| 8227 | return false; |
| 8228 | break; |
| 8229 | default: |
| 8230 | return false; |
| 8231 | } |
| 8232 | |
| 8233 | // Read the first operand. |
| 8234 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8235 | if (!success) |
| 8236 | return false; |
| 8237 | |
| 8238 | uint32_t result = val1 | imm32; |
| 8239 | |
| 8240 | EmulateInstruction::Context context; |
| 8241 | context.type = EmulateInstruction::eContextImmediate; |
| 8242 | context.SetNoArgs (); |
| 8243 | |
| 8244 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 8245 | return false; |
| 8246 | } |
| 8247 | return true; |
| 8248 | } |
| 8249 | |
| 8250 | // Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register |
| 8251 | // value, and writes the result to the destination register. It can optionally update the condition flags based |
| 8252 | // on the result. |
| 8253 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8254 | EmulateInstructionARM::EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8255 | { |
| 8256 | #if 0 |
| 8257 | // ARM pseudo code... |
| 8258 | if ConditionPassed() then |
| 8259 | EncodingSpecificOperations(); |
| 8260 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 8261 | result = R[n] OR shifted; |
| 8262 | if d == 15 then // Can only occur for ARM encoding |
| 8263 | ALUWritePC(result); // setflags is always FALSE here |
| 8264 | else |
| 8265 | R[d] = result; |
| 8266 | if setflags then |
| 8267 | APSR.N = result<31>; |
| 8268 | APSR.Z = IsZeroBit(result); |
| 8269 | APSR.C = carry; |
| 8270 | // APSR.V unchanged |
| 8271 | #endif |
| 8272 | |
| 8273 | bool success = false; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8274 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8275 | if (ConditionPassed(opcode)) |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8276 | { |
| 8277 | uint32_t Rd, Rn, Rm; |
| 8278 | ARM_ShifterType shift_t; |
| 8279 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 8280 | bool setflags; |
| 8281 | uint32_t carry; |
| 8282 | switch (encoding) |
| 8283 | { |
| 8284 | case eEncodingT1: |
| 8285 | Rd = Rn = Bits32(opcode, 2, 0); |
| 8286 | Rm = Bits32(opcode, 5, 3); |
| 8287 | setflags = !InITBlock(); |
| 8288 | shift_t = SRType_LSL; |
| 8289 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8290 | break; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8291 | case eEncodingT2: |
| 8292 | Rd = Bits32(opcode, 11, 8); |
| 8293 | Rn = Bits32(opcode, 19, 16); |
| 8294 | Rm = Bits32(opcode, 3, 0); |
| 8295 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 8296 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
| 8297 | // if Rn == '1111' then SEE MOV (register); |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8298 | if (Rn == 15) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8299 | return EmulateMOVRdRm (opcode, eEncodingT3); |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8300 | if (BadReg(Rd) || Rn == 13 || BadReg(Rm)) |
| 8301 | return false; |
| 8302 | break; |
| 8303 | case eEncodingA1: |
| 8304 | Rd = Bits32(opcode, 15, 12); |
| 8305 | Rn = Bits32(opcode, 19, 16); |
| 8306 | Rm = Bits32(opcode, 3, 0); |
| 8307 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 8308 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8309 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8310 | if (Rd == 15 && setflags) |
| 8311 | return false; |
| 8312 | break; |
| 8313 | default: |
| 8314 | return false; |
| 8315 | } |
| 8316 | |
| 8317 | // Read the first operand. |
| 8318 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8319 | if (!success) |
| 8320 | return false; |
| 8321 | |
| 8322 | // Read the second operand. |
| 8323 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 8324 | if (!success) |
| 8325 | return false; |
| 8326 | |
| 8327 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8328 | uint32_t result = val1 | shifted; |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 8329 | |
| 8330 | EmulateInstruction::Context context; |
| 8331 | context.type = EmulateInstruction::eContextImmediate; |
| 8332 | context.SetNoArgs (); |
| 8333 | |
| 8334 | if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) |
| 8335 | return false; |
| 8336 | } |
| 8337 | return true; |
| 8338 | } |
| 8339 | |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8340 | // Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to |
| 8341 | // the destination register. It can optionally update the condition flags based on the result. |
| 8342 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8343 | EmulateInstructionARM::EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8344 | { |
| 8345 | #if 0 |
| 8346 | // ARM pseudo code... |
| 8347 | if ConditionPassed() then |
| 8348 | EncodingSpecificOperations(); |
| 8349 | (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, '1'); |
| 8350 | if d == 15 then // Can only occur for ARM encoding |
| 8351 | ALUWritePC(result); // setflags is always FALSE here |
| 8352 | else |
| 8353 | R[d] = result; |
| 8354 | if setflags then |
| 8355 | APSR.N = result<31>; |
| 8356 | APSR.Z = IsZeroBit(result); |
| 8357 | APSR.C = carry; |
| 8358 | APSR.V = overflow; |
| 8359 | #endif |
| 8360 | |
| 8361 | bool success = false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8362 | |
| 8363 | uint32_t Rd; // the destination register |
| 8364 | uint32_t Rn; // the first operand |
| 8365 | bool setflags; |
| 8366 | uint32_t imm32; // the immediate value to be added to the value obtained from Rn |
| 8367 | switch (encoding) { |
| 8368 | case eEncodingT1: |
| 8369 | Rd = Bits32(opcode, 2, 0); |
| 8370 | Rn = Bits32(opcode, 5, 3); |
| 8371 | setflags = !InITBlock(); |
| 8372 | imm32 = 0; |
| 8373 | break; |
| 8374 | case eEncodingT2: |
| 8375 | Rd = Bits32(opcode, 11, 8); |
| 8376 | Rn = Bits32(opcode, 19, 16); |
| 8377 | setflags = BitIsSet(opcode, 20); |
| 8378 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 8379 | if (BadReg(Rd) || BadReg(Rn)) |
| 8380 | return false; |
| 8381 | break; |
| 8382 | case eEncodingA1: |
| 8383 | Rd = Bits32(opcode, 15, 12); |
| 8384 | Rn = Bits32(opcode, 19, 16); |
| 8385 | setflags = BitIsSet(opcode, 20); |
| 8386 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 8387 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8388 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8389 | if (Rd == 15 && setflags) |
| 8390 | return false; |
| 8391 | break; |
| 8392 | default: |
| 8393 | return false; |
| 8394 | } |
| 8395 | // Read the register value from the operand register Rn. |
| 8396 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 8397 | if (!success) |
| 8398 | return false; |
| 8399 | |
| 8400 | AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1); |
| 8401 | |
| 8402 | EmulateInstruction::Context context; |
| 8403 | context.type = EmulateInstruction::eContextImmediate; |
| 8404 | context.SetNoArgs (); |
| 8405 | |
| 8406 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8407 | return false; |
| 8408 | |
| 8409 | return true; |
| 8410 | } |
| 8411 | |
| 8412 | // Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the |
| 8413 | // result to the destination register. It can optionally update the condition flags based on the result. |
| 8414 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8415 | EmulateInstructionARM::EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8416 | { |
| 8417 | #if 0 |
| 8418 | // ARM pseudo code... |
| 8419 | if ConditionPassed() then |
| 8420 | EncodingSpecificOperations(); |
| 8421 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 8422 | (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, '1'); |
| 8423 | if d == 15 then // Can only occur for ARM encoding |
| 8424 | ALUWritePC(result); // setflags is always FALSE here |
| 8425 | else |
| 8426 | R[d] = result; |
| 8427 | if setflags then |
| 8428 | APSR.N = result<31>; |
| 8429 | APSR.Z = IsZeroBit(result); |
| 8430 | APSR.C = carry; |
| 8431 | APSR.V = overflow; |
| 8432 | #endif |
| 8433 | |
| 8434 | bool success = false; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 8435 | |
| 8436 | uint32_t Rd; // the destination register |
| 8437 | uint32_t Rn; // the first operand |
| 8438 | uint32_t Rm; // the second operand |
| 8439 | bool setflags; |
| 8440 | ARM_ShifterType shift_t; |
| 8441 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 8442 | switch (encoding) { |
| 8443 | case eEncodingT1: |
| 8444 | Rd = Bits32(opcode, 11, 8); |
| 8445 | Rn = Bits32(opcode, 19, 16); |
| 8446 | Rm = Bits32(opcode, 3, 0); |
| 8447 | setflags = BitIsSet(opcode, 20); |
| 8448 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
| 8449 | // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; |
| 8450 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 8451 | return false; |
| 8452 | break; |
| 8453 | case eEncodingA1: |
| 8454 | Rd = Bits32(opcode, 15, 12); |
| 8455 | Rn = Bits32(opcode, 19, 16); |
| 8456 | Rm = Bits32(opcode, 3, 0); |
| 8457 | setflags = BitIsSet(opcode, 20); |
| 8458 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
| 8459 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8460 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8461 | if (Rd == 15 && setflags) |
| 8462 | return false; |
| 8463 | break; |
| 8464 | default: |
| 8465 | return false; |
| 8466 | } |
| 8467 | // Read the register value from register Rn. |
| 8468 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8469 | if (!success) |
| 8470 | return false; |
| 8471 | |
| 8472 | // Read the register value from register Rm. |
| 8473 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 8474 | if (!success) |
| 8475 | return false; |
| 8476 | |
| 8477 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
| 8478 | AddWithCarryResult res = AddWithCarry(~val1, shifted, 1); |
| 8479 | |
| 8480 | EmulateInstruction::Context context; |
| 8481 | context.type = EmulateInstruction::eContextImmediate; |
| 8482 | context.SetNoArgs(); |
| 8483 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8484 | return false; |
| 8485 | |
| 8486 | return true; |
| 8487 | } |
| 8488 | |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 8489 | // Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from |
| 8490 | // an immediate value, and writes the result to the destination register. It can optionally update the condition |
| 8491 | // flags based on the result. |
| 8492 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8493 | EmulateInstructionARM::EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 8494 | { |
| 8495 | #if 0 |
| 8496 | // ARM pseudo code... |
| 8497 | if ConditionPassed() then |
| 8498 | EncodingSpecificOperations(); |
| 8499 | (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, APSR.C); |
| 8500 | if d == 15 then |
| 8501 | ALUWritePC(result); // setflags is always FALSE here |
| 8502 | else |
| 8503 | R[d] = result; |
| 8504 | if setflags then |
| 8505 | APSR.N = result<31>; |
| 8506 | APSR.Z = IsZeroBit(result); |
| 8507 | APSR.C = carry; |
| 8508 | APSR.V = overflow; |
| 8509 | #endif |
| 8510 | |
| 8511 | bool success = false; |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 8512 | |
| 8513 | uint32_t Rd; // the destination register |
| 8514 | uint32_t Rn; // the first operand |
| 8515 | bool setflags; |
| 8516 | uint32_t imm32; // the immediate value to be added to the value obtained from Rn |
| 8517 | switch (encoding) { |
| 8518 | case eEncodingA1: |
| 8519 | Rd = Bits32(opcode, 15, 12); |
| 8520 | Rn = Bits32(opcode, 19, 16); |
| 8521 | setflags = BitIsSet(opcode, 20); |
| 8522 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 8523 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8524 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8525 | if (Rd == 15 && setflags) |
| 8526 | return false; |
| 8527 | break; |
| 8528 | default: |
| 8529 | return false; |
| 8530 | } |
| 8531 | // Read the register value from the operand register Rn. |
| 8532 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 8533 | if (!success) |
| 8534 | return false; |
| 8535 | |
| 8536 | AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C); |
| 8537 | |
| 8538 | EmulateInstruction::Context context; |
| 8539 | context.type = EmulateInstruction::eContextImmediate; |
| 8540 | context.SetNoArgs (); |
| 8541 | |
| 8542 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8543 | return false; |
| 8544 | |
| 8545 | return true; |
| 8546 | } |
| 8547 | |
| 8548 | // Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an |
| 8549 | // optionally-shifted register value, and writes the result to the destination register. It can optionally update the |
| 8550 | // condition flags based on the result. |
| 8551 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8552 | EmulateInstructionARM::EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 8553 | { |
| 8554 | #if 0 |
| 8555 | // ARM pseudo code... |
| 8556 | if ConditionPassed() then |
| 8557 | EncodingSpecificOperations(); |
| 8558 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 8559 | (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, APSR.C); |
| 8560 | if d == 15 then |
| 8561 | ALUWritePC(result); // setflags is always FALSE here |
| 8562 | else |
| 8563 | R[d] = result; |
| 8564 | if setflags then |
| 8565 | APSR.N = result<31>; |
| 8566 | APSR.Z = IsZeroBit(result); |
| 8567 | APSR.C = carry; |
| 8568 | APSR.V = overflow; |
| 8569 | #endif |
| 8570 | |
| 8571 | bool success = false; |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 8572 | |
| 8573 | uint32_t Rd; // the destination register |
| 8574 | uint32_t Rn; // the first operand |
| 8575 | uint32_t Rm; // the second operand |
| 8576 | bool setflags; |
| 8577 | ARM_ShifterType shift_t; |
| 8578 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 8579 | switch (encoding) { |
| 8580 | case eEncodingA1: |
| 8581 | Rd = Bits32(opcode, 15, 12); |
| 8582 | Rn = Bits32(opcode, 19, 16); |
| 8583 | Rm = Bits32(opcode, 3, 0); |
| 8584 | setflags = BitIsSet(opcode, 20); |
| 8585 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
| 8586 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8587 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8588 | if (Rd == 15 && setflags) |
| 8589 | return false; |
| 8590 | break; |
| 8591 | default: |
| 8592 | return false; |
| 8593 | } |
| 8594 | // Read the register value from register Rn. |
| 8595 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8596 | if (!success) |
| 8597 | return false; |
| 8598 | |
| 8599 | // Read the register value from register Rm. |
| 8600 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 8601 | if (!success) |
| 8602 | return false; |
| 8603 | |
| 8604 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
| 8605 | AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C); |
| 8606 | |
| 8607 | EmulateInstruction::Context context; |
| 8608 | context.type = EmulateInstruction::eContextImmediate; |
| 8609 | context.SetNoArgs(); |
| 8610 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8611 | return false; |
| 8612 | |
| 8613 | return true; |
| 8614 | } |
| 8615 | |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8616 | // Subtract with Carry (immediate) subtracts an immediate value and the value of |
| 8617 | // NOT (Carry flag) from a register value, and writes the result to the destination register. |
| 8618 | // It can optionally update the condition flags based on the result. |
| 8619 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8620 | EmulateInstructionARM::EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8621 | { |
| 8622 | #if 0 |
| 8623 | // ARM pseudo code... |
| 8624 | if ConditionPassed() then |
| 8625 | EncodingSpecificOperations(); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8626 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C); |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8627 | if d == 15 then // Can only occur for ARM encoding |
| 8628 | ALUWritePC(result); // setflags is always FALSE here |
| 8629 | else |
| 8630 | R[d] = result; |
| 8631 | if setflags then |
| 8632 | APSR.N = result<31>; |
| 8633 | APSR.Z = IsZeroBit(result); |
| 8634 | APSR.C = carry; |
| 8635 | APSR.V = overflow; |
| 8636 | #endif |
| 8637 | |
| 8638 | bool success = false; |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8639 | |
| 8640 | uint32_t Rd; // the destination register |
| 8641 | uint32_t Rn; // the first operand |
| 8642 | bool setflags; |
| 8643 | uint32_t imm32; // the immediate value to be added to the value obtained from Rn |
| 8644 | switch (encoding) { |
| 8645 | case eEncodingT1: |
| 8646 | Rd = Bits32(opcode, 11, 8); |
| 8647 | Rn = Bits32(opcode, 19, 16); |
| 8648 | setflags = BitIsSet(opcode, 20); |
| 8649 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 8650 | if (BadReg(Rd) || BadReg(Rn)) |
| 8651 | return false; |
| 8652 | break; |
| 8653 | case eEncodingA1: |
| 8654 | Rd = Bits32(opcode, 15, 12); |
| 8655 | Rn = Bits32(opcode, 19, 16); |
| 8656 | setflags = BitIsSet(opcode, 20); |
| 8657 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 8658 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8659 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8660 | if (Rd == 15 && setflags) |
| 8661 | return false; |
| 8662 | break; |
| 8663 | default: |
| 8664 | return false; |
| 8665 | } |
| 8666 | // Read the register value from the operand register Rn. |
| 8667 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 8668 | if (!success) |
| 8669 | return false; |
| 8670 | |
| 8671 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C); |
| 8672 | |
| 8673 | EmulateInstruction::Context context; |
| 8674 | context.type = EmulateInstruction::eContextImmediate; |
| 8675 | context.SetNoArgs (); |
| 8676 | |
| 8677 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8678 | return false; |
| 8679 | |
| 8680 | return true; |
| 8681 | } |
| 8682 | |
| 8683 | // Subtract with Carry (register) subtracts an optionally-shifted register value and the value of |
| 8684 | // NOT (Carry flag) from a register value, and writes the result to the destination register. |
| 8685 | // It can optionally update the condition flags based on the result. |
| 8686 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8687 | EmulateInstructionARM::EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8688 | { |
| 8689 | #if 0 |
| 8690 | // ARM pseudo code... |
| 8691 | if ConditionPassed() then |
| 8692 | EncodingSpecificOperations(); |
| 8693 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 8694 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C); |
| 8695 | if d == 15 then // Can only occur for ARM encoding |
| 8696 | ALUWritePC(result); // setflags is always FALSE here |
| 8697 | else |
| 8698 | R[d] = result; |
| 8699 | if setflags then |
| 8700 | APSR.N = result<31>; |
| 8701 | APSR.Z = IsZeroBit(result); |
| 8702 | APSR.C = carry; |
| 8703 | APSR.V = overflow; |
| 8704 | #endif |
| 8705 | |
| 8706 | bool success = false; |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 8707 | |
| 8708 | uint32_t Rd; // the destination register |
| 8709 | uint32_t Rn; // the first operand |
| 8710 | uint32_t Rm; // the second operand |
| 8711 | bool setflags; |
| 8712 | ARM_ShifterType shift_t; |
| 8713 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 8714 | switch (encoding) { |
| 8715 | case eEncodingT1: |
| 8716 | Rd = Rn = Bits32(opcode, 2, 0); |
| 8717 | Rm = Bits32(opcode, 5, 3); |
| 8718 | setflags = !InITBlock(); |
| 8719 | shift_t = SRType_LSL; |
| 8720 | shift_n = 0; |
| 8721 | break; |
| 8722 | case eEncodingT2: |
| 8723 | Rd = Bits32(opcode, 11, 8); |
| 8724 | Rn = Bits32(opcode, 19, 16); |
| 8725 | Rm = Bits32(opcode, 3, 0); |
| 8726 | setflags = BitIsSet(opcode, 20); |
| 8727 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
| 8728 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 8729 | return false; |
| 8730 | break; |
| 8731 | case eEncodingA1: |
| 8732 | Rd = Bits32(opcode, 15, 12); |
| 8733 | Rn = Bits32(opcode, 19, 16); |
| 8734 | Rm = Bits32(opcode, 3, 0); |
| 8735 | setflags = BitIsSet(opcode, 20); |
| 8736 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
| 8737 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8738 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8739 | if (Rd == 15 && setflags) |
| 8740 | return false; |
| 8741 | break; |
| 8742 | default: |
| 8743 | return false; |
| 8744 | } |
| 8745 | // Read the register value from register Rn. |
| 8746 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8747 | if (!success) |
| 8748 | return false; |
| 8749 | |
| 8750 | // Read the register value from register Rm. |
| 8751 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 8752 | if (!success) |
| 8753 | return false; |
| 8754 | |
| 8755 | uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); |
| 8756 | AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C); |
| 8757 | |
| 8758 | EmulateInstruction::Context context; |
| 8759 | context.type = EmulateInstruction::eContextImmediate; |
| 8760 | context.SetNoArgs(); |
| 8761 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8762 | return false; |
| 8763 | |
| 8764 | return true; |
| 8765 | } |
| 8766 | |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8767 | // This instruction subtracts an immediate value from a register value, and writes the result |
| 8768 | // to the destination register. It can optionally update the condition flags based on the result. |
| 8769 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8770 | EmulateInstructionARM::EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8771 | { |
| 8772 | #if 0 |
| 8773 | // ARM pseudo code... |
| 8774 | if ConditionPassed() then |
| 8775 | EncodingSpecificOperations(); |
| 8776 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 8777 | R[d] = result; |
| 8778 | if setflags then |
| 8779 | APSR.N = result<31>; |
| 8780 | APSR.Z = IsZeroBit(result); |
| 8781 | APSR.C = carry; |
| 8782 | APSR.V = overflow; |
| 8783 | #endif |
| 8784 | |
| 8785 | bool success = false; |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8786 | |
| 8787 | uint32_t Rd; // the destination register |
| 8788 | uint32_t Rn; // the first operand |
| 8789 | bool setflags; |
| 8790 | uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn |
| 8791 | switch (encoding) { |
| 8792 | case eEncodingT1: |
| 8793 | Rd = Bits32(opcode, 2, 0); |
| 8794 | Rn = Bits32(opcode, 5, 3); |
| 8795 | setflags = !InITBlock(); |
| 8796 | imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32) |
| 8797 | break; |
| 8798 | case eEncodingT2: |
| 8799 | Rd = Rn = Bits32(opcode, 10, 8); |
| 8800 | setflags = !InITBlock(); |
| 8801 | imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) |
| 8802 | break; |
| 8803 | case eEncodingT3: |
| 8804 | Rd = Bits32(opcode, 11, 8); |
| 8805 | Rn = Bits32(opcode, 19, 16); |
| 8806 | setflags = BitIsSet(opcode, 20); |
| 8807 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 8808 | |
| 8809 | // if Rd == '1111' && S == '1' then SEE CMP (immediate); |
| 8810 | if (Rd == 15 && setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8811 | return EmulateCMPImm (opcode, eEncodingT2); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8812 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 8813 | // if Rn == '1101' then SEE SUB (SP minus immediate); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8814 | if (Rn == 13) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8815 | return EmulateSUBSPImm (opcode, eEncodingT2); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8816 | |
| 8817 | // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE; |
| 8818 | if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15) |
| 8819 | return false; |
| 8820 | break; |
| 8821 | case eEncodingT4: |
| 8822 | Rd = Bits32(opcode, 11, 8); |
| 8823 | Rn = Bits32(opcode, 19, 16); |
| 8824 | setflags = BitIsSet(opcode, 20); |
| 8825 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 8826 | |
| 8827 | // if Rn == '1111' then SEE ADR; |
| 8828 | if (Rn == 15) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8829 | return EmulateADR (opcode, eEncodingT2); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8830 | |
| 8831 | // if Rn == '1101' then SEE SUB (SP minus immediate); |
| 8832 | if (Rn == 13) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8833 | return EmulateSUBSPImm (opcode, eEncodingT3); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8834 | |
| 8835 | if (BadReg(Rd)) |
| 8836 | return false; |
| 8837 | break; |
| 8838 | default: |
| 8839 | return false; |
| 8840 | } |
| 8841 | // Read the register value from the operand register Rn. |
| 8842 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 8843 | if (!success) |
| 8844 | return false; |
| 8845 | |
| 8846 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 8847 | |
| 8848 | EmulateInstruction::Context context; |
| 8849 | context.type = EmulateInstruction::eContextImmediate; |
| 8850 | context.SetNoArgs (); |
| 8851 | |
| 8852 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8853 | return false; |
| 8854 | |
| 8855 | return true; |
| 8856 | } |
| 8857 | |
| 8858 | // This instruction subtracts an immediate value from a register value, and writes the result |
| 8859 | // to the destination register. It can optionally update the condition flags based on the result. |
| 8860 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8861 | EmulateInstructionARM::EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8862 | { |
| 8863 | #if 0 |
| 8864 | // ARM pseudo code... |
| 8865 | if ConditionPassed() then |
| 8866 | EncodingSpecificOperations(); |
| 8867 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 8868 | if d == 15 then |
| 8869 | ALUWritePC(result); // setflags is always FALSE here |
| 8870 | else |
| 8871 | R[d] = result; |
| 8872 | if setflags then |
| 8873 | APSR.N = result<31>; |
| 8874 | APSR.Z = IsZeroBit(result); |
| 8875 | APSR.C = carry; |
| 8876 | APSR.V = overflow; |
| 8877 | #endif |
| 8878 | |
| 8879 | bool success = false; |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8880 | |
| 8881 | uint32_t Rd; // the destination register |
| 8882 | uint32_t Rn; // the first operand |
| 8883 | bool setflags; |
| 8884 | uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn |
| 8885 | switch (encoding) { |
| 8886 | case eEncodingA1: |
| 8887 | Rd = Bits32(opcode, 15, 12); |
| 8888 | Rn = Bits32(opcode, 19, 16); |
| 8889 | setflags = BitIsSet(opcode, 20); |
| 8890 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 8891 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 8892 | // if Rn == '1111' && S == '0' then SEE ADR; |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8893 | if (Rn == 15 && !setflags) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8894 | return EmulateADR (opcode, eEncodingA2); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8895 | |
Caroline Tice | bb48f0b | 2011-03-28 16:10:45 +0000 | [diff] [blame] | 8896 | // if Rn == '1101' then SEE SUB (SP minus immediate); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8897 | if (Rn == 13) |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8898 | return EmulateSUBSPImm (opcode, eEncodingA1); |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 8899 | |
| 8900 | // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; |
| 8901 | // TODO: Emulate SUBS PC, LR and related instructions. |
| 8902 | if (Rd == 15 && setflags) |
| 8903 | return false; |
| 8904 | break; |
| 8905 | default: |
| 8906 | return false; |
| 8907 | } |
| 8908 | // Read the register value from the operand register Rn. |
| 8909 | uint32_t reg_val = ReadCoreReg(Rn, &success); |
| 8910 | if (!success) |
| 8911 | return false; |
| 8912 | |
| 8913 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 8914 | |
| 8915 | EmulateInstruction::Context context; |
| 8916 | context.type = EmulateInstruction::eContextImmediate; |
| 8917 | context.SetNoArgs (); |
| 8918 | |
| 8919 | if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) |
| 8920 | return false; |
| 8921 | |
| 8922 | return true; |
| 8923 | } |
| 8924 | |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8925 | // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an |
| 8926 | // immediate value. It updates the condition flags based on the result, and discards the result. |
| 8927 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8928 | EmulateInstructionARM::EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8929 | { |
| 8930 | #if 0 |
| 8931 | // ARM pseudo code... |
| 8932 | if ConditionPassed() then |
| 8933 | EncodingSpecificOperations(); |
| 8934 | result = R[n] EOR imm32; |
| 8935 | APSR.N = result<31>; |
| 8936 | APSR.Z = IsZeroBit(result); |
| 8937 | APSR.C = carry; |
| 8938 | // APSR.V unchanged |
| 8939 | #endif |
| 8940 | |
| 8941 | bool success = false; |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8942 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8943 | if (ConditionPassed(opcode)) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8944 | { |
| 8945 | uint32_t Rn; |
| 8946 | uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn |
| 8947 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 8948 | switch (encoding) |
| 8949 | { |
| 8950 | case eEncodingT1: |
| 8951 | Rn = Bits32(opcode, 19, 16); |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8952 | imm32 = ThumbExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8953 | if (BadReg(Rn)) |
| 8954 | return false; |
| 8955 | break; |
| 8956 | case eEncodingA1: |
| 8957 | Rn = Bits32(opcode, 19, 16); |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8958 | imm32 = ARMExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8959 | break; |
| 8960 | default: |
| 8961 | return false; |
| 8962 | } |
| 8963 | |
| 8964 | // Read the first operand. |
| 8965 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 8966 | if (!success) |
| 8967 | return false; |
| 8968 | |
| 8969 | uint32_t result = val1 ^ imm32; |
| 8970 | |
| 8971 | EmulateInstruction::Context context; |
| 8972 | context.type = EmulateInstruction::eContextImmediate; |
| 8973 | context.SetNoArgs (); |
| 8974 | |
| 8975 | if (!WriteFlags(context, result, carry)) |
| 8976 | return false; |
| 8977 | } |
| 8978 | return true; |
| 8979 | } |
| 8980 | |
| 8981 | // Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an |
| 8982 | // optionally-shifted register value. It updates the condition flags based on the result, and discards |
| 8983 | // the result. |
| 8984 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 8985 | EmulateInstructionARM::EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 8986 | { |
| 8987 | #if 0 |
| 8988 | // ARM pseudo code... |
| 8989 | if ConditionPassed() then |
| 8990 | EncodingSpecificOperations(); |
| 8991 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 8992 | result = R[n] EOR shifted; |
| 8993 | APSR.N = result<31>; |
| 8994 | APSR.Z = IsZeroBit(result); |
| 8995 | APSR.C = carry; |
| 8996 | // APSR.V unchanged |
| 8997 | #endif |
| 8998 | |
| 8999 | bool success = false; |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 9000 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 9001 | if (ConditionPassed(opcode)) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 9002 | { |
| 9003 | uint32_t Rn, Rm; |
| 9004 | ARM_ShifterType shift_t; |
| 9005 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 9006 | uint32_t carry; |
| 9007 | switch (encoding) |
| 9008 | { |
| 9009 | case eEncodingT1: |
| 9010 | Rn = Bits32(opcode, 19, 16); |
| 9011 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 9012 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 9013 | if (BadReg(Rn) || BadReg(Rm)) |
| 9014 | return false; |
| 9015 | break; |
| 9016 | case eEncodingA1: |
| 9017 | Rn = Bits32(opcode, 19, 16); |
| 9018 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 9019 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 9020 | break; |
| 9021 | default: |
| 9022 | return false; |
| 9023 | } |
| 9024 | |
| 9025 | // Read the first operand. |
| 9026 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 9027 | if (!success) |
| 9028 | return false; |
| 9029 | |
| 9030 | // Read the second operand. |
| 9031 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 9032 | if (!success) |
| 9033 | return false; |
| 9034 | |
| 9035 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
| 9036 | uint32_t result = val1 ^ shifted; |
| 9037 | |
| 9038 | EmulateInstruction::Context context; |
| 9039 | context.type = EmulateInstruction::eContextImmediate; |
| 9040 | context.SetNoArgs (); |
| 9041 | |
| 9042 | if (!WriteFlags(context, result, carry)) |
| 9043 | return false; |
| 9044 | } |
| 9045 | return true; |
| 9046 | } |
| 9047 | |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9048 | // Test (immediate) performs a bitwise AND operation on a register value and an immediate value. |
| 9049 | // It updates the condition flags based on the result, and discards the result. |
| 9050 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 9051 | EmulateInstructionARM::EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9052 | { |
| 9053 | #if 0 |
| 9054 | // ARM pseudo code... |
| 9055 | if ConditionPassed() then |
| 9056 | EncodingSpecificOperations(); |
| 9057 | result = R[n] AND imm32; |
| 9058 | APSR.N = result<31>; |
| 9059 | APSR.Z = IsZeroBit(result); |
| 9060 | APSR.C = carry; |
| 9061 | // APSR.V unchanged |
| 9062 | #endif |
| 9063 | |
| 9064 | bool success = false; |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9065 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 9066 | if (ConditionPassed(opcode)) |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9067 | { |
| 9068 | uint32_t Rn; |
| 9069 | uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn |
| 9070 | uint32_t carry; // the carry bit after ARM/Thumb Expand operation |
| 9071 | switch (encoding) |
| 9072 | { |
| 9073 | case eEncodingT1: |
| 9074 | Rn = Bits32(opcode, 19, 16); |
| 9075 | imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) |
| 9076 | if (BadReg(Rn)) |
| 9077 | return false; |
| 9078 | break; |
| 9079 | case eEncodingA1: |
| 9080 | Rn = Bits32(opcode, 19, 16); |
| 9081 | imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) |
| 9082 | break; |
| 9083 | default: |
| 9084 | return false; |
| 9085 | } |
| 9086 | |
| 9087 | // Read the first operand. |
| 9088 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 9089 | if (!success) |
| 9090 | return false; |
| 9091 | |
| 9092 | uint32_t result = val1 & imm32; |
| 9093 | |
| 9094 | EmulateInstruction::Context context; |
| 9095 | context.type = EmulateInstruction::eContextImmediate; |
| 9096 | context.SetNoArgs (); |
| 9097 | |
| 9098 | if (!WriteFlags(context, result, carry)) |
| 9099 | return false; |
| 9100 | } |
| 9101 | return true; |
| 9102 | } |
| 9103 | |
| 9104 | // Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. |
| 9105 | // It updates the condition flags based on the result, and discards the result. |
| 9106 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 9107 | EmulateInstructionARM::EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding) |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9108 | { |
| 9109 | #if 0 |
| 9110 | // ARM pseudo code... |
| 9111 | if ConditionPassed() then |
| 9112 | EncodingSpecificOperations(); |
| 9113 | (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); |
| 9114 | result = R[n] AND shifted; |
| 9115 | APSR.N = result<31>; |
| 9116 | APSR.Z = IsZeroBit(result); |
| 9117 | APSR.C = carry; |
| 9118 | // APSR.V unchanged |
| 9119 | #endif |
| 9120 | |
| 9121 | bool success = false; |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9122 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 9123 | if (ConditionPassed(opcode)) |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9124 | { |
| 9125 | uint32_t Rn, Rm; |
| 9126 | ARM_ShifterType shift_t; |
| 9127 | uint32_t shift_n; // the shift applied to the value read from Rm |
| 9128 | uint32_t carry; |
| 9129 | switch (encoding) |
| 9130 | { |
| 9131 | case eEncodingT1: |
| 9132 | Rn = Bits32(opcode, 2, 0); |
| 9133 | Rm = Bits32(opcode, 5, 3); |
| 9134 | shift_t = SRType_LSL; |
| 9135 | shift_n = 0; |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 9136 | break; |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9137 | case eEncodingT2: |
| 9138 | Rn = Bits32(opcode, 19, 16); |
| 9139 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 9140 | shift_n = DecodeImmShiftThumb(opcode, shift_t); |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9141 | if (BadReg(Rn) || BadReg(Rm)) |
| 9142 | return false; |
| 9143 | break; |
| 9144 | case eEncodingA1: |
| 9145 | Rn = Bits32(opcode, 19, 16); |
| 9146 | Rm = Bits32(opcode, 3, 0); |
Johnny Chen | 3dd0605 | 2011-02-22 21:17:52 +0000 | [diff] [blame] | 9147 | shift_n = DecodeImmShiftARM(opcode, shift_t); |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 9148 | break; |
| 9149 | default: |
| 9150 | return false; |
| 9151 | } |
| 9152 | |
| 9153 | // Read the first operand. |
| 9154 | uint32_t val1 = ReadCoreReg(Rn, &success); |
| 9155 | if (!success) |
| 9156 | return false; |
| 9157 | |
| 9158 | // Read the second operand. |
| 9159 | uint32_t val2 = ReadCoreReg(Rm, &success); |
| 9160 | if (!success) |
| 9161 | return false; |
| 9162 | |
| 9163 | uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); |
| 9164 | uint32_t result = val1 & shifted; |
| 9165 | |
| 9166 | EmulateInstruction::Context context; |
| 9167 | context.type = EmulateInstruction::eContextImmediate; |
| 9168 | context.SetNoArgs (); |
| 9169 | |
| 9170 | if (!WriteFlags(context, result, carry)) |
| 9171 | return false; |
| 9172 | } |
| 9173 | return true; |
| 9174 | } |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9175 | |
| 9176 | // A8.6.216 SUB (SP minus register) |
| 9177 | bool |
| 9178 | EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding) |
| 9179 | { |
| 9180 | #if 0 |
| 9181 | if ConditionPassed() then |
| 9182 | EncodingSpecificOperations(); |
| 9183 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9184 | (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ‘1’); |
| 9185 | if d == 15 then // Can only occur for ARM encoding |
| 9186 | ALUWritePC(result); // setflags is always FALSE here |
| 9187 | else |
| 9188 | R[d] = result; |
| 9189 | if setflags then |
| 9190 | APSR.N = result<31>; |
| 9191 | APSR.Z = IsZeroBit(result); |
| 9192 | APSR.C = carry; |
| 9193 | APSR.V = overflow; |
| 9194 | #endif |
| 9195 | |
| 9196 | bool success = false; |
| 9197 | |
| 9198 | if (ConditionPassed(opcode)) |
| 9199 | { |
| 9200 | uint32_t d; |
| 9201 | uint32_t m; |
| 9202 | bool setflags; |
| 9203 | ARM_ShifterType shift_t; |
| 9204 | uint32_t shift_n; |
| 9205 | |
| 9206 | switch (encoding) |
| 9207 | { |
| 9208 | case eEncodingT1: |
| 9209 | // d = UInt(Rd); m = UInt(Rm); setflags = (S == ‘1’); |
| 9210 | d = Bits32 (opcode, 11, 8); |
| 9211 | m = Bits32 (opcode, 3, 0); |
| 9212 | setflags = BitIsSet (opcode, 20); |
| 9213 | |
| 9214 | // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); |
| 9215 | shift_n = DecodeImmShiftThumb (opcode, shift_t); |
| 9216 | |
| 9217 | // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE; |
| 9218 | if ((d == 13) && ((shift_t != SRType_LSL) || (shift_n > 3))) |
| 9219 | return false; |
| 9220 | |
| 9221 | // if d == 15 || BadReg(m) then UNPREDICTABLE; |
| 9222 | if ((d == 15) || BadReg (m)) |
| 9223 | return false; |
| 9224 | break; |
| 9225 | |
| 9226 | case eEncodingA1: |
| 9227 | // if Rd == ‘1111’ && S == ‘1’ then SEE SUBS PC, LR and related instructions; |
| 9228 | // d = UInt(Rd); m = UInt(Rm); setflags = (S == ‘1’); |
| 9229 | d = Bits32 (opcode, 15, 12); |
| 9230 | m = Bits32 (opcode, 3, 0); |
| 9231 | setflags = BitIsSet (opcode, 20); |
| 9232 | |
| 9233 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 9234 | shift_n = DecodeImmShiftARM (opcode, shift_t); |
| 9235 | break; |
| 9236 | |
| 9237 | default: |
| 9238 | return false; |
| 9239 | } |
| 9240 | |
| 9241 | // shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9242 | uint32_t Rm = ReadCoreReg (m, &success); |
| 9243 | if (!success) |
| 9244 | return false; |
| 9245 | |
| 9246 | uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); |
| 9247 | |
| 9248 | // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ‘1’); |
| 9249 | uint32_t sp_val = ReadCoreReg (SP_REG, &success); |
| 9250 | if (!success) |
| 9251 | return false; |
| 9252 | |
| 9253 | AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1); |
| 9254 | |
| 9255 | EmulateInstruction::Context context; |
| 9256 | context.type = eContextSubtraction; |
| 9257 | Register sp_reg; |
| 9258 | sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); |
| 9259 | Register dwarf_reg; |
| 9260 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
| 9261 | context.SetRegisterRegisterOperands (sp_reg, dwarf_reg); |
| 9262 | |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9263 | if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow)) |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9264 | return false; |
| 9265 | } |
| 9266 | return true; |
| 9267 | } |
| 9268 | |
| 9269 | |
| 9270 | // A8.6.7 ADD (register-shifted register) |
| 9271 | bool |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9272 | EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding) |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9273 | { |
| 9274 | #if 0 |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9275 | if ConditionPassed() then |
| 9276 | EncodingSpecificOperations(); |
| 9277 | shift_n = UInt(R[s]<7:0>); |
| 9278 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9279 | (result, carry, overflow) = AddWithCarry(R[n], shifted, ‘0’); |
| 9280 | R[d] = result; |
| 9281 | if setflags then |
| 9282 | APSR.N = result<31>; |
| 9283 | APSR.Z = IsZeroBit(result); |
| 9284 | APSR.C = carry; |
| 9285 | APSR.V = overflow; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9286 | #endif |
| 9287 | |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9288 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9289 | |
| 9290 | if (ConditionPassed(opcode)) |
| 9291 | { |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9292 | uint32_t d; |
| 9293 | uint32_t n; |
| 9294 | uint32_t m; |
| 9295 | uint32_t s; |
| 9296 | bool setflags; |
| 9297 | ARM_ShifterType shift_t; |
| 9298 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9299 | switch (encoding) |
| 9300 | { |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9301 | case eEncodingA1: |
| 9302 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs); |
| 9303 | d = Bits32 (opcode, 15, 12); |
| 9304 | n = Bits32 (opcode, 19, 16); |
| 9305 | m = Bits32 (opcode, 3, 0); |
| 9306 | s = Bits32 (opcode, 11, 8); |
| 9307 | |
| 9308 | // setflags = (S == ‘1’); shift_t = DecodeRegShift(type); |
| 9309 | setflags = BitIsSet (opcode, 20); |
| 9310 | shift_t = DecodeRegShift (Bits32 (opcode, 6, 5)); |
| 9311 | |
| 9312 | // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; |
| 9313 | if ((d == 15) || (m == 15) || (m == 15) || (s == 15)) |
| 9314 | return false; |
| 9315 | break; |
| 9316 | |
| 9317 | default: |
| 9318 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9319 | } |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9320 | |
| 9321 | // shift_n = UInt(R[s]<7:0>); |
| 9322 | uint32_t Rs = ReadCoreReg (s, &success); |
| 9323 | if (!success) |
| 9324 | return false; |
| 9325 | |
| 9326 | uint32_t shift_n = Bits32 (Rs, 7, 0); |
| 9327 | |
| 9328 | // shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9329 | uint32_t Rm = ReadCoreReg (m, &success); |
| 9330 | if (!success) |
| 9331 | return false; |
| 9332 | |
| 9333 | uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); |
| 9334 | |
| 9335 | // (result, carry, overflow) = AddWithCarry(R[n], shifted, ‘0’); |
| 9336 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9337 | if (!success) |
| 9338 | return false; |
| 9339 | |
| 9340 | AddWithCarryResult res = AddWithCarry (Rn, shifted, 0); |
| 9341 | |
| 9342 | // R[d] = result; |
| 9343 | EmulateInstruction::Context context; |
| 9344 | context.type = eContextAddition; |
| 9345 | Register reg_n; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9346 | reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 +n); |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9347 | Register reg_m; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9348 | reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 9349 | |
| 9350 | context.SetRegisterRegisterOperands (reg_n, reg_m); |
| 9351 | |
| 9352 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, res.result)) |
| 9353 | return false; |
| 9354 | |
| 9355 | // if setflags then |
| 9356 | // APSR.N = result<31>; |
| 9357 | // APSR.Z = IsZeroBit(result); |
| 9358 | // APSR.C = carry; |
| 9359 | // APSR.V = overflow; |
| 9360 | if (setflags) |
| 9361 | return WriteFlags (context, res.result, res.carry_out, res.overflow); |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9362 | } |
| 9363 | return true; |
| 9364 | } |
| 9365 | |
| 9366 | // A8.6.213 SUB (register) |
| 9367 | bool |
| 9368 | EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding) |
| 9369 | { |
| 9370 | #if 0 |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9371 | if ConditionPassed() then |
| 9372 | EncodingSpecificOperations(); |
| 9373 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9374 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), ‘1’); |
| 9375 | if d == 15 then // Can only occur for ARM encoding |
| 9376 | ALUWritePC(result); // setflags is always FALSE here |
| 9377 | else |
| 9378 | R[d] = result; |
| 9379 | if setflags then |
| 9380 | APSR.N = result<31>; |
| 9381 | APSR.Z = IsZeroBit(result); |
| 9382 | APSR.C = carry; |
| 9383 | APSR.V = overflow; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9384 | #endif |
| 9385 | |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9386 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9387 | |
| 9388 | if (ConditionPassed(opcode)) |
| 9389 | { |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9390 | uint32_t d; |
| 9391 | uint32_t n; |
| 9392 | uint32_t m; |
| 9393 | bool setflags; |
| 9394 | ARM_ShifterType shift_t; |
| 9395 | uint32_t shift_n; |
| 9396 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9397 | switch (encoding) |
| 9398 | { |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9399 | case eEncodingT1: |
| 9400 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock(); |
| 9401 | d = Bits32 (opcode, 2, 0); |
| 9402 | n = Bits32 (opcode, 5, 3); |
| 9403 | m = Bits32 (opcode, 8, 6); |
| 9404 | setflags = !InITBlock(); |
| 9405 | |
| 9406 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 9407 | shift_t = SRType_LSL; |
| 9408 | shift_n = 0; |
| 9409 | |
| 9410 | break; |
| 9411 | |
| 9412 | case eEncodingT2: |
| 9413 | // if Rd == ‘1111’ && S == ‘1’ then SEE CMP (register); |
| 9414 | // if Rn == ‘1101’ then SEE SUB (SP minus register); |
| 9415 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ‘1’); |
| 9416 | d = Bits32 (opcode, 11, 8); |
| 9417 | n = Bits32 (opcode, 19, 16); |
| 9418 | m = Bits32 (opcode, 3, 0); |
| 9419 | setflags = BitIsSet (opcode, 20); |
| 9420 | |
| 9421 | // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); |
| 9422 | shift_n = DecodeImmShiftThumb (opcode, shift_t); |
| 9423 | |
| 9424 | // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE; |
| 9425 | if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m)) |
| 9426 | return false; |
| 9427 | |
| 9428 | break; |
| 9429 | |
| 9430 | case eEncodingA1: |
| 9431 | // if Rd == ‘1111’ && S == ‘1’ then SEE SUBS PC, LR and related instructions; |
| 9432 | // if Rn == ‘1101’ then SEE SUB (SP minus register); |
| 9433 | // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ‘1’); |
| 9434 | d = Bits32 (opcode, 15, 12); |
| 9435 | n = Bits32 (opcode, 19, 16); |
| 9436 | m = Bits32 (opcode, 3, 0); |
| 9437 | setflags = BitIsSet (opcode, 20); |
| 9438 | |
| 9439 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 9440 | shift_n = DecodeImmShiftARM (opcode, shift_t); |
| 9441 | |
| 9442 | break; |
| 9443 | |
| 9444 | default: |
| 9445 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9446 | } |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9447 | |
| 9448 | // shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 9449 | uint32_t Rm = ReadCoreReg (m, &success); |
| 9450 | if (!success) |
| 9451 | return false; |
| 9452 | |
| 9453 | uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); |
| 9454 | |
| 9455 | // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), ‘1’); |
| 9456 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9457 | if (!success) |
| 9458 | return false; |
| 9459 | |
| 9460 | AddWithCarryResult res = AddWithCarry (Rn, ~shifted, 1); |
| 9461 | |
| 9462 | // if d == 15 then // Can only occur for ARM encoding |
| 9463 | // ALUWritePC(result); // setflags is always FALSE here |
| 9464 | // else |
| 9465 | // R[d] = result; |
| 9466 | // if setflags then |
| 9467 | // APSR.N = result<31>; |
| 9468 | // APSR.Z = IsZeroBit(result); |
| 9469 | // APSR.C = carry; |
| 9470 | // APSR.V = overflow; |
| 9471 | |
| 9472 | EmulateInstruction::Context context; |
| 9473 | context.type = eContextSubtraction; |
| 9474 | Register reg_n; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9475 | reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9476 | Register reg_m; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9477 | reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9478 | context.SetRegisterRegisterOperands (reg_n, reg_m); |
| 9479 | |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9480 | if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow)) |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9481 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9482 | } |
| 9483 | return true; |
| 9484 | } |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 9485 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9486 | // A8.6.202 STREX |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 9487 | // Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a |
| 9488 | // word from a register to memory if the executing processor has exclusive access to the memory addressed. |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9489 | bool |
| 9490 | EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding) |
| 9491 | { |
| 9492 | #if 0 |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 9493 | if ConditionPassed() then |
| 9494 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 9495 | address = R[n] + imm32; |
| 9496 | if ExclusiveMonitorsPass(address,4) then |
| 9497 | MemA[address,4] = R[t]; |
| 9498 | R[d] = 0; |
| 9499 | else |
| 9500 | R[d] = 1; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9501 | #endif |
| 9502 | |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 9503 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9504 | |
| 9505 | if (ConditionPassed(opcode)) |
| 9506 | { |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 9507 | uint32_t d; |
| 9508 | uint32_t t; |
| 9509 | uint32_t n; |
| 9510 | uint32_t imm32; |
| 9511 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 9512 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9513 | switch (encoding) |
| 9514 | { |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 9515 | case eEncodingT1: |
| 9516 | // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:’00’, 32); |
| 9517 | d = Bits32 (opcode, 11, 8); |
| 9518 | t = Bits32 (opcode, 15, 12); |
| 9519 | n = Bits32 (opcode, 19, 16); |
| 9520 | imm32 = Bits32 (opcode, 7, 0) << 2; |
| 9521 | |
| 9522 | // if BadReg(d) || BadReg(t) || n == 15 then UNPREDICTABLE; |
| 9523 | if (BadReg (d) || BadReg (t) || (n == 15)) |
| 9524 | return false; |
| 9525 | |
| 9526 | // if d == n || d == t then UNPREDICTABLE; |
| 9527 | if ((d == n) || (d == t)) |
| 9528 | return false; |
| 9529 | |
| 9530 | break; |
| 9531 | |
| 9532 | case eEncodingA1: |
| 9533 | // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset |
| 9534 | d = Bits32 (opcode, 15, 12); |
| 9535 | t = Bits32 (opcode, 3, 0); |
| 9536 | n = Bits32 (opcode, 19, 16); |
| 9537 | imm32 = 0; |
| 9538 | |
| 9539 | // if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; |
| 9540 | if ((d == 15) || (t == 15) || (n == 15)) |
| 9541 | return false; |
| 9542 | |
| 9543 | // if d == n || d == t then UNPREDICTABLE; |
| 9544 | if ((d == n) || (d == t)) |
| 9545 | return false; |
| 9546 | |
| 9547 | break; |
| 9548 | |
| 9549 | default: |
| 9550 | return false; |
| 9551 | } |
| 9552 | |
| 9553 | // address = R[n] + imm32; |
| 9554 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9555 | if (!success) |
| 9556 | return false; |
| 9557 | |
| 9558 | addr_t address = Rn + imm32; |
| 9559 | |
| 9560 | Register base_reg; |
| 9561 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 9562 | Register data_reg; |
| 9563 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 9564 | EmulateInstruction::Context context; |
| 9565 | context.type = eContextRegisterStore; |
| 9566 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, imm32); |
| 9567 | |
| 9568 | // if ExclusiveMonitorsPass(address,4) then |
| 9569 | // if (ExclusiveMonitorsPass (address, addr_byte_size)) -- For now, for the sake of emulation, we will say this |
| 9570 | // always return true. |
| 9571 | if (true) |
| 9572 | { |
| 9573 | // MemA[address,4] = R[t]; |
| 9574 | uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 9575 | if (!success) |
| 9576 | return false; |
| 9577 | |
| 9578 | if (!MemAWrite (context, address, Rt, addr_byte_size)) |
| 9579 | return false; |
| 9580 | |
| 9581 | // R[d] = 0; |
| 9582 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 0)) |
| 9583 | return false; |
| 9584 | } |
| 9585 | else |
| 9586 | { |
| 9587 | // R[d] = 1; |
| 9588 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 1)) |
| 9589 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9590 | } |
| 9591 | } |
| 9592 | return true; |
| 9593 | } |
| 9594 | |
| 9595 | // A8.6.197 STRB (immediate, ARM) |
| 9596 | bool |
| 9597 | EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding) |
| 9598 | { |
| 9599 | #if 0 |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9600 | if ConditionPassed() then |
| 9601 | EncodingSpecificOperations(); |
| 9602 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9603 | address = if index then offset_addr else R[n]; |
| 9604 | MemU[address,1] = R[t]<7:0>; |
| 9605 | if wback then R[n] = offset_addr; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9606 | #endif |
| 9607 | |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9608 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9609 | |
| 9610 | if (ConditionPassed(opcode)) |
| 9611 | { |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9612 | uint32_t t; |
| 9613 | uint32_t n; |
| 9614 | uint32_t imm32; |
| 9615 | bool index; |
| 9616 | bool add; |
| 9617 | bool wback; |
| 9618 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9619 | switch (encoding) |
| 9620 | { |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9621 | case eEncodingA1: |
| 9622 | // if P == ‘0’ && W == ‘1’ then SEE STRBT; |
| 9623 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 9624 | t = Bits32 (opcode, 15, 12); |
| 9625 | n = Bits32 (opcode, 19, 16); |
| 9626 | imm32 = Bits32 (opcode, 11, 0); |
| 9627 | |
| 9628 | // index = (P == ‘1’); add = (U == ‘1’); wback = (P == ‘0’) || (W == ‘1’); |
| 9629 | index = BitIsSet (opcode, 24); |
| 9630 | add = BitIsSet (opcode, 23); |
| 9631 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 9632 | |
| 9633 | // if t == 15 then UNPREDICTABLE; |
| 9634 | if (t == 15) |
| 9635 | return false; |
| 9636 | |
| 9637 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 9638 | if (wback && ((n == 15) || (n == t))) |
| 9639 | return false; |
| 9640 | |
| 9641 | break; |
| 9642 | |
| 9643 | default: |
| 9644 | return false; |
| 9645 | } |
| 9646 | |
| 9647 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9648 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9649 | if (!success) |
| 9650 | return false; |
| 9651 | |
| 9652 | addr_t offset_addr; |
| 9653 | if (add) |
| 9654 | offset_addr = Rn + imm32; |
| 9655 | else |
| 9656 | offset_addr = Rn - imm32; |
| 9657 | |
| 9658 | // address = if index then offset_addr else R[n]; |
| 9659 | addr_t address; |
| 9660 | if (index) |
| 9661 | address = offset_addr; |
| 9662 | else |
| 9663 | address = Rn; |
| 9664 | |
| 9665 | // MemU[address,1] = R[t]<7:0>; |
| 9666 | uint32_t Rt = ReadCoreReg (t, &success); |
| 9667 | if (!success) |
| 9668 | return false; |
| 9669 | |
| 9670 | Register base_reg; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9671 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9672 | Register data_reg; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9673 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 9674 | EmulateInstruction::Context context; |
| 9675 | context.type = eContextRegisterStore; |
| 9676 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); |
| 9677 | |
| 9678 | if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1)) |
| 9679 | return false; |
| 9680 | |
| 9681 | // if wback then R[n] = offset_addr; |
| 9682 | if (wback) |
| 9683 | { |
| 9684 | if (WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 9685 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9686 | } |
| 9687 | } |
| 9688 | return true; |
| 9689 | } |
| 9690 | |
| 9691 | // A8.6.194 STR (immediate, ARM) |
| 9692 | bool |
| 9693 | EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding) |
| 9694 | { |
| 9695 | #if 0 |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9696 | if ConditionPassed() then |
| 9697 | EncodingSpecificOperations(); |
| 9698 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9699 | address = if index then offset_addr else R[n]; |
| 9700 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 9701 | if wback then R[n] = offset_addr; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9702 | #endif |
| 9703 | |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9704 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9705 | |
| 9706 | if (ConditionPassed(opcode)) |
| 9707 | { |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9708 | uint32_t t; |
| 9709 | uint32_t n; |
| 9710 | uint32_t imm32; |
| 9711 | bool index; |
| 9712 | bool add; |
| 9713 | bool wback; |
| 9714 | |
| 9715 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 9716 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9717 | switch (encoding) |
| 9718 | { |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9719 | case eEncodingA1: |
| 9720 | // if P == ‘0’ && W == ‘1’ then SEE STRT; |
| 9721 | // if Rn == ‘1101’ && P == ‘1’ && U == ‘0’ && W == ‘1’ && imm12 == ‘000000000100’ then SEE PUSH; |
| 9722 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 9723 | t = Bits32 (opcode, 15, 12); |
| 9724 | n = Bits32 (opcode, 19, 16); |
| 9725 | imm32 = Bits32 (opcode, 11, 0); |
| 9726 | |
| 9727 | // index = (P == ‘1’); add = (U == ‘1’); wback = (P == ‘0’) || (W == ‘1’); |
| 9728 | index = BitIsSet (opcode, 24); |
| 9729 | add = BitIsSet (opcode, 23); |
| 9730 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 9731 | |
| 9732 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 9733 | if (wback && ((n == 15) || (n == t))) |
| 9734 | return false; |
| 9735 | |
| 9736 | break; |
| 9737 | |
| 9738 | default: |
| 9739 | return false; |
| 9740 | } |
| 9741 | |
| 9742 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9743 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9744 | if (!success) |
| 9745 | return false; |
| 9746 | |
| 9747 | addr_t offset_addr; |
| 9748 | if (add) |
| 9749 | offset_addr = Rn + imm32; |
| 9750 | else |
| 9751 | offset_addr = Rn - imm32; |
| 9752 | |
| 9753 | // address = if index then offset_addr else R[n]; |
| 9754 | addr_t address; |
| 9755 | if (index) |
| 9756 | address = offset_addr; |
| 9757 | else |
| 9758 | address = Rn; |
| 9759 | |
| 9760 | Register base_reg; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9761 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9762 | Register data_reg; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9763 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9764 | EmulateInstruction::Context context; |
| 9765 | context.type = eContextRegisterStore; |
| 9766 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); |
| 9767 | |
| 9768 | // MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 9769 | uint32_t Rt = ReadCoreReg (t, &success); |
| 9770 | if (!success) |
| 9771 | return false; |
| 9772 | |
| 9773 | if (t == 15) |
| 9774 | { |
Caroline Tice | e98b958 | 2011-03-30 16:05:23 +0000 | [diff] [blame] | 9775 | uint32_t pc_value = ReadCoreReg (PC_REG, &success); |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 9776 | if (!success) |
| 9777 | return false; |
| 9778 | |
| 9779 | if (!MemUWrite (context, address, pc_value, addr_byte_size)) |
| 9780 | return false; |
| 9781 | } |
| 9782 | else |
| 9783 | { |
| 9784 | if (!MemUWrite (context, address, Rt, addr_byte_size)) |
| 9785 | return false; |
| 9786 | } |
| 9787 | |
| 9788 | // if wback then R[n] = offset_addr; |
| 9789 | if (wback) |
| 9790 | { |
| 9791 | context.type = eContextAdjustBaseRegister; |
| 9792 | context.SetImmediate (offset_addr); |
| 9793 | |
| 9794 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 9795 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9796 | } |
| 9797 | } |
| 9798 | return true; |
| 9799 | } |
| 9800 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9801 | // A8.6.66 LDRD (immediate) |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9802 | // Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two |
| 9803 | // words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9804 | bool |
| 9805 | EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding) |
| 9806 | { |
| 9807 | #if 0 |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9808 | if ConditionPassed() then |
| 9809 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 9810 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9811 | address = if index then offset_addr else R[n]; |
| 9812 | R[t] = MemA[address,4]; |
| 9813 | R[t2] = MemA[address+4,4]; |
| 9814 | if wback then R[n] = offset_addr; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9815 | #endif |
| 9816 | |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9817 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9818 | |
| 9819 | if (ConditionPassed(opcode)) |
| 9820 | { |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9821 | uint32_t t; |
| 9822 | uint32_t t2; |
| 9823 | uint32_t n; |
| 9824 | uint32_t imm32; |
| 9825 | bool index; |
| 9826 | bool add; |
| 9827 | bool wback; |
| 9828 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9829 | switch (encoding) |
| 9830 | { |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9831 | case eEncodingT1: |
| 9832 | //if P == ‘0’ && W == ‘0’ then SEE “Related encodings”; |
| 9833 | //if Rn == ‘1111’ then SEE LDRD (literal); |
| 9834 | //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:’00’, 32); |
| 9835 | t = Bits32 (opcode, 15, 12); |
| 9836 | t2 = Bits32 (opcode, 11, 8); |
| 9837 | n = Bits32 (opcode, 19, 16); |
| 9838 | imm32 = Bits32 (opcode, 7, 0) << 2; |
| 9839 | |
| 9840 | //index = (P == ‘1’); add = (U == ‘1’); wback = (W == ‘1’); |
| 9841 | index = BitIsSet (opcode, 24); |
| 9842 | add = BitIsSet (opcode, 23); |
| 9843 | wback = BitIsSet (opcode, 21); |
| 9844 | |
| 9845 | //if wback && (n == t || n == t2) then UNPREDICTABLE; |
| 9846 | if (wback && ((n == t) || (n == t2))) |
| 9847 | return false; |
| 9848 | |
| 9849 | //if BadReg(t) || BadReg(t2) || t == t2 then UNPREDICTABLE; |
| 9850 | if (BadReg (t) || BadReg (t2) || (t == t2)) |
| 9851 | return false; |
| 9852 | |
| 9853 | break; |
| 9854 | |
| 9855 | case eEncodingA1: |
| 9856 | //if Rn == ‘1111’ then SEE LDRD (literal); |
| 9857 | //if Rt<0> == ‘1’ then UNPREDICTABLE; |
| 9858 | //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); |
| 9859 | t = Bits32 (opcode, 15, 12); |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9860 | if (BitIsSet (t, 0)) |
| 9861 | return false; |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 9862 | t2 = t + 1; |
| 9863 | n = Bits32 (opcode, 19, 16); |
| 9864 | imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0); |
| 9865 | |
| 9866 | //index = (P == ‘1’); add = (U == ‘1’); wback = (P == ‘0’) || (W == ‘1’); |
| 9867 | index = BitIsSet (opcode, 24); |
| 9868 | add = BitIsSet (opcode, 23); |
| 9869 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 9870 | |
| 9871 | //if P == ‘0’ && W == ‘1’ then UNPREDICTABLE; |
| 9872 | if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) |
| 9873 | return false; |
| 9874 | |
| 9875 | //if wback && (n == t || n == t2) then UNPREDICTABLE; |
| 9876 | if (wback && ((n == t) || (n == t2))) |
| 9877 | return false; |
| 9878 | |
| 9879 | //if t2 == 15 then UNPREDICTABLE; |
| 9880 | if (t2 == 15) |
| 9881 | return false; |
| 9882 | |
| 9883 | break; |
| 9884 | |
| 9885 | default: |
| 9886 | return false; |
| 9887 | } |
| 9888 | |
| 9889 | //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 9890 | uint32_t Rn = ReadCoreReg (n, &success); |
| 9891 | if (!success) |
| 9892 | return false; |
| 9893 | |
| 9894 | addr_t offset_addr; |
| 9895 | if (add) |
| 9896 | offset_addr = Rn + imm32; |
| 9897 | else |
| 9898 | offset_addr = Rn - imm32; |
| 9899 | |
| 9900 | //address = if index then offset_addr else R[n]; |
| 9901 | addr_t address; |
| 9902 | if (index) |
| 9903 | address = offset_addr; |
| 9904 | else |
| 9905 | address = Rn; |
| 9906 | |
| 9907 | //R[t] = MemA[address,4]; |
| 9908 | Register base_reg; |
| 9909 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 9910 | |
| 9911 | EmulateInstruction::Context context; |
| 9912 | context.type = eContextRegisterLoad; |
| 9913 | context.SetRegisterPlusOffset (base_reg, address - Rn); |
| 9914 | |
| 9915 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 9916 | uint32_t data = MemARead (context, address, addr_byte_size, 0, &success); |
| 9917 | if (!success) |
| 9918 | return false; |
| 9919 | |
| 9920 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 9921 | return false; |
| 9922 | |
| 9923 | //R[t2] = MemA[address+4,4]; |
| 9924 | |
| 9925 | context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn); |
| 9926 | data = MemARead (context, address + 4, addr_byte_size, 0, &success); |
| 9927 | if (!success) |
| 9928 | return false; |
| 9929 | |
| 9930 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data)) |
| 9931 | return false; |
| 9932 | |
| 9933 | //if wback then R[n] = offset_addr; |
| 9934 | if (wback) |
| 9935 | { |
| 9936 | context.type = eContextAdjustBaseRegister; |
| 9937 | context.SetAddress (offset_addr); |
| 9938 | |
| 9939 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 9940 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9941 | } |
| 9942 | } |
| 9943 | return true; |
| 9944 | } |
| 9945 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9946 | // A8.6.68 LDRD (register) |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9947 | // Load Register Dual (register) calculates an address from a base register value and a register offset, loads two |
| 9948 | // words from memory, and writes them to two registers. It can use offset, post-indexed or pre-indexed addressing. |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9949 | bool |
| 9950 | EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding) |
| 9951 | { |
| 9952 | #if 0 |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9953 | if ConditionPassed() then |
| 9954 | EncodingSpecificOperations(); |
| 9955 | offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]); |
| 9956 | address = if index then offset_addr else R[n]; |
| 9957 | R[t] = MemA[address,4]; |
| 9958 | R[t2] = MemA[address+4,4]; |
| 9959 | if wback then R[n] = offset_addr; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9960 | #endif |
| 9961 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9962 | bool success = false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9963 | |
| 9964 | if (ConditionPassed(opcode)) |
| 9965 | { |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9966 | uint32_t t; |
| 9967 | uint32_t t2; |
| 9968 | uint32_t n; |
| 9969 | uint32_t m; |
| 9970 | bool index; |
| 9971 | bool add; |
| 9972 | bool wback; |
| 9973 | |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 9974 | switch (encoding) |
| 9975 | { |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 9976 | case eEncodingA1: |
| 9977 | // if Rt<0> == ‘1’ then UNPREDICTABLE; |
| 9978 | // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm); |
| 9979 | t = Bits32 (opcode, 15, 12); |
| 9980 | if (BitIsSet (t, 0)) |
| 9981 | return false; |
| 9982 | t2 = t + 1; |
| 9983 | n = Bits32 (opcode, 19, 16); |
| 9984 | m = Bits32 (opcode, 3, 0); |
| 9985 | |
| 9986 | // index = (P == ‘1’); add = (U == ‘1’); wback = (P == ‘0’) || (W == ‘1’); |
| 9987 | index = BitIsSet (opcode, 24); |
| 9988 | add = BitIsSet (opcode, 23); |
| 9989 | wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); |
| 9990 | |
| 9991 | // if P == ‘0’ && W == ‘1’ then UNPREDICTABLE; |
| 9992 | if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) |
| 9993 | return false; |
| 9994 | |
| 9995 | // if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE; |
| 9996 | if ((t2 == 15) || (m == 15) || (m == t) || (m == t2)) |
| 9997 | return false; |
| 9998 | |
| 9999 | // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE; |
| 10000 | if (wback && ((n == 15) || (n == t) || (n == t2))) |
| 10001 | return false; |
| 10002 | |
| 10003 | // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE; |
| 10004 | if ((ArchVersion() < 6) && wback && (m == n)) |
| 10005 | return false; |
| 10006 | break; |
| 10007 | |
| 10008 | default: |
| 10009 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10010 | } |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10011 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10012 | uint32_t Rn = ReadCoreReg (n, &success); |
| 10013 | if (!success) |
| 10014 | return false; |
| 10015 | Register base_reg; |
| 10016 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10017 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10018 | uint32_t Rm = ReadCoreReg (m, &success); |
| 10019 | if (!success) |
| 10020 | return false; |
| 10021 | Register offset_reg; |
| 10022 | offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10023 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10024 | // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]); |
| 10025 | addr_t offset_addr; |
| 10026 | if (add) |
| 10027 | offset_addr = Rn + Rm; |
| 10028 | else |
| 10029 | offset_addr = Rn - Rm; |
| 10030 | |
| 10031 | // address = if index then offset_addr else R[n]; |
| 10032 | addr_t address; |
| 10033 | if (index) |
| 10034 | address = offset_addr; |
| 10035 | else |
| 10036 | address = Rn; |
| 10037 | |
| 10038 | EmulateInstruction::Context context; |
| 10039 | context.type = eContextRegisterLoad; |
| 10040 | context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); |
| 10041 | |
| 10042 | // R[t] = MemA[address,4]; |
| 10043 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 10044 | uint32_t data = MemARead (context, address, addr_byte_size, 0, &success); |
| 10045 | if (!success) |
| 10046 | return false; |
| 10047 | |
| 10048 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) |
| 10049 | return false; |
| 10050 | |
| 10051 | // R[t2] = MemA[address+4,4]; |
| 10052 | |
| 10053 | data = MemARead (context, address + 4, addr_byte_size, 0, &success); |
| 10054 | if (!success) |
| 10055 | return false; |
| 10056 | |
| 10057 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data)) |
| 10058 | return false; |
| 10059 | |
| 10060 | // if wback then R[n] = offset_addr; |
| 10061 | if (wback) |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10062 | { |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10063 | context.type = eContextAdjustBaseRegister; |
| 10064 | context.SetAddress (offset_addr); |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10065 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10066 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 10067 | return false; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10068 | } |
| 10069 | } |
| 10070 | return true; |
| 10071 | } |
| 10072 | |
| 10073 | |
| 10074 | // A8.6.200 STRD (immediate) |
| 10075 | bool |
| 10076 | EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding) |
| 10077 | { |
| 10078 | #if 0 |
| 10079 | #endif |
| 10080 | |
| 10081 | //bool success = false; |
| 10082 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10083 | // if (ConditionPassed(opcode)) |
| 10084 | // { |
| 10085 | // switch (encoding) |
| 10086 | // { |
| 10087 | // } |
| 10088 | // } |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10089 | return true; |
| 10090 | } |
| 10091 | |
| 10092 | |
| 10093 | // A8.6.201 STRD (register) |
| 10094 | bool |
| 10095 | EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding) |
| 10096 | { |
| 10097 | #if 0 |
| 10098 | #endif |
| 10099 | |
| 10100 | //bool success = false; |
| 10101 | |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10102 | // if (ConditionPassed(opcode)) |
| 10103 | // { |
| 10104 | // switch (encoding) |
| 10105 | // { |
| 10106 | // } |
| 10107 | // } |
Greg Clayton | 24bc5d9 | 2011-03-30 18:16:51 +0000 | [diff] [blame] | 10108 | return true; |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10109 | } |
| 10110 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10111 | EmulateInstructionARM::ARMOpcode* |
| 10112 | EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10113 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10114 | static ARMOpcode |
| 10115 | g_arm_opcodes[] = |
| 10116 | { |
| 10117 | //---------------------------------------------------------------------- |
| 10118 | // Prologue instructions |
| 10119 | //---------------------------------------------------------------------- |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 10120 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10121 | // push register(s) |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10122 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <registers>" }, |
| 10123 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <register>" }, |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 10124 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10125 | // set r7 to point to a stack offset |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10126 | { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #<const>" }, |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10127 | { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBR7IPImm, "sub r7, ip, #<const>"}, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 10128 | // copy the stack pointer to ip |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10129 | { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMOVRdSP, "mov ip, sp" }, |
| 10130 | { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add ip, sp, #<const>" }, |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10131 | { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBIPSPImm, "sub ip, sp, #<const>"}, |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 10132 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10133 | // adjust the stack pointer |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10134 | { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #<const>"}, |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10135 | { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" }, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 10136 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10137 | // push one register |
| 10138 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
Caroline Tice | 3e40797 | 2011-03-18 19:41:00 +0000 | [diff] [blame] | 10139 | { 0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" }, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 10140 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10141 | // vector push consecutive extension register(s) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 10142 | { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 10143 | { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 10144 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10145 | //---------------------------------------------------------------------- |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 10146 | // Epilogue instructions |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10147 | //---------------------------------------------------------------------- |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 10148 | |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10149 | { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <registers>"}, |
| 10150 | { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <register>"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 10151 | { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 10152 | { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 10153 | |
| 10154 | //---------------------------------------------------------------------- |
| 10155 | // Supervisor Call (previously Software Interrupt) |
| 10156 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 10157 | { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, |
| 10158 | |
| 10159 | //---------------------------------------------------------------------- |
| 10160 | // Branch instructions |
| 10161 | //---------------------------------------------------------------------- |
Johnny Chen | 696b4ef | 2011-02-24 21:54:22 +0000 | [diff] [blame] | 10162 | { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateB, "b #imm24"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 10163 | // To resolve ambiguity, "blx <label>" should come before "bl <label>". |
| 10164 | { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 10165 | { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 10166 | { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 10167 | // for example, "bx lr" |
| 10168 | { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 10169 | // bxj |
| 10170 | { 0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 10171 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 10172 | //---------------------------------------------------------------------- |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 10173 | // Data-processing instructions |
| 10174 | //---------------------------------------------------------------------- |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10175 | // adc (immediate) |
| 10176 | { 0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"}, |
| 10177 | // adc (register) |
| 10178 | { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 10179 | // add (immediate) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10180 | { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s}<c> <Rd>, <Rn>, #const"}, |
Johnny Chen | 8fa2059 | 2011-02-18 01:22:22 +0000 | [diff] [blame] | 10181 | // add (register) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10182 | { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Caroline Tice | c08ed38 | 2011-03-29 23:03:16 +0000 | [diff] [blame] | 10183 | // add (register-shifted register) |
| 10184 | { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>m, <Rm>, <type> <RS>"}, |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 10185 | // adr |
| 10186 | { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"}, |
| 10187 | { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"}, |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 10188 | // and (immediate) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10189 | { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"}, |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 10190 | // and (register) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10191 | { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 10192 | // bic (immediate) |
| 10193 | { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"}, |
| 10194 | // bic (register) |
| 10195 | { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 10196 | // eor (immediate) |
| 10197 | { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"}, |
| 10198 | // eor (register) |
| 10199 | { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 10200 | // orr (immediate) |
| 10201 | { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"}, |
| 10202 | // orr (register) |
| 10203 | { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 10204 | // rsb (immediate) |
| 10205 | { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10206 | // rsb (register) |
| 10207 | { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 90e607b | 2011-02-23 00:07:09 +0000 | [diff] [blame] | 10208 | // rsc (immediate) |
| 10209 | { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10210 | // rsc (register) |
| 10211 | { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 10212 | // sbc (immediate) |
| 10213 | { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10214 | // sbc (register) |
| 10215 | { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 10216 | // sub (immediate, ARM) |
| 10217 | { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s}<c> <Rd>, <Rn>, #<const>"}, |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 10218 | // sub (sp minus immediate) |
| 10219 | { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"}, |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 10220 | // sub (register) |
| 10221 | { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"}, |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 10222 | // teq (immediate) |
| 10223 | { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"}, |
| 10224 | // teq (register) |
| 10225 | { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 10226 | // tst (immediate) |
| 10227 | { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"}, |
| 10228 | // tst (register) |
| 10229 | { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"}, |
| 10230 | |
Caroline Tice | 89c6d58 | 2011-03-29 19:53:44 +0000 | [diff] [blame] | 10231 | // mov (immediate) |
| 10232 | { 0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"}, |
| 10233 | { 0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>" }, |
Johnny Chen | 01d6157 | 2011-02-25 00:23:25 +0000 | [diff] [blame] | 10234 | // mov (register) |
| 10235 | { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"}, |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 10236 | // mvn (immediate) |
| 10237 | { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"}, |
| 10238 | // mvn (register) |
| 10239 | { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c> <Rd>, <Rm> {,<shift>}"}, |
Johnny Chen | 3847dad | 2011-02-22 02:00:12 +0000 | [diff] [blame] | 10240 | // cmn (immediate) |
| 10241 | { 0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"}, |
| 10242 | // cmn (register) |
| 10243 | { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 10244 | // cmp (immediate) |
| 10245 | { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #<const>"}, |
| 10246 | // cmp (register) |
| 10247 | { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 10248 | // asr (immediate) |
| 10249 | { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 10250 | // asr (register) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 10251 | { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 10252 | // lsl (immediate) |
| 10253 | { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"}, |
| 10254 | // lsl (register) |
| 10255 | { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"}, |
| 10256 | // lsr (immediate) |
| 10257 | { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"}, |
| 10258 | // lsr (register) |
| 10259 | { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 10260 | // rrx is a special case encoding of ror (immediate) |
| 10261 | { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"}, |
| 10262 | // ror (immediate) |
| 10263 | { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"}, |
| 10264 | // ror (register) |
| 10265 | { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"}, |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 10266 | // mul |
| 10267 | { 0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>" }, |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 10268 | |
| 10269 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 10270 | // Load instructions |
| 10271 | //---------------------------------------------------------------------- |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 10272 | { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 10273 | { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 10274 | { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10275 | { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" }, |
Caroline Tice | 4d729c5 | 2011-02-18 00:55:53 +0000 | [diff] [blame] | 10276 | { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" }, |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 10277 | { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" }, |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 10278 | { 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"}, |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 10279 | { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" }, |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 10280 | { 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" }, |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 10281 | { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" }, |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 10282 | { 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" }, |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 10283 | { 0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>" }, |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 10284 | { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" }, |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 10285 | { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"}, |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 10286 | { 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" }, |
| 10287 | { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" }, |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 10288 | { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"}, |
Caroline Tice | eab301f | 2011-03-30 17:54:52 +0000 | [diff] [blame] | 10289 | { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"}, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10290 | |
| 10291 | //---------------------------------------------------------------------- |
| 10292 | // Store instructions |
| 10293 | //---------------------------------------------------------------------- |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 10294 | { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 10295 | { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 10296 | { 0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 10297 | { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>" }, |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10298 | { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}" }, |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 10299 | { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" }, |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 10300 | { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"}, |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 10301 | { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"}, |
Caroline Tice | d42b3cc | 2011-03-30 06:03:24 +0000 | [diff] [blame] | 10302 | { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"}, |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 10303 | |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10304 | //---------------------------------------------------------------------- |
| 10305 | // Other instructions |
| 10306 | //---------------------------------------------------------------------- |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 10307 | { 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" }, |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 10308 | { 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" }, |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 10309 | { 0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}" }, |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10310 | { 0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}" }, |
| 10311 | { 0xfe500000, 0xf8100000, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{<amode>} <Rn>{!}" } |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10312 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10313 | }; |
| 10314 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
| 10315 | |
| 10316 | for (size_t i=0; i<k_num_arm_opcodes; ++i) |
| 10317 | { |
| 10318 | if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) |
| 10319 | return &g_arm_opcodes[i]; |
| 10320 | } |
| 10321 | return NULL; |
| 10322 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10323 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10324 | |
| 10325 | EmulateInstructionARM::ARMOpcode* |
| 10326 | EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 10327 | { |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 10328 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10329 | static ARMOpcode |
| 10330 | g_thumb_opcodes[] = |
| 10331 | { |
| 10332 | //---------------------------------------------------------------------- |
| 10333 | // Prologue instructions |
| 10334 | //---------------------------------------------------------------------- |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 10335 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10336 | // push register(s) |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10337 | { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePUSH, "push <registers>" }, |
| 10338 | { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <registers>" }, |
| 10339 | { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <register>" }, |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 10340 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10341 | // set r7 to point to a stack offset |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10342 | { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #imm" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 10343 | // copy the stack pointer to r7 |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10344 | { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdSP, "mov r7, sp" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 10345 | // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity) |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10346 | { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVLowHigh, "mov r0-r7, r8-r15" }, |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 10347 | |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10348 | // PC-relative load into register (see also EmulateADDSPRm) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 10349 | { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"}, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 10350 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10351 | // adjust the stack pointer |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10352 | { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"}, |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 10353 | { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"}, |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10354 | { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #<const>"}, |
| 10355 | { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"}, |
Caroline Tice | d05b490 | 2011-03-29 21:24:06 +0000 | [diff] [blame] | 10356 | { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" }, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 10357 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10358 | // vector push consecutive extension register(s) |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 10359 | { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 10360 | { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 10361 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10362 | //---------------------------------------------------------------------- |
| 10363 | // Epilogue instructions |
| 10364 | //---------------------------------------------------------------------- |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 10365 | |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 10366 | { 0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"}, |
Johnny Chen | 864a8e8 | 2011-02-18 00:07:39 +0000 | [diff] [blame] | 10367 | { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add sp, #imm"}, |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10368 | { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePOP, "pop <registers>"}, |
| 10369 | { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <registers>" }, |
| 10370 | { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <register>" }, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 10371 | { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
| 10372 | { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 10373 | |
| 10374 | //---------------------------------------------------------------------- |
| 10375 | // Supervisor Call (previously Software Interrupt) |
| 10376 | //---------------------------------------------------------------------- |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 10377 | { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, |
| 10378 | |
| 10379 | //---------------------------------------------------------------------- |
| 10380 | // If Then makes up to four following instructions conditional. |
| 10381 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 10382 | { 0xffffff00, 0x0000bf00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, |
| 10383 | |
| 10384 | //---------------------------------------------------------------------- |
| 10385 | // Branch instructions |
| 10386 | //---------------------------------------------------------------------- |
| 10387 | // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". |
| 10388 | { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 10389 | { 0xfffff800, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm11 (outside or last in IT)"}, |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10390 | { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"}, |
Johnny Chen | 696b4ef | 2011-02-24 21:54:22 +0000 | [diff] [blame] | 10391 | { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside or last in IT)"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 10392 | // J1 == J2 == 1 |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 10393 | { 0xf800d000, 0xf000d000, ARMV4T_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 10394 | // J1 == J2 == 1 |
Caroline Tice | e221288 | 2011-03-22 22:38:28 +0000 | [diff] [blame] | 10395 | { 0xf800d001, 0xf000c000, ARMV5_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 10396 | { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 10397 | // for example, "bx lr" |
| 10398 | { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | 59e6ab7 | 2011-02-24 21:01:20 +0000 | [diff] [blame] | 10399 | // bxj |
| 10400 | { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"}, |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 10401 | // compare and branch |
| 10402 | { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"}, |
Johnny Chen | 60299ec | 2011-02-17 19:34:27 +0000 | [diff] [blame] | 10403 | // table branch byte |
| 10404 | { 0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"}, |
| 10405 | // table branch halfword |
| 10406 | { 0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 10407 | |
| 10408 | //---------------------------------------------------------------------- |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10409 | // Data-processing instructions |
| 10410 | //---------------------------------------------------------------------- |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10411 | // adc (immediate) |
| 10412 | { 0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10413 | // adc (register) |
| 10414 | { 0xffffffc0, 0x00004140, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"}, |
| 10415 | { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
| 10416 | // add (register) |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10417 | { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10418 | // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two. |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10419 | { 0xffffff00, 0x00004400, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"}, |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 10420 | // adr |
| 10421 | { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"}, |
| 10422 | { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"}, |
| 10423 | { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"}, |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 10424 | // and (immediate) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 10425 | { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"}, |
Johnny Chen | e97c0d5 | 2011-02-18 19:32:20 +0000 | [diff] [blame] | 10426 | // and (register) |
| 10427 | { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"}, |
| 10428 | { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | b9f02cf | 2011-02-24 01:15:17 +0000 | [diff] [blame] | 10429 | // bic (immediate) |
| 10430 | { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10431 | // bic (register) |
| 10432 | { 0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"}, |
| 10433 | { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 10434 | // eor (immediate) |
| 10435 | { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10436 | // eor (register) |
| 10437 | { 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"}, |
| 10438 | { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 10439 | // orr (immediate) |
| 10440 | { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10441 | // orr (register) |
| 10442 | { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"}, |
| 10443 | { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | ed32e7c | 2011-02-22 23:42:58 +0000 | [diff] [blame] | 10444 | // rsb (immediate) |
| 10445 | { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"}, |
| 10446 | { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"}, |
| 10447 | // rsb (register) |
| 10448 | { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 9b38177 | 2011-02-23 01:01:21 +0000 | [diff] [blame] | 10449 | // sbc (immediate) |
| 10450 | { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"}, |
| 10451 | // sbc (register) |
| 10452 | { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"}, |
| 10453 | { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"}, |
Caroline Tice | dcc11b3 | 2011-03-02 23:57:02 +0000 | [diff] [blame] | 10454 | // add (immediate, Thumb) |
| 10455 | { 0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rd>,<Rn>,#<imm3>" }, |
| 10456 | { 0xfffff800, 0x00003000, ARMV4T_ABOVE, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rdn>,#<imm8>" }, |
| 10457 | { 0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "add{s}<c>.w <Rd>,<Rn>,#<const>" }, |
| 10458 | { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" }, |
Johnny Chen | 15a7a6b | 2011-02-23 23:47:56 +0000 | [diff] [blame] | 10459 | // sub (immediate, Thumb) |
| 10460 | { 0xfffffe00, 0x00001e00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rd>, <Rn> #imm3"}, |
| 10461 | { 0xfffff800, 0x00003800, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rdn>, #imm8"}, |
| 10462 | { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}<c>.w <Rd>, <Rn>, #<const>"}, |
| 10463 | { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"}, |
Johnny Chen | c9e747f | 2011-02-23 01:55:07 +0000 | [diff] [blame] | 10464 | // sub (sp minus immediate) |
| 10465 | { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"}, |
| 10466 | { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"}, |
Caroline Tice | 4cccd53 | 2011-03-29 23:44:20 +0000 | [diff] [blame] | 10467 | // sub (register) |
| 10468 | { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"}, |
| 10469 | { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"}, |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 10470 | // teq (immediate) |
| 10471 | { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"}, |
| 10472 | // teq (register) |
| 10473 | { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 10474 | // tst (immediate) |
Johnny Chen | 2115b41 | 2011-02-21 23:42:44 +0000 | [diff] [blame] | 10475 | { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"}, |
Johnny Chen | de3cce3 | 2011-02-21 21:24:49 +0000 | [diff] [blame] | 10476 | // tst (register) |
| 10477 | { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"}, |
| 10478 | { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"}, |
| 10479 | |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 10480 | |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 10481 | // move from high register to high register |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10482 | { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"}, |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 10483 | // move from low register to low register |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10484 | { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"}, |
Johnny Chen | 7c5234d | 2011-02-18 23:41:11 +0000 | [diff] [blame] | 10485 | // mov{s}<c>.w <Rd>, <Rm> |
| 10486 | { 0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"}, |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 10487 | // move immediate |
Johnny Chen | 9f68772 | 2011-02-18 00:02:28 +0000 | [diff] [blame] | 10488 | { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"}, |
| 10489 | { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"}, |
Caroline Tice | 89c6d58 | 2011-03-29 19:53:44 +0000 | [diff] [blame] | 10490 | { 0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"}, |
Johnny Chen | d642a6a | 2011-02-22 01:01:03 +0000 | [diff] [blame] | 10491 | // mvn (immediate) |
| 10492 | { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"}, |
| 10493 | // mvn (register) |
| 10494 | { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"}, |
| 10495 | { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"}, |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 10496 | // cmn (immediate) |
Johnny Chen | 688926f | 2011-02-22 19:01:11 +0000 | [diff] [blame] | 10497 | { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"}, |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 10498 | // cmn (register) |
| 10499 | { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"}, |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 10500 | { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"}, |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 10501 | // cmp (immediate) |
| 10502 | { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"}, |
Johnny Chen | 078fbc6 | 2011-02-22 19:48:22 +0000 | [diff] [blame] | 10503 | { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"}, |
Johnny Chen | 34075cb | 2011-02-22 01:56:31 +0000 | [diff] [blame] | 10504 | // cmp (register) (Rn and Rm both from r0-r7) |
| 10505 | { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"}, |
| 10506 | // cmp (register) (Rn and Rm not both from r0-r7) |
| 10507 | { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"}, |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 10508 | // asr (immediate) |
| 10509 | { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"}, |
Johnny Chen | 4d896db | 2011-02-15 20:14:02 +0000 | [diff] [blame] | 10510 | { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"}, |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 10511 | // asr (register) |
| 10512 | { 0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"}, |
| 10513 | { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 10514 | // lsl (immediate) |
| 10515 | { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"}, |
| 10516 | { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 10517 | // lsl (register) |
| 10518 | { 0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"}, |
| 10519 | { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
| 10520 | // lsr (immediate) |
| 10521 | { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"}, |
| 10522 | { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 10523 | // lsr (register) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 10524 | { 0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 10525 | { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 10526 | // rrx is a special case encoding of ror (immediate) |
| 10527 | { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"}, |
| 10528 | // ror (immediate) |
| 10529 | { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 10530 | // ror (register) |
| 10531 | { 0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"}, |
| 10532 | { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Caroline Tice | 5c1e2ed | 2011-03-02 22:43:54 +0000 | [diff] [blame] | 10533 | // mul |
| 10534 | { 0xffffffc0, 0x00004340, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMUL, "muls <Rdm>,<Rn>,<Rdm>" }, |
| 10535 | // mul |
| 10536 | { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" }, |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10537 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10538 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 10539 | // Load instructions |
| 10540 | //---------------------------------------------------------------------- |
| 10541 | { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 10542 | { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" }, |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 10543 | { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | baf1f64 | 2011-03-24 19:23:45 +0000 | [diff] [blame] | 10544 | { 0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"}, |
| 10545 | { 0xfffff800, 0x00009800, ARMV4T_ABOVE, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"}, |
| 10546 | { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"}, |
| 10547 | { 0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"}, |
| 10548 | // Thumb2 PC-relative load into register |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10549 | { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"}, |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 10550 | { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" }, |
| 10551 | { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" }, |
Caroline Tice | 21b604b | 2011-02-18 21:06:04 +0000 | [diff] [blame] | 10552 | { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" }, |
| 10553 | { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" }, |
| 10554 | { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[>Rn>, #+/-<imm8>]{!}" }, |
Caroline Tice | f55261f | 2011-02-18 22:24:22 +0000 | [diff] [blame] | 10555 | { 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]" }, |
Caroline Tice | 30fec12 | 2011-02-18 23:52:21 +0000 | [diff] [blame] | 10556 | { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" }, |
Caroline Tice | ef44000 | 2011-03-30 05:40:56 +0000 | [diff] [blame] | 10557 | { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, eSize32,&EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" }, |
Caroline Tice | 0491b3b | 2011-02-28 22:39:58 +0000 | [diff] [blame] | 10558 | { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" }, |
| 10559 | { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" }, |
| 10560 | { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" }, |
Caroline Tice | 952b538 | 2011-02-28 23:15:24 +0000 | [diff] [blame] | 10561 | { 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" }, |
Caroline Tice | 0e6bc95 | 2011-03-01 18:00:42 +0000 | [diff] [blame] | 10562 | { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" }, |
| 10563 | { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" }, |
Caroline Tice | a5e28af | 2011-03-01 21:53:03 +0000 | [diff] [blame] | 10564 | { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" }, |
| 10565 | { 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" }, |
Caroline Tice | 5f59391 | 2011-03-01 22:25:17 +0000 | [diff] [blame] | 10566 | { 0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>" }, |
Caroline Tice | 672f311 | 2011-03-01 23:55:59 +0000 | [diff] [blame] | 10567 | { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" }, |
| 10568 | { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" }, |
Caroline Tice | 78fb563 | 2011-03-02 00:39:42 +0000 | [diff] [blame] | 10569 | { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" }, |
| 10570 | { 0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]" }, |
Caroline Tice | d2fac09 | 2011-03-02 19:45:34 +0000 | [diff] [blame] | 10571 | { 0xff7f0000, 0xf93f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" }, |
Caroline Tice | 291a3e9 | 2011-03-02 21:13:44 +0000 | [diff] [blame] | 10572 | { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" }, |
| 10573 | { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" }, |
Caroline Tice | 1697dd7 | 2011-03-30 17:11:45 +0000 | [diff] [blame] | 10574 | { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt?, <Rt2>, [<Rn>,#+/-<imm>]!"}, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10575 | |
| 10576 | //---------------------------------------------------------------------- |
| 10577 | // Store instructions |
| 10578 | //---------------------------------------------------------------------- |
| 10579 | { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 10580 | { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" }, |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 10581 | { 0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | fe47911 | 2011-02-18 18:52:37 +0000 | [diff] [blame] | 10582 | { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]" }, |
| 10583 | { 0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]" }, |
| 10584 | { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" }, |
| 10585 | { 0xfff00800, 0xf8400800, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>,#+/-<imm8>]" }, |
| 10586 | { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" }, |
| 10587 | { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" }, |
| 10588 | { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" }, |
| 10589 | { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" }, |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10590 | { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}" }, |
Caroline Tice | 8ce836d | 2011-03-16 22:46:55 +0000 | [diff] [blame] | 10591 | { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" }, |
| 10592 | { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" }, |
Caroline Tice | 5168b6c | 2011-03-30 05:15:46 +0000 | [diff] [blame] | 10593 | { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" }, |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10594 | |
| 10595 | //---------------------------------------------------------------------- |
| 10596 | // Other instructions |
| 10597 | //---------------------------------------------------------------------- |
| 10598 | { 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" }, |
Caroline Tice | 868198b | 2011-03-03 18:04:49 +0000 | [diff] [blame] | 10599 | { 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" }, |
| 10600 | { 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" }, |
Caroline Tice | 8ce96d9 | 2011-03-03 18:27:17 +0000 | [diff] [blame] | 10601 | { 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" }, |
| 10602 | { 0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>" }, |
Caroline Tice | 11555f2 | 2011-03-03 18:48:58 +0000 | [diff] [blame] | 10603 | { 0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}" }, |
| 10604 | { 0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>" }, |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10605 | { 0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}" }, |
| 10606 | { 0xffd00000, 0xe8100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}" }, |
| 10607 | { 0xffd00000, 0xe9900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}" } |
Caroline Tice | 6bf6516 | 2011-03-03 17:42:58 +0000 | [diff] [blame] | 10608 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 10609 | }; |
| 10610 | |
| 10611 | const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
| 10612 | for (size_t i=0; i<k_num_thumb_opcodes; ++i) |
| 10613 | { |
| 10614 | if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) |
| 10615 | return &g_thumb_opcodes[i]; |
| 10616 | } |
| 10617 | return NULL; |
| 10618 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10619 | |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 10620 | bool |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 10621 | EmulateInstructionARM::SetArchitecture (const ArchSpec &arch) |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 10622 | { |
| 10623 | m_arm_isa = 0; |
Greg Clayton | 940b103 | 2011-02-23 00:35:02 +0000 | [diff] [blame] | 10624 | const char *arch_cstr = arch.GetArchitectureName (); |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 10625 | if (arch_cstr) |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 10626 | { |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 10627 | if (0 == ::strcasecmp(arch_cstr, "armv4t")) m_arm_isa = ARMv4T; |
| 10628 | else if (0 == ::strcasecmp(arch_cstr, "armv4")) m_arm_isa = ARMv4; |
| 10629 | else if (0 == ::strcasecmp(arch_cstr, "armv5tej")) m_arm_isa = ARMv5TEJ; |
| 10630 | else if (0 == ::strcasecmp(arch_cstr, "armv5te")) m_arm_isa = ARMv5TE; |
| 10631 | else if (0 == ::strcasecmp(arch_cstr, "armv5t")) m_arm_isa = ARMv5T; |
| 10632 | else if (0 == ::strcasecmp(arch_cstr, "armv6k")) m_arm_isa = ARMv6K; |
| 10633 | else if (0 == ::strcasecmp(arch_cstr, "armv6")) m_arm_isa = ARMv6; |
| 10634 | else if (0 == ::strcasecmp(arch_cstr, "armv6t2")) m_arm_isa = ARMv6T2; |
| 10635 | else if (0 == ::strcasecmp(arch_cstr, "armv7")) m_arm_isa = ARMv7; |
| 10636 | else if (0 == ::strcasecmp(arch_cstr, "armv8")) m_arm_isa = ARMv8; |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 10637 | } |
| 10638 | return m_arm_isa != 0; |
| 10639 | } |
| 10640 | |
| 10641 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10642 | bool |
| 10643 | EmulateInstructionARM::ReadInstruction () |
| 10644 | { |
| 10645 | bool success = false; |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10646 | m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10647 | if (success) |
| 10648 | { |
| 10649 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 10650 | if (success) |
| 10651 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 10652 | Context read_inst_context; |
| 10653 | read_inst_context.type = eContextReadOpcode; |
| 10654 | read_inst_context.SetNoArgs (); |
| 10655 | |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10656 | if (m_opcode_cpsr & MASK_CPSR_T) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10657 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10658 | m_opcode_mode = eModeThumb; |
Caroline Tice | cc96eb5 | 2011-02-17 19:20:40 +0000 | [diff] [blame] | 10659 | uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10660 | |
| 10661 | if (success) |
| 10662 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10663 | if ((thumb_opcode & 0xe000) != 0xe000 || ((thumb_opcode & 0x1800u) == 0)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10664 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10665 | m_opcode.SetOpcode16 (thumb_opcode); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10666 | } |
| 10667 | else |
| 10668 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10669 | m_opcode.SetOpcode32 ((thumb_opcode << 16) | MemARead(read_inst_context, pc + 2, 2, 0, &success)); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10670 | } |
| 10671 | } |
| 10672 | } |
| 10673 | else |
| 10674 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10675 | m_opcode_mode = eModeARM; |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10676 | m_opcode.SetOpcode32 (MemARead(read_inst_context, pc, 4, 0, &success)); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10677 | } |
| 10678 | } |
| 10679 | } |
| 10680 | if (!success) |
| 10681 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10682 | m_opcode_mode = eModeInvalid; |
| 10683 | m_opcode_pc = LLDB_INVALID_ADDRESS; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10684 | } |
| 10685 | return success; |
| 10686 | } |
| 10687 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10688 | uint32_t |
| 10689 | EmulateInstructionARM::ArchVersion () |
| 10690 | { |
| 10691 | return m_arm_isa; |
| 10692 | } |
| 10693 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10694 | bool |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10695 | EmulateInstructionARM::ConditionPassed (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10696 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10697 | if (m_opcode_cpsr == 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10698 | return false; |
| 10699 | |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10700 | const uint32_t cond = CurrentCond (opcode); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10701 | |
| 10702 | if (cond == UINT32_MAX) |
| 10703 | return false; |
| 10704 | |
| 10705 | bool result = false; |
| 10706 | switch (UnsignedBits(cond, 3, 1)) |
| 10707 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10708 | case 0: result = (m_opcode_cpsr & MASK_CPSR_Z) != 0; break; |
| 10709 | case 1: result = (m_opcode_cpsr & MASK_CPSR_C) != 0; break; |
| 10710 | case 2: result = (m_opcode_cpsr & MASK_CPSR_N) != 0; break; |
| 10711 | case 3: result = (m_opcode_cpsr & MASK_CPSR_V) != 0; break; |
| 10712 | case 4: result = ((m_opcode_cpsr & MASK_CPSR_C) != 0) && ((m_opcode_cpsr & MASK_CPSR_Z) == 0); break; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10713 | case 5: |
| 10714 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10715 | bool n = (m_opcode_cpsr & MASK_CPSR_N); |
| 10716 | bool v = (m_opcode_cpsr & MASK_CPSR_V); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10717 | result = n == v; |
| 10718 | } |
| 10719 | break; |
| 10720 | case 6: |
| 10721 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10722 | bool n = (m_opcode_cpsr & MASK_CPSR_N); |
| 10723 | bool v = (m_opcode_cpsr & MASK_CPSR_V); |
| 10724 | result = n == v && ((m_opcode_cpsr & MASK_CPSR_Z) == 0); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10725 | } |
| 10726 | break; |
| 10727 | case 7: |
| 10728 | result = true; |
| 10729 | break; |
| 10730 | } |
| 10731 | |
| 10732 | if (cond & 1) |
| 10733 | result = !result; |
| 10734 | return result; |
| 10735 | } |
| 10736 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10737 | uint32_t |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10738 | EmulateInstructionARM::CurrentCond (const uint32_t opcode) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10739 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10740 | switch (m_opcode_mode) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10741 | { |
| 10742 | default: |
| 10743 | case eModeInvalid: |
| 10744 | break; |
| 10745 | |
| 10746 | case eModeARM: |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10747 | return UnsignedBits(opcode, 31, 28); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10748 | |
| 10749 | case eModeThumb: |
| 10750 | // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit |
| 10751 | // 'cond' field of the encoding. |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10752 | { |
Greg Clayton | 7bc3908 | 2011-03-24 23:53:38 +0000 | [diff] [blame] | 10753 | const uint32_t byte_size = m_opcode.GetByteSize(); |
| 10754 | if (byte_size == 2) |
| 10755 | { |
| 10756 | if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 7) != 0x0f) |
| 10757 | return Bits32(opcode, 11, 7); |
| 10758 | } |
| 10759 | else |
| 10760 | { |
| 10761 | assert (byte_size == 4); |
| 10762 | if (Bits32(opcode, 31, 27) == 0x1e && |
| 10763 | Bits32(opcode, 15, 14) == 0x02 && |
| 10764 | Bits32(opcode, 12, 12) == 0x00 && |
| 10765 | Bits32(opcode, 25, 22) <= 0x0d) |
| 10766 | { |
| 10767 | return Bits32(opcode, 25, 22); |
| 10768 | } |
| 10769 | } |
| 10770 | |
| 10771 | return m_it_session.GetCond(); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10772 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10773 | } |
| 10774 | return UINT32_MAX; // Return invalid value |
| 10775 | } |
| 10776 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10777 | bool |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 10778 | EmulateInstructionARM::InITBlock() |
| 10779 | { |
| 10780 | return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock(); |
| 10781 | } |
| 10782 | |
| 10783 | bool |
| 10784 | EmulateInstructionARM::LastInITBlock() |
| 10785 | { |
| 10786 | return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock(); |
| 10787 | } |
| 10788 | |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10789 | bool |
| 10790 | EmulateInstructionARM::BadMode (uint32_t mode) |
| 10791 | { |
| 10792 | |
| 10793 | switch (mode) |
| 10794 | { |
| 10795 | case 16: return false; // '10000' |
| 10796 | case 17: return false; // '10001' |
| 10797 | case 18: return false; // '10010' |
| 10798 | case 19: return false; // '10011' |
| 10799 | case 22: return false; // '10110' |
| 10800 | case 23: return false; // '10111' |
| 10801 | case 27: return false; // '11011' |
| 10802 | case 31: return false; // '11111' |
| 10803 | default: return true; |
| 10804 | } |
| 10805 | return true; |
| 10806 | } |
| 10807 | |
| 10808 | bool |
| 10809 | EmulateInstructionARM::CurrentModeIsPrivileged () |
| 10810 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10811 | uint32_t mode = Bits32 (m_opcode_cpsr, 4, 0); |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10812 | |
| 10813 | if (BadMode (mode)) |
| 10814 | return false; |
| 10815 | |
| 10816 | if (mode == 16) |
| 10817 | return false; |
| 10818 | |
| 10819 | return true; |
| 10820 | } |
| 10821 | |
| 10822 | void |
| 10823 | EmulateInstructionARM::CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate) |
| 10824 | { |
| 10825 | bool privileged = CurrentModeIsPrivileged(); |
| 10826 | |
| 10827 | uint32_t tmp_cpsr = 0; |
| 10828 | |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10829 | tmp_cpsr = tmp_cpsr | (Bits32 (m_opcode_cpsr, 23, 20) << 20); |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10830 | |
| 10831 | if (BitIsSet (bytemask, 3)) |
| 10832 | { |
| 10833 | tmp_cpsr = tmp_cpsr | (Bits32 (value, 31, 27) << 27); |
| 10834 | if (affect_execstate) |
| 10835 | tmp_cpsr = tmp_cpsr | (Bits32 (value, 26, 24) << 24); |
| 10836 | } |
| 10837 | |
| 10838 | if (BitIsSet (bytemask, 2)) |
| 10839 | { |
| 10840 | tmp_cpsr = tmp_cpsr | (Bits32 (value, 19, 16) << 16); |
| 10841 | } |
| 10842 | |
| 10843 | if (BitIsSet (bytemask, 1)) |
| 10844 | { |
| 10845 | if (affect_execstate) |
| 10846 | tmp_cpsr = tmp_cpsr | (Bits32 (value, 15, 10) << 10); |
| 10847 | tmp_cpsr = tmp_cpsr | (Bit32 (value, 9) << 9); |
| 10848 | if (privileged) |
| 10849 | tmp_cpsr = tmp_cpsr | (Bit32 (value, 8) << 8); |
| 10850 | } |
| 10851 | |
| 10852 | if (BitIsSet (bytemask, 0)) |
| 10853 | { |
| 10854 | if (privileged) |
| 10855 | tmp_cpsr = tmp_cpsr | (Bits32 (value, 7, 6) << 6); |
| 10856 | if (affect_execstate) |
| 10857 | tmp_cpsr = tmp_cpsr | (Bit32 (value, 5) << 5); |
| 10858 | if (privileged) |
| 10859 | tmp_cpsr = tmp_cpsr | Bits32 (value, 4, 0); |
| 10860 | } |
| 10861 | |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10862 | m_opcode_cpsr = tmp_cpsr; |
Caroline Tice | b27771d | 2011-03-03 22:37:46 +0000 | [diff] [blame] | 10863 | } |
| 10864 | |
| 10865 | |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 10866 | bool |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10867 | EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr) |
| 10868 | { |
| 10869 | addr_t target; |
| 10870 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10871 | // Check the current instruction set. |
| 10872 | if (CurrentInstrSet() == eModeARM) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10873 | target = addr & 0xfffffffc; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10874 | else |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10875 | target = addr & 0xfffffffe; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10876 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10877 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 10878 | return false; |
| 10879 | |
| 10880 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10881 | } |
| 10882 | |
| 10883 | // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. |
| 10884 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10885 | EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10886 | { |
| 10887 | addr_t target; |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 10888 | // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, |
| 10889 | // we want to record it and issue a WriteRegister callback so the clients |
| 10890 | // can track the mode changes accordingly. |
| 10891 | bool cpsr_changed = false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10892 | |
| 10893 | if (BitIsSet(addr, 0)) |
| 10894 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 10895 | if (CurrentInstrSet() != eModeThumb) |
| 10896 | { |
| 10897 | SelectInstrSet(eModeThumb); |
| 10898 | cpsr_changed = true; |
| 10899 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10900 | target = addr & 0xfffffffe; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10901 | context.SetMode (eModeThumb); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10902 | } |
| 10903 | else if (BitIsClear(addr, 1)) |
| 10904 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 10905 | if (CurrentInstrSet() != eModeARM) |
| 10906 | { |
| 10907 | SelectInstrSet(eModeARM); |
| 10908 | cpsr_changed = true; |
| 10909 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10910 | target = addr & 0xfffffffc; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10911 | context.SetMode (eModeARM); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10912 | } |
| 10913 | else |
| 10914 | return false; // address<1:0> == '10' => UNPREDICTABLE |
| 10915 | |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 10916 | if (cpsr_changed) |
| 10917 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 10918 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 10919 | return false; |
| 10920 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10921 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 10922 | return false; |
| 10923 | |
| 10924 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 10925 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 10926 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10927 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions. |
| 10928 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10929 | EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr) |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10930 | { |
| 10931 | if (ArchVersion() >= ARMv5T) |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10932 | return BXWritePC(context, addr); |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10933 | else |
| 10934 | return BranchWritePC((const Context)context, addr); |
| 10935 | } |
| 10936 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10937 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set. |
| 10938 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10939 | EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10940 | { |
| 10941 | if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 10942 | return BXWritePC(context, addr); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 10943 | else |
| 10944 | return BranchWritePC((const Context)context, addr); |
| 10945 | } |
| 10946 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10947 | EmulateInstructionARM::Mode |
| 10948 | EmulateInstructionARM::CurrentInstrSet () |
| 10949 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10950 | return m_opcode_mode; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10951 | } |
| 10952 | |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10953 | // Set the 'T' bit of our CPSR. The m_opcode_mode gets updated when the next |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 10954 | // ReadInstruction() is performed. This function has a side effect of updating |
| 10955 | // the m_new_inst_cpsr member variable if necessary. |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10956 | bool |
| 10957 | EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb) |
| 10958 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 10959 | m_new_inst_cpsr = m_opcode_cpsr; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10960 | switch (arm_or_thumb) |
| 10961 | { |
| 10962 | default: |
| 10963 | return false; |
| 10964 | eModeARM: |
| 10965 | // Clear the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 10966 | m_new_inst_cpsr &= ~MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10967 | break; |
| 10968 | eModeThumb: |
| 10969 | // Set the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 10970 | m_new_inst_cpsr |= MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 10971 | break; |
| 10972 | } |
| 10973 | return true; |
| 10974 | } |
| 10975 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 10976 | // This function returns TRUE if the processor currently provides support for |
| 10977 | // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7, |
| 10978 | // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6. |
| 10979 | bool |
| 10980 | EmulateInstructionARM::UnalignedSupport() |
| 10981 | { |
| 10982 | return (ArchVersion() >= ARMv7); |
| 10983 | } |
| 10984 | |
Johnny Chen | bf6ad17 | 2011-02-11 01:29:53 +0000 | [diff] [blame] | 10985 | // The main addition and subtraction instructions can produce status information |
| 10986 | // about both unsigned carry and signed overflow conditions. This status |
| 10987 | // information can be used to synthesize multi-word additions and subtractions. |
| 10988 | EmulateInstructionARM::AddWithCarryResult |
| 10989 | EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in) |
| 10990 | { |
| 10991 | uint32_t result; |
| 10992 | uint8_t carry_out; |
| 10993 | uint8_t overflow; |
| 10994 | |
| 10995 | uint64_t unsigned_sum = x + y + carry_in; |
| 10996 | int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in; |
| 10997 | |
| 10998 | result = UnsignedBits(unsigned_sum, 31, 0); |
| 10999 | carry_out = (result == unsigned_sum ? 0 : 1); |
| 11000 | overflow = ((int32_t)result == signed_sum ? 0 : 1); |
| 11001 | |
| 11002 | AddWithCarryResult res = { result, carry_out, overflow }; |
| 11003 | return res; |
| 11004 | } |
| 11005 | |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11006 | uint32_t |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11007 | EmulateInstructionARM::ReadCoreReg(uint32_t num, bool *success) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11008 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11009 | uint32_t reg_kind, reg_num; |
| 11010 | switch (num) |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11011 | { |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11012 | case SP_REG: |
| 11013 | reg_kind = eRegisterKindGeneric; |
| 11014 | reg_num = LLDB_REGNUM_GENERIC_SP; |
| 11015 | break; |
| 11016 | case LR_REG: |
| 11017 | reg_kind = eRegisterKindGeneric; |
| 11018 | reg_num = LLDB_REGNUM_GENERIC_RA; |
| 11019 | break; |
| 11020 | case PC_REG: |
| 11021 | reg_kind = eRegisterKindGeneric; |
| 11022 | reg_num = LLDB_REGNUM_GENERIC_PC; |
| 11023 | break; |
| 11024 | default: |
Greg Clayton | 4fdf760 | 2011-03-20 04:57:14 +0000 | [diff] [blame] | 11025 | if (num < SP_REG) |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11026 | { |
| 11027 | reg_kind = eRegisterKindDWARF; |
| 11028 | reg_num = dwarf_r0 + num; |
| 11029 | } |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11030 | else |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11031 | { |
| 11032 | assert(0 && "Invalid register number"); |
| 11033 | *success = false; |
Greg Clayton | 4fdf760 | 2011-03-20 04:57:14 +0000 | [diff] [blame] | 11034 | return UINT32_MAX; |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11035 | } |
| 11036 | break; |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11037 | } |
Johnny Chen | e39f22d | 2011-02-19 01:36:13 +0000 | [diff] [blame] | 11038 | |
| 11039 | // Read our register. |
| 11040 | uint32_t val = ReadRegisterUnsigned (reg_kind, reg_num, 0, success); |
| 11041 | |
| 11042 | // When executing an ARM instruction , PC reads as the address of the current |
| 11043 | // instruction plus 8. |
| 11044 | // When executing a Thumb instruction , PC reads as the address of the current |
| 11045 | // instruction plus 4. |
| 11046 | if (num == 15) |
| 11047 | { |
| 11048 | if (CurrentInstrSet() == eModeARM) |
| 11049 | val += 8; |
| 11050 | else |
| 11051 | val += 4; |
| 11052 | } |
Johnny Chen | 157b959 | 2011-02-18 21:13:05 +0000 | [diff] [blame] | 11053 | |
| 11054 | return val; |
| 11055 | } |
| 11056 | |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 11057 | // Write the result to the ARM core register Rd, and optionally update the |
| 11058 | // condition flags based on the result. |
| 11059 | // |
| 11060 | // This helper method tries to encapsulate the following pseudocode from the |
| 11061 | // ARM Architecture Reference Manual: |
| 11062 | // |
| 11063 | // if d == 15 then // Can only occur for encoding A1 |
| 11064 | // ALUWritePC(result); // setflags is always FALSE here |
| 11065 | // else |
| 11066 | // R[d] = result; |
| 11067 | // if setflags then |
| 11068 | // APSR.N = result<31>; |
| 11069 | // APSR.Z = IsZeroBit(result); |
| 11070 | // APSR.C = carry; |
| 11071 | // // APSR.V unchanged |
| 11072 | // |
| 11073 | // In the above case, the API client does not pass in the overflow arg, which |
| 11074 | // defaults to ~0u. |
| 11075 | bool |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 11076 | EmulateInstructionARM::WriteCoreRegOptionalFlags (Context &context, |
| 11077 | const uint32_t result, |
| 11078 | const uint32_t Rd, |
| 11079 | bool setflags, |
| 11080 | const uint32_t carry, |
| 11081 | const uint32_t overflow) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 11082 | { |
| 11083 | if (Rd == 15) |
| 11084 | { |
| 11085 | if (!ALUWritePC (context, result)) |
| 11086 | return false; |
| 11087 | } |
| 11088 | else |
| 11089 | { |
Johnny Chen | a695f95 | 2011-02-23 21:24:25 +0000 | [diff] [blame] | 11090 | uint32_t reg_kind, reg_num; |
| 11091 | switch (Rd) |
| 11092 | { |
| 11093 | case SP_REG: |
| 11094 | reg_kind = eRegisterKindGeneric; |
| 11095 | reg_num = LLDB_REGNUM_GENERIC_SP; |
| 11096 | break; |
| 11097 | case LR_REG: |
| 11098 | reg_kind = eRegisterKindGeneric; |
| 11099 | reg_num = LLDB_REGNUM_GENERIC_RA; |
| 11100 | break; |
| 11101 | default: |
| 11102 | reg_kind = eRegisterKindDWARF; |
| 11103 | reg_num = dwarf_r0 + Rd; |
| 11104 | } |
| 11105 | if (!WriteRegisterUnsigned (context, reg_kind, reg_num, result)) |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 11106 | return false; |
| 11107 | if (setflags) |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 11108 | return WriteFlags (context, result, carry, overflow); |
| 11109 | } |
| 11110 | return true; |
| 11111 | } |
| 11112 | |
| 11113 | // This helper method tries to encapsulate the following pseudocode from the |
| 11114 | // ARM Architecture Reference Manual: |
| 11115 | // |
| 11116 | // APSR.N = result<31>; |
| 11117 | // APSR.Z = IsZeroBit(result); |
| 11118 | // APSR.C = carry; |
| 11119 | // APSR.V = overflow |
| 11120 | // |
| 11121 | // Default arguments can be specified for carry and overflow parameters, which means |
| 11122 | // not to update the respective flags. |
| 11123 | bool |
| 11124 | EmulateInstructionARM::WriteFlags (Context &context, |
| 11125 | const uint32_t result, |
| 11126 | const uint32_t carry, |
| 11127 | const uint32_t overflow) |
| 11128 | { |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 11129 | m_new_inst_cpsr = m_opcode_cpsr; |
Johnny Chen | 2434884 | 2011-02-23 00:15:56 +0000 | [diff] [blame] | 11130 | SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, CPSR_N_POS)); |
| 11131 | SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0); |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 11132 | if (carry != ~0u) |
Johnny Chen | 2434884 | 2011-02-23 00:15:56 +0000 | [diff] [blame] | 11133 | SetBit32(m_new_inst_cpsr, CPSR_C_POS, carry); |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 11134 | if (overflow != ~0u) |
Johnny Chen | 2434884 | 2011-02-23 00:15:56 +0000 | [diff] [blame] | 11135 | SetBit32(m_new_inst_cpsr, CPSR_V_POS, overflow); |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 11136 | if (m_new_inst_cpsr != m_opcode_cpsr) |
Johnny Chen | 10530c2 | 2011-02-17 22:37:12 +0000 | [diff] [blame] | 11137 | { |
| 11138 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 11139 | return false; |
Johnny Chen | ca67d1c | 2011-02-17 01:35:27 +0000 | [diff] [blame] | 11140 | } |
| 11141 | return true; |
| 11142 | } |
| 11143 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 11144 | bool |
| 11145 | EmulateInstructionARM::EvaluateInstruction () |
| 11146 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 11147 | // Advance the ITSTATE bits to their values for the next instruction. |
Greg Clayton | b344843 | 2011-03-24 21:19:54 +0000 | [diff] [blame] | 11148 | if (m_opcode_mode == eModeThumb && m_it_session.InITBlock()) |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 11149 | m_it_session.ITAdvance(); |
| 11150 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 11151 | return false; |
| 11152 | } |