Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | #include "EmulateInstructionARM.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 11 | #include "lldb/Core/ConstString.h" |
| 12 | |
Johnny Chen | 8584c92 | 2011-01-26 01:18:52 +0000 | [diff] [blame] | 13 | #include "ARMDefines.h" |
Johnny Chen | 4baf2e3 | 2011-01-24 18:24:53 +0000 | [diff] [blame] | 14 | #include "ARMUtils.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 15 | #include "ARM_DWARF_Registers.h" |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 16 | #include "llvm/Support/MathExtras.h" // for SignExtend32 template function |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 17 | // and CountTrailingZeros_32 function |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 18 | |
| 19 | using namespace lldb; |
| 20 | using namespace lldb_private; |
| 21 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 22 | // A8.6.50 |
| 23 | // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. |
| 24 | static unsigned short CountITSize(unsigned ITMask) { |
| 25 | // First count the trailing zeros of the IT mask. |
| 26 | unsigned TZ = llvm::CountTrailingZeros_32(ITMask); |
| 27 | if (TZ > 3) |
| 28 | { |
| 29 | printf("Encoding error: IT Mask '0000'\n"); |
| 30 | return 0; |
| 31 | } |
| 32 | return (4 - TZ); |
| 33 | } |
| 34 | |
| 35 | // Init ITState. Note that at least one bit is always 1 in mask. |
| 36 | bool ITSession::InitIT(unsigned short bits7_0) |
| 37 | { |
| 38 | ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); |
| 39 | if (ITCounter == 0) |
| 40 | return false; |
| 41 | |
| 42 | // A8.6.50 IT |
| 43 | unsigned short FirstCond = Bits32(bits7_0, 7, 4); |
| 44 | if (FirstCond == 0xF) |
| 45 | { |
| 46 | printf("Encoding error: IT FirstCond '1111'\n"); |
| 47 | return false; |
| 48 | } |
| 49 | if (FirstCond == 0xE && ITCounter != 1) |
| 50 | { |
| 51 | printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n"); |
| 52 | return false; |
| 53 | } |
| 54 | |
| 55 | ITState = bits7_0; |
| 56 | return true; |
| 57 | } |
| 58 | |
| 59 | // Update ITState if necessary. |
| 60 | void ITSession::ITAdvance() |
| 61 | { |
| 62 | assert(ITCounter); |
| 63 | --ITCounter; |
| 64 | if (ITCounter == 0) |
| 65 | ITState = 0; |
| 66 | else |
| 67 | { |
| 68 | unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; |
| 69 | SetBits32(ITState, 4, 0, NewITState4_0); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | // Return true if we're inside an IT Block. |
| 74 | bool ITSession::InITBlock() |
| 75 | { |
| 76 | return ITCounter != 0; |
| 77 | } |
| 78 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 79 | // Return true if we're the last instruction inside an IT Block. |
| 80 | bool ITSession::LastInITBlock() |
| 81 | { |
| 82 | return ITCounter == 1; |
| 83 | } |
| 84 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 85 | // Get condition bits for the current thumb instruction. |
| 86 | uint32_t ITSession::GetCond() |
| 87 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 88 | if (InITBlock()) |
| 89 | return Bits32(ITState, 7, 4); |
| 90 | else |
| 91 | return COND_AL; |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 94 | // ARM constants used during decoding |
| 95 | #define REG_RD 0 |
| 96 | #define LDM_REGLIST 1 |
| 97 | #define PC_REG 15 |
| 98 | #define PC_REGLIST_BIT 0x8000 |
| 99 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 100 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 101 | #define ARMv4T (1u << 1) |
| 102 | #define ARMv5T (1u << 2) |
| 103 | #define ARMv5TE (1u << 3) |
| 104 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 105 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 106 | #define ARMv6K (1u << 6) |
| 107 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 108 | #define ARMv7 (1u << 8) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 109 | #define ARMv8 (1u << 9) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 110 | #define ARMvAll (0xffffffffu) |
| 111 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 112 | #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 113 | #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 114 | #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 115 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 116 | void |
| 117 | EmulateInstructionARM::Initialize () |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 118 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 119 | } |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 120 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 121 | void |
| 122 | EmulateInstructionARM::Terminate () |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 123 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 124 | } |
| 125 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 126 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 127 | // Push Multiple Registers stores multiple registers to the stack, storing to |
| 128 | // consecutive memory locations ending just below the address in SP, and updates |
| 129 | // SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 130 | bool |
| 131 | EmulateInstructionARM::EmulatePush (ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 132 | { |
| 133 | #if 0 |
| 134 | // ARM pseudo code... |
| 135 | if (ConditionPassed()) |
| 136 | { |
| 137 | EncodingSpecificOperations(); |
| 138 | NullCheckIfThumbEE(13); |
| 139 | address = SP - 4*BitCount(registers); |
| 140 | |
| 141 | for (i = 0 to 14) |
| 142 | { |
| 143 | if (registers<i> == ’1’) |
| 144 | { |
| 145 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 146 | MemA[address,4] = bits(32) UNKNOWN; |
| 147 | else |
| 148 | MemA[address,4] = R[i]; |
| 149 | address = address + 4; |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | if (registers<15> == ’1’) // Only possible for encoding A1 or A2 |
| 154 | MemA[address,4] = PCStoreValue(); |
| 155 | |
| 156 | SP = SP - 4*BitCount(registers); |
| 157 | } |
| 158 | #endif |
| 159 | |
| 160 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 161 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 162 | if (!success) |
| 163 | return false; |
| 164 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 165 | if (ConditionPassed()) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 166 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 167 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 168 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 169 | if (!success) |
| 170 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 171 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 172 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 173 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 174 | case eEncodingT1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 175 | registers = Bits32(opcode, 7, 0); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 176 | // The M bit represents LR. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 177 | if (Bits32(opcode, 8, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 178 | registers |= (1u << 14); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 179 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 180 | if (BitCount(registers) < 1) |
| 181 | return false; |
| 182 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 183 | case eEncodingT2: |
| 184 | // Ignore bits 15 & 13. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 185 | registers = Bits32(opcode, 15, 0) & ~0xa000; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 186 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 187 | if (BitCount(registers) < 2) |
| 188 | return false; |
| 189 | break; |
| 190 | case eEncodingT3: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 191 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 192 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 193 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 194 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 195 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 196 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 197 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 198 | registers = Bits32(opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 199 | // Instead of return false, let's handle the following case as well, |
| 200 | // which amounts to pushing one reg onto the full descending stacks. |
| 201 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 202 | break; |
| 203 | case eEncodingA2: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 204 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 205 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 206 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 207 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 208 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 209 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 210 | default: |
| 211 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 212 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 213 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 214 | addr_t addr = sp - sp_offset; |
| 215 | uint32_t i; |
| 216 | |
| 217 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
| 218 | for (i=0; i<15; ++i) |
| 219 | { |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 220 | if (BitIsSet (registers, 1u << i)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 221 | { |
| 222 | context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number |
| 223 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 224 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 225 | if (!success) |
| 226 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 227 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 228 | return false; |
| 229 | addr += addr_byte_size; |
| 230 | } |
| 231 | } |
| 232 | |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 233 | if (BitIsSet (registers, 1u << 15)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 234 | { |
| 235 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 236 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 237 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 238 | if (!success) |
| 239 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 240 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 241 | return false; |
| 242 | } |
| 243 | |
| 244 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 245 | context.arg0 = eRegisterKindGeneric; |
| 246 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 247 | context.arg2 = -sp_offset; |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 248 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 249 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 250 | return false; |
| 251 | } |
| 252 | return true; |
| 253 | } |
| 254 | |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 255 | // Pop Multiple Registers loads multiple registers from the stack, loading from |
| 256 | // consecutive memory locations staring at the address in SP, and updates |
| 257 | // SP to point just above the loaded data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 258 | bool |
| 259 | EmulateInstructionARM::EmulatePop (ARMEncoding encoding) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 260 | { |
| 261 | #if 0 |
| 262 | // ARM pseudo code... |
| 263 | if (ConditionPassed()) |
| 264 | { |
| 265 | EncodingSpecificOperations(); NullCheckIfThumbEE(13); |
| 266 | address = SP; |
| 267 | for i = 0 to 14 |
| 268 | if registers<i> == ‘1’ then |
| 269 | R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; |
| 270 | if registers<15> == ‘1’ then |
| 271 | if UnalignedAllowed then |
| 272 | LoadWritePC(MemU[address,4]); |
| 273 | else |
| 274 | LoadWritePC(MemA[address,4]); |
| 275 | if registers<13> == ‘0’ then SP = SP + 4*BitCount(registers); |
| 276 | if registers<13> == ‘1’ then SP = bits(32) UNKNOWN; |
| 277 | } |
| 278 | #endif |
| 279 | |
| 280 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 281 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 282 | if (!success) |
| 283 | return false; |
| 284 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 285 | if (ConditionPassed()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 286 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 287 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 288 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 289 | if (!success) |
| 290 | return false; |
| 291 | uint32_t registers = 0; |
| 292 | uint32_t Rt; // the destination register |
| 293 | switch (encoding) { |
| 294 | case eEncodingT1: |
| 295 | registers = Bits32(opcode, 7, 0); |
| 296 | // The P bit represents PC. |
| 297 | if (Bits32(opcode, 8, 8)) |
| 298 | registers |= (1u << 15); |
| 299 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 300 | if (BitCount(registers) < 1) |
| 301 | return false; |
| 302 | break; |
| 303 | case eEncodingT2: |
| 304 | // Ignore bit 13. |
| 305 | registers = Bits32(opcode, 15, 0) & ~0x2000; |
| 306 | // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
| 307 | if (BitCount(registers) < 2 || (Bits32(opcode, 15, 15) && Bits32(opcode, 14, 14))) |
| 308 | return false; |
| 309 | break; |
| 310 | case eEncodingT3: |
| 311 | Rt = Bits32(opcode, 15, 12); |
| 312 | // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
| 313 | if (Rt == dwarf_sp) |
| 314 | return false; |
| 315 | registers = (1u << Rt); |
| 316 | break; |
| 317 | case eEncodingA1: |
| 318 | registers = Bits32(opcode, 15, 0); |
| 319 | // Instead of return false, let's handle the following case as well, |
| 320 | // which amounts to popping one reg from the full descending stacks. |
| 321 | // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; |
| 322 | |
| 323 | // if registers<13> == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE; |
| 324 | if (Bits32(opcode, 13, 13)) |
| 325 | return false; |
| 326 | break; |
| 327 | case eEncodingA2: |
| 328 | Rt = Bits32(opcode, 15, 12); |
| 329 | // if t == 13 then UNPREDICTABLE; |
| 330 | if (Rt == dwarf_sp) |
| 331 | return false; |
| 332 | registers = (1u << Rt); |
| 333 | break; |
| 334 | default: |
| 335 | return false; |
| 336 | } |
| 337 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
| 338 | addr_t addr = sp; |
| 339 | uint32_t i, data; |
| 340 | |
| 341 | EmulateInstruction::Context context = { EmulateInstruction::eContextPopRegisterOffStack, eRegisterKindDWARF, 0, 0 }; |
| 342 | for (i=0; i<15; ++i) |
| 343 | { |
| 344 | if (BitIsSet (registers, 1u << i)) |
| 345 | { |
| 346 | context.arg1 = dwarf_r0 + i; // arg1 in the context is the DWARF register number |
| 347 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 348 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 349 | if (!success) |
| 350 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 351 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, context.arg1, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 352 | return false; |
| 353 | addr += addr_byte_size; |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | if (BitIsSet (registers, 1u << 15)) |
| 358 | { |
| 359 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 360 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 361 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 362 | if (!success) |
| 363 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 364 | if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 365 | return false; |
| 366 | addr += addr_byte_size; |
| 367 | } |
| 368 | |
| 369 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 370 | context.arg0 = eRegisterKindGeneric; |
| 371 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 372 | context.arg2 = sp_offset; |
| 373 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 374 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 375 | return false; |
| 376 | } |
| 377 | return true; |
| 378 | } |
| 379 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 380 | // Set r7 or ip to point to saved value residing within the stack. |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 381 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 382 | bool |
| 383 | EmulateInstructionARM::EmulateAddRdSPImmediate (ARMEncoding encoding) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 384 | { |
| 385 | #if 0 |
| 386 | // ARM pseudo code... |
| 387 | if (ConditionPassed()) |
| 388 | { |
| 389 | EncodingSpecificOperations(); |
| 390 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 391 | if d == 15 then |
| 392 | ALUWritePC(result); // setflags is always FALSE here |
| 393 | else |
| 394 | R[d] = result; |
| 395 | if setflags then |
| 396 | APSR.N = result<31>; |
| 397 | APSR.Z = IsZeroBit(result); |
| 398 | APSR.C = carry; |
| 399 | APSR.V = overflow; |
| 400 | } |
| 401 | #endif |
| 402 | |
| 403 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 404 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 405 | if (!success) |
| 406 | return false; |
| 407 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 408 | if (ConditionPassed()) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 409 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 410 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 411 | if (!success) |
| 412 | return false; |
| 413 | uint32_t Rd; // the destination register |
| 414 | uint32_t imm32; |
| 415 | switch (encoding) { |
| 416 | case eEncodingT1: |
| 417 | Rd = 7; |
| 418 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) |
| 419 | break; |
| 420 | case eEncodingA1: |
| 421 | Rd = Bits32(opcode, 15, 12); |
| 422 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 423 | break; |
| 424 | default: |
| 425 | return false; |
| 426 | } |
| 427 | addr_t sp_offset = imm32; |
| 428 | addr_t addr = sp + sp_offset; // a pointer to the stack area |
| 429 | |
| 430 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 431 | eRegisterKindGeneric, |
| 432 | LLDB_REGNUM_GENERIC_SP, |
| 433 | sp_offset }; |
| 434 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 435 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 436 | return false; |
| 437 | } |
| 438 | return true; |
| 439 | } |
| 440 | |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 441 | // Set r7 or ip to the current stack pointer. |
| 442 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 443 | bool |
| 444 | EmulateInstructionARM::EmulateMovRdSP (ARMEncoding encoding) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 445 | { |
| 446 | #if 0 |
| 447 | // ARM pseudo code... |
| 448 | if (ConditionPassed()) |
| 449 | { |
| 450 | EncodingSpecificOperations(); |
| 451 | result = R[m]; |
| 452 | if d == 15 then |
| 453 | ALUWritePC(result); // setflags is always FALSE here |
| 454 | else |
| 455 | R[d] = result; |
| 456 | if setflags then |
| 457 | APSR.N = result<31>; |
| 458 | APSR.Z = IsZeroBit(result); |
| 459 | // APSR.C unchanged |
| 460 | // APSR.V unchanged |
| 461 | } |
| 462 | #endif |
| 463 | |
| 464 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 465 | //const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 466 | //if (!success) |
| 467 | // return false; |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 468 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 469 | if (ConditionPassed()) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 470 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 471 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 472 | if (!success) |
| 473 | return false; |
| 474 | uint32_t Rd; // the destination register |
| 475 | switch (encoding) { |
| 476 | case eEncodingT1: |
| 477 | Rd = 7; |
| 478 | break; |
| 479 | case eEncodingA1: |
| 480 | Rd = 12; |
| 481 | break; |
| 482 | default: |
| 483 | return false; |
| 484 | } |
| 485 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 486 | eRegisterKindGeneric, |
| 487 | LLDB_REGNUM_GENERIC_SP, |
| 488 | 0 }; |
| 489 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 490 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 491 | return false; |
| 492 | } |
| 493 | return true; |
| 494 | } |
| 495 | |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 496 | // Move from high register (r8-r15) to low register (r0-r7). |
| 497 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 498 | bool |
| 499 | EmulateInstructionARM::EmulateMovLowHigh (ARMEncoding encoding) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 500 | { |
| 501 | #if 0 |
| 502 | // ARM pseudo code... |
| 503 | if (ConditionPassed()) |
| 504 | { |
| 505 | EncodingSpecificOperations(); |
| 506 | result = R[m]; |
| 507 | if d == 15 then |
| 508 | ALUWritePC(result); // setflags is always FALSE here |
| 509 | else |
| 510 | R[d] = result; |
| 511 | if setflags then |
| 512 | APSR.N = result<31>; |
| 513 | APSR.Z = IsZeroBit(result); |
| 514 | // APSR.C unchanged |
| 515 | // APSR.V unchanged |
| 516 | } |
| 517 | #endif |
| 518 | |
| 519 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 520 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 521 | if (!success) |
| 522 | return false; |
| 523 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 524 | if (ConditionPassed()) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 525 | { |
| 526 | uint32_t Rm; // the source register |
| 527 | uint32_t Rd; // the destination register |
| 528 | switch (encoding) { |
| 529 | case eEncodingT1: |
| 530 | Rm = Bits32(opcode, 6, 3); |
| 531 | Rd = Bits32(opcode, 2, 1); // bits(7) == 0 |
| 532 | break; |
| 533 | default: |
| 534 | return false; |
| 535 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 536 | int32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 537 | if (!success) |
| 538 | return false; |
| 539 | |
| 540 | // The context specifies that Rm is to be moved into Rd. |
| 541 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 542 | eRegisterKindDWARF, |
| 543 | dwarf_r0 + Rm, |
| 544 | 0 }; |
| 545 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 546 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, reg_value)) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 547 | return false; |
| 548 | } |
| 549 | return true; |
| 550 | } |
| 551 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 552 | // PC relative immediate load into register, possibly followed by ADD (SP plus register). |
| 553 | // LDR (literal) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 554 | bool |
| 555 | EmulateInstructionARM::EmulateLDRRdPCRelative (ARMEncoding encoding) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 556 | { |
| 557 | #if 0 |
| 558 | // ARM pseudo code... |
| 559 | if (ConditionPassed()) |
| 560 | { |
| 561 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 562 | base = Align(PC,4); |
| 563 | address = if add then (base + imm32) else (base - imm32); |
| 564 | data = MemU[address,4]; |
| 565 | if t == 15 then |
| 566 | if address<1:0> == ‘00’ then LoadWritePC(data); else UNPREDICTABLE; |
| 567 | elsif UnalignedSupport() || address<1:0> = ‘00’ then |
| 568 | R[t] = data; |
| 569 | else // Can only apply before ARMv7 |
| 570 | if CurrentInstrSet() == InstrSet_ARM then |
| 571 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 572 | else |
| 573 | R[t] = bits(32) UNKNOWN; |
| 574 | } |
| 575 | #endif |
| 576 | |
| 577 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 578 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 579 | if (!success) |
| 580 | return false; |
| 581 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 582 | if (ConditionPassed()) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 583 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 584 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 585 | if (!success) |
| 586 | return false; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 587 | |
| 588 | // PC relative immediate load context |
| 589 | EmulateInstruction::Context context = {EmulateInstruction::eContextRegisterPlusOffset, |
| 590 | eRegisterKindGeneric, |
| 591 | LLDB_REGNUM_GENERIC_PC, |
| 592 | 0}; |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 593 | uint32_t Rd; // the destination register |
| 594 | uint32_t imm32; // immediate offset from the PC |
| 595 | addr_t addr; // the PC relative address |
| 596 | uint32_t data; // the literal data value from the PC relative load |
| 597 | switch (encoding) { |
| 598 | case eEncodingT1: |
| 599 | Rd = Bits32(opcode, 10, 8); |
| 600 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); |
| 601 | addr = pc + 4 + imm32; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 602 | context.arg2 = 4 + imm32; |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 603 | break; |
| 604 | default: |
| 605 | return false; |
| 606 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 607 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 608 | if (!success) |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 609 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 610 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, data)) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 611 | return false; |
| 612 | } |
| 613 | return true; |
| 614 | } |
| 615 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 616 | // An add operation to adjust the SP. |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 617 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 618 | bool |
| 619 | EmulateInstructionARM::EmulateAddSPImmediate (ARMEncoding encoding) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 620 | { |
| 621 | #if 0 |
| 622 | // ARM pseudo code... |
| 623 | if (ConditionPassed()) |
| 624 | { |
| 625 | EncodingSpecificOperations(); |
| 626 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 627 | if d == 15 then // Can only occur for ARM encoding |
| 628 | ALUWritePC(result); // setflags is always FALSE here |
| 629 | else |
| 630 | R[d] = result; |
| 631 | if setflags then |
| 632 | APSR.N = result<31>; |
| 633 | APSR.Z = IsZeroBit(result); |
| 634 | APSR.C = carry; |
| 635 | APSR.V = overflow; |
| 636 | } |
| 637 | #endif |
| 638 | |
| 639 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 640 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 641 | if (!success) |
| 642 | return false; |
| 643 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 644 | if (ConditionPassed()) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 645 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 646 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 647 | if (!success) |
| 648 | return false; |
| 649 | uint32_t imm32; // the immediate operand |
| 650 | switch (encoding) { |
| 651 | case eEncodingT2: |
| 652 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
| 653 | break; |
| 654 | default: |
| 655 | return false; |
| 656 | } |
| 657 | addr_t sp_offset = imm32; |
| 658 | addr_t addr = sp + sp_offset; // the adjusted stack pointer value |
| 659 | |
| 660 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 661 | eRegisterKindGeneric, |
| 662 | LLDB_REGNUM_GENERIC_SP, |
| 663 | sp_offset }; |
| 664 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 665 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 666 | return false; |
| 667 | } |
| 668 | return true; |
| 669 | } |
| 670 | |
| 671 | // An add operation to adjust the SP. |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 672 | // ADD (SP plus register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 673 | bool |
| 674 | EmulateInstructionARM::EmulateAddSPRm (ARMEncoding encoding) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 675 | { |
| 676 | #if 0 |
| 677 | // ARM pseudo code... |
| 678 | if (ConditionPassed()) |
| 679 | { |
| 680 | EncodingSpecificOperations(); |
| 681 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 682 | (result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’); |
| 683 | if d == 15 then |
| 684 | ALUWritePC(result); // setflags is always FALSE here |
| 685 | else |
| 686 | R[d] = result; |
| 687 | if setflags then |
| 688 | APSR.N = result<31>; |
| 689 | APSR.Z = IsZeroBit(result); |
| 690 | APSR.C = carry; |
| 691 | APSR.V = overflow; |
| 692 | } |
| 693 | #endif |
| 694 | |
| 695 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 696 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 697 | if (!success) |
| 698 | return false; |
| 699 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 700 | if (ConditionPassed()) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 701 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 702 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 703 | if (!success) |
| 704 | return false; |
| 705 | uint32_t Rm; // the second operand |
| 706 | switch (encoding) { |
| 707 | case eEncodingT2: |
| 708 | Rm = Bits32(opcode, 6, 3); |
| 709 | break; |
| 710 | default: |
| 711 | return false; |
| 712 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 713 | int32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 714 | if (!success) |
| 715 | return false; |
| 716 | |
| 717 | addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value |
| 718 | |
| 719 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 720 | eRegisterKindGeneric, |
| 721 | LLDB_REGNUM_GENERIC_SP, |
| 722 | reg_value }; |
| 723 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 724 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 725 | return false; |
| 726 | } |
| 727 | return true; |
| 728 | } |
| 729 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 730 | // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine |
| 731 | // at a PC-relative address, and changes instruction set from ARM to Thumb, or |
| 732 | // from Thumb to ARM. |
| 733 | // BLX (immediate) |
| 734 | bool |
| 735 | EmulateInstructionARM::EmulateBLXImmediate (ARMEncoding encoding) |
| 736 | { |
| 737 | #if 0 |
| 738 | // ARM pseudo code... |
| 739 | if (ConditionPassed()) |
| 740 | { |
| 741 | EncodingSpecificOperations(); |
| 742 | if CurrentInstrSet() == InstrSet_ARM then |
| 743 | LR = PC - 4; |
| 744 | else |
| 745 | LR = PC<31:1> : '1'; |
| 746 | if targetInstrSet == InstrSet_ARM then |
| 747 | targetAddress = Align(PC,4) + imm32; |
| 748 | else |
| 749 | targetAddress = PC + imm32; |
| 750 | SelectInstrSet(targetInstrSet); |
| 751 | BranchWritePC(targetAddress); |
| 752 | } |
| 753 | #endif |
| 754 | |
| 755 | bool success = false; |
| 756 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 757 | if (!success) |
| 758 | return false; |
| 759 | |
| 760 | if (ConditionPassed()) |
| 761 | { |
| 762 | EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0}; |
| 763 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 764 | addr_t lr; // next instruction address |
| 765 | addr_t target; // target address |
| 766 | if (!success) |
| 767 | return false; |
| 768 | int32_t imm32; // PC-relative offset |
| 769 | switch (encoding) { |
| 770 | case eEncodingT2: |
| 771 | { |
| 772 | lr = (pc + 4) | 1u; // return address |
| 773 | uint32_t S = Bits32(opcode, 26, 26); |
| 774 | uint32_t imm10H = Bits32(opcode, 25, 16); |
| 775 | uint32_t J1 = Bits32(opcode, 13, 13); |
| 776 | uint32_t J2 = Bits32(opcode, 11, 11); |
| 777 | uint32_t imm10L = Bits32(opcode, 10, 1); |
| 778 | uint32_t I1 = !(J1 ^ S); |
| 779 | uint32_t I2 = !(J2 ^ S); |
| 780 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) + (imm10L << 2); |
| 781 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 782 | target = ((pc + 4) & 0xfffffffc) + imm32; |
| 783 | context.arg1 = 4 + imm32; // signed offset |
| 784 | context.arg2 = eModeARM; // target instruction set |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 785 | break; |
| 786 | } |
| 787 | case eEncodingA2: |
| 788 | lr = pc + 4; // return address |
| 789 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1); |
| 790 | target = pc + 8 + imm32; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 791 | context.arg1 = 8 + imm32; // signed offset |
| 792 | context.arg2 = eModeThumb; // target instruction set |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 793 | break; |
| 794 | default: |
| 795 | return false; |
| 796 | } |
| 797 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 798 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 799 | if (!BranchWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 800 | return false; |
| 801 | } |
| 802 | return true; |
| 803 | } |
| 804 | |
| 805 | // Branch with Link and Exchange (register) calls a subroutine at an address and |
| 806 | // instruction set specified by a register. |
| 807 | // BLX (register) |
| 808 | bool |
| 809 | EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding) |
| 810 | { |
| 811 | #if 0 |
| 812 | // ARM pseudo code... |
| 813 | if (ConditionPassed()) |
| 814 | { |
| 815 | EncodingSpecificOperations(); |
| 816 | target = R[m]; |
| 817 | if CurrentInstrSet() == InstrSet_ARM then |
| 818 | next_instr_addr = PC - 4; |
| 819 | LR = next_instr_addr; |
| 820 | else |
| 821 | next_instr_addr = PC - 2; |
| 822 | LR = next_instr_addr<31:1> : ‘1’; |
| 823 | BXWritePC(target); |
| 824 | } |
| 825 | #endif |
| 826 | |
| 827 | bool success = false; |
| 828 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 829 | if (!success) |
| 830 | return false; |
| 831 | |
| 832 | if (ConditionPassed()) |
| 833 | { |
| 834 | EmulateInstruction::Context context = { EmulateInstruction::eContextAbsoluteBranchRegister, 0, 0, 0}; |
| 835 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 836 | addr_t lr; // next instruction address |
| 837 | addr_t target; // target address |
| 838 | if (!success) |
| 839 | return false; |
| 840 | uint32_t Rm; // the register with the target address |
| 841 | switch (encoding) { |
| 842 | case eEncodingT1: |
| 843 | lr = (pc + 2) | 1u; // return address |
| 844 | Rm = Bits32(opcode, 6, 3); |
| 845 | // if m == 15 then UNPREDICTABLE; |
| 846 | if (Rm == 15) |
| 847 | return false; |
| 848 | target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 849 | break; |
| 850 | case eEncodingA1: |
| 851 | lr = pc + 4; // return address |
| 852 | Rm = Bits32(opcode, 3, 0); |
| 853 | // if m == 15 then UNPREDICTABLE; |
| 854 | if (Rm == 15) |
| 855 | return false; |
| 856 | target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 857 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 858 | default: |
| 859 | return false; |
| 860 | } |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 861 | context.arg0 = eRegisterKindDWARF; |
| 862 | context.arg1 = dwarf_r0 + Rm; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 863 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 864 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 865 | if (!BXWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 866 | return false; |
| 867 | } |
| 868 | return true; |
| 869 | } |
| 870 | |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 871 | // Set r7 to point to some ip offset. |
| 872 | // SUB (immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 873 | bool |
| 874 | EmulateInstructionARM::EmulateSubR7IPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 875 | { |
| 876 | #if 0 |
| 877 | // ARM pseudo code... |
| 878 | if (ConditionPassed()) |
| 879 | { |
| 880 | EncodingSpecificOperations(); |
| 881 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 882 | if d == 15 then // Can only occur for ARM encoding |
| 883 | ALUWritePC(result); // setflags is always FALSE here |
| 884 | else |
| 885 | R[d] = result; |
| 886 | if setflags then |
| 887 | APSR.N = result<31>; |
| 888 | APSR.Z = IsZeroBit(result); |
| 889 | APSR.C = carry; |
| 890 | APSR.V = overflow; |
| 891 | } |
| 892 | #endif |
| 893 | |
| 894 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 895 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 896 | if (!success) |
| 897 | return false; |
| 898 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 899 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 900 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 901 | const addr_t ip = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r12, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 902 | if (!success) |
| 903 | return false; |
| 904 | uint32_t imm32; |
| 905 | switch (encoding) { |
| 906 | case eEncodingA1: |
| 907 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 908 | break; |
| 909 | default: |
| 910 | return false; |
| 911 | } |
| 912 | addr_t ip_offset = imm32; |
| 913 | addr_t addr = ip - ip_offset; // the adjusted ip value |
| 914 | |
| 915 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 916 | eRegisterKindDWARF, |
| 917 | dwarf_r12, |
| 918 | -ip_offset }; |
| 919 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 920 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 921 | return false; |
| 922 | } |
| 923 | return true; |
| 924 | } |
| 925 | |
| 926 | // Set ip to point to some stack offset. |
| 927 | // SUB (SP minus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 928 | bool |
| 929 | EmulateInstructionARM::EmulateSubIPSPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 930 | { |
| 931 | #if 0 |
| 932 | // ARM pseudo code... |
| 933 | if (ConditionPassed()) |
| 934 | { |
| 935 | EncodingSpecificOperations(); |
| 936 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 937 | if d == 15 then // Can only occur for ARM encoding |
| 938 | ALUWritePC(result); // setflags is always FALSE here |
| 939 | else |
| 940 | R[d] = result; |
| 941 | if setflags then |
| 942 | APSR.N = result<31>; |
| 943 | APSR.Z = IsZeroBit(result); |
| 944 | APSR.C = carry; |
| 945 | APSR.V = overflow; |
| 946 | } |
| 947 | #endif |
| 948 | |
| 949 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 950 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 951 | if (!success) |
| 952 | return false; |
| 953 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 954 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 955 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 956 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 957 | if (!success) |
| 958 | return false; |
| 959 | uint32_t imm32; |
| 960 | switch (encoding) { |
| 961 | case eEncodingA1: |
| 962 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 963 | break; |
| 964 | default: |
| 965 | return false; |
| 966 | } |
| 967 | addr_t sp_offset = imm32; |
| 968 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 969 | |
| 970 | EmulateInstruction::Context context = { EmulateInstruction::eContextRegisterPlusOffset, |
| 971 | eRegisterKindGeneric, |
| 972 | LLDB_REGNUM_GENERIC_SP, |
| 973 | -sp_offset }; |
| 974 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 975 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 976 | return false; |
| 977 | } |
| 978 | return true; |
| 979 | } |
| 980 | |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 981 | // A sub operation to adjust the SP -- allocate space for local storage. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 982 | bool |
| 983 | EmulateInstructionARM::EmulateSubSPImmdiate (ARMEncoding encoding) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 984 | { |
| 985 | #if 0 |
| 986 | // ARM pseudo code... |
| 987 | if (ConditionPassed()) |
| 988 | { |
| 989 | EncodingSpecificOperations(); |
| 990 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 991 | if d == 15 then // Can only occur for ARM encoding |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 992 | ALUWritePC(result); // setflags is always FALSE here |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 993 | else |
| 994 | R[d] = result; |
| 995 | if setflags then |
| 996 | APSR.N = result<31>; |
| 997 | APSR.Z = IsZeroBit(result); |
| 998 | APSR.C = carry; |
| 999 | APSR.V = overflow; |
| 1000 | } |
| 1001 | #endif |
| 1002 | |
| 1003 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1004 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1005 | if (!success) |
| 1006 | return false; |
| 1007 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1008 | if (ConditionPassed()) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1009 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1010 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1011 | if (!success) |
| 1012 | return false; |
| 1013 | uint32_t imm32; |
| 1014 | switch (encoding) { |
Johnny Chen | e445502 | 2011-01-26 00:08:59 +0000 | [diff] [blame] | 1015 | case eEncodingT1: |
| 1016 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1017 | case eEncodingT2: |
| 1018 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 1019 | break; |
| 1020 | case eEncodingT3: |
| 1021 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 1022 | break; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1023 | case eEncodingA1: |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1024 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1025 | break; |
| 1026 | default: |
| 1027 | return false; |
| 1028 | } |
| 1029 | addr_t sp_offset = imm32; |
| 1030 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1031 | |
| 1032 | EmulateInstruction::Context context = { EmulateInstruction::eContextAdjustStackPointer, |
| 1033 | eRegisterKindGeneric, |
| 1034 | LLDB_REGNUM_GENERIC_SP, |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1035 | -sp_offset }; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1036 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1037 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1038 | return false; |
| 1039 | } |
| 1040 | return true; |
| 1041 | } |
| 1042 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1043 | // A store operation to the stack that also updates the SP. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1044 | bool |
| 1045 | EmulateInstructionARM::EmulateSTRRtSP (ARMEncoding encoding) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1046 | { |
| 1047 | #if 0 |
| 1048 | // ARM pseudo code... |
| 1049 | if (ConditionPassed()) |
| 1050 | { |
| 1051 | EncodingSpecificOperations(); |
| 1052 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 1053 | address = if index then offset_addr else R[n]; |
| 1054 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 1055 | if wback then R[n] = offset_addr; |
| 1056 | } |
| 1057 | #endif |
| 1058 | |
| 1059 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1060 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1061 | if (!success) |
| 1062 | return false; |
| 1063 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1064 | if (ConditionPassed()) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1065 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1066 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1067 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1068 | if (!success) |
| 1069 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1070 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1071 | uint32_t imm12; |
| 1072 | switch (encoding) { |
| 1073 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 1074 | Rt = Bits32(opcode, 15, 12); |
| 1075 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1076 | break; |
| 1077 | default: |
| 1078 | return false; |
| 1079 | } |
| 1080 | addr_t sp_offset = imm12; |
| 1081 | addr_t addr = sp - sp_offset; |
| 1082 | |
| 1083 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1084 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1085 | { |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1086 | context.arg1 = dwarf_r0 + Rt; // arg1 in the context is the DWARF register number |
| 1087 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1088 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1089 | if (!success) |
| 1090 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1091 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1092 | return false; |
| 1093 | } |
| 1094 | else |
| 1095 | { |
| 1096 | context.arg1 = dwarf_pc; // arg1 in the context is the DWARF register number |
| 1097 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1098 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1099 | if (!success) |
| 1100 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1101 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1102 | return false; |
| 1103 | } |
| 1104 | |
| 1105 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1106 | context.arg0 = eRegisterKindGeneric; |
| 1107 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1108 | context.arg2 = -sp_offset; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1109 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1110 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1111 | return false; |
| 1112 | } |
| 1113 | return true; |
| 1114 | } |
| 1115 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1116 | // Vector Push stores multiple extension registers to the stack. |
| 1117 | // It also updates SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1118 | bool |
| 1119 | EmulateInstructionARM::EmulateVPUSH (ARMEncoding encoding) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1120 | { |
| 1121 | #if 0 |
| 1122 | // ARM pseudo code... |
| 1123 | if (ConditionPassed()) |
| 1124 | { |
| 1125 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1126 | address = SP - imm32; |
| 1127 | SP = SP - imm32; |
| 1128 | if single_regs then |
| 1129 | for r = 0 to regs-1 |
| 1130 | MemA[address,4] = S[d+r]; address = address+4; |
| 1131 | else |
| 1132 | for r = 0 to regs-1 |
| 1133 | // Store as two word-aligned words in the correct order for current endianness. |
| 1134 | MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>; |
| 1135 | MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>; |
| 1136 | address = address+8; |
| 1137 | } |
| 1138 | #endif |
| 1139 | |
| 1140 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1141 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1142 | if (!success) |
| 1143 | return false; |
| 1144 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1145 | if (ConditionPassed()) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1146 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1147 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1148 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1149 | if (!success) |
| 1150 | return false; |
| 1151 | bool single_regs; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1152 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1153 | uint32_t imm32; // stack offset |
| 1154 | uint32_t regs; // number of registers |
| 1155 | switch (encoding) { |
| 1156 | case eEncodingT1: |
| 1157 | case eEncodingA1: |
| 1158 | single_regs = false; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1159 | d = Bits32(opcode, 22, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1160 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1161 | // If UInt(imm8) is odd, see "FSTMX". |
| 1162 | regs = Bits32(opcode, 7, 0) / 2; |
| 1163 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1164 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1165 | return false; |
| 1166 | break; |
| 1167 | case eEncodingT2: |
| 1168 | case eEncodingA2: |
| 1169 | single_regs = true; |
| 1170 | d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22, 22); |
| 1171 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1172 | regs = Bits32(opcode, 7, 0); |
| 1173 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1174 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1175 | return false; |
| 1176 | break; |
| 1177 | default: |
| 1178 | return false; |
| 1179 | } |
| 1180 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1181 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1182 | addr_t sp_offset = imm32; |
| 1183 | addr_t addr = sp - sp_offset; |
| 1184 | uint32_t i; |
| 1185 | |
| 1186 | EmulateInstruction::Context context = { EmulateInstruction::eContextPushRegisterOnStack, eRegisterKindDWARF, 0, 0 }; |
| 1187 | for (i=d; i<regs; ++i) |
| 1188 | { |
| 1189 | context.arg1 = start_reg + i; // arg1 in the context is the DWARF register number |
| 1190 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 1191 | // uint64_t to accommodate 64-bit registers. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1192 | uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, context.arg1, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1193 | if (!success) |
| 1194 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1195 | if (!WriteMemoryUnsigned (context, addr, reg_value, reg_byte_size)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1196 | return false; |
| 1197 | addr += reg_byte_size; |
| 1198 | } |
| 1199 | |
| 1200 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1201 | context.arg0 = eRegisterKindGeneric; |
| 1202 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1203 | context.arg2 = -sp_offset; |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1204 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1205 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1206 | return false; |
| 1207 | } |
| 1208 | return true; |
| 1209 | } |
| 1210 | |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1211 | // Vector Pop loads multiple extension registers from the stack. |
| 1212 | // It also updates SP to point just above the loaded data. |
| 1213 | bool |
| 1214 | EmulateInstructionARM::EmulateVPOP (ARMEncoding encoding) |
| 1215 | { |
| 1216 | #if 0 |
| 1217 | // ARM pseudo code... |
| 1218 | if (ConditionPassed()) |
| 1219 | { |
| 1220 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1221 | address = SP; |
| 1222 | SP = SP + imm32; |
| 1223 | if single_regs then |
| 1224 | for r = 0 to regs-1 |
| 1225 | S[d+r] = MemA[address,4]; address = address+4; |
| 1226 | else |
| 1227 | for r = 0 to regs-1 |
| 1228 | word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; |
| 1229 | // Combine the word-aligned words in the correct order for current endianness. |
| 1230 | D[d+r] = if BigEndian() then word1:word2 else word2:word1; |
| 1231 | } |
| 1232 | #endif |
| 1233 | |
| 1234 | bool success = false; |
| 1235 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1236 | if (!success) |
| 1237 | return false; |
| 1238 | |
| 1239 | if (ConditionPassed()) |
| 1240 | { |
| 1241 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1242 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 1243 | if (!success) |
| 1244 | return false; |
| 1245 | bool single_regs; |
| 1246 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
| 1247 | uint32_t imm32; // stack offset |
| 1248 | uint32_t regs; // number of registers |
| 1249 | switch (encoding) { |
| 1250 | case eEncodingT1: |
| 1251 | case eEncodingA1: |
| 1252 | single_regs = false; |
| 1253 | d = Bits32(opcode, 22, 22) << 4 | Bits32(opcode, 15, 12); |
| 1254 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1255 | // If UInt(imm8) is odd, see "FLDMX". |
| 1256 | regs = Bits32(opcode, 7, 0) / 2; |
| 1257 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1258 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1259 | return false; |
| 1260 | break; |
| 1261 | case eEncodingT2: |
| 1262 | case eEncodingA2: |
| 1263 | single_regs = true; |
| 1264 | d = Bits32(opcode, 15, 12) << 1 | Bits32(opcode, 22, 22); |
| 1265 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1266 | regs = Bits32(opcode, 7, 0); |
| 1267 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1268 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1269 | return false; |
| 1270 | break; |
| 1271 | default: |
| 1272 | return false; |
| 1273 | } |
| 1274 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1275 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1276 | addr_t sp_offset = imm32; |
| 1277 | addr_t addr = sp; |
| 1278 | uint32_t i; |
| 1279 | uint64_t data; // uint64_t to accomodate 64-bit registers. |
| 1280 | |
| 1281 | EmulateInstruction::Context context = { EmulateInstruction::eContextPopRegisterOffStack, eRegisterKindDWARF, 0, 0 }; |
| 1282 | for (i=d; i<regs; ++i) |
| 1283 | { |
| 1284 | context.arg1 = start_reg + i; // arg1 in the context is the DWARF register number |
| 1285 | context.arg2 = addr - sp; // arg2 in the context is the stack pointer offset |
| 1286 | data = ReadMemoryUnsigned(context, addr, reg_byte_size, 0, &success); |
| 1287 | if (!success) |
| 1288 | return false; |
| 1289 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, context.arg1, data)) |
| 1290 | return false; |
| 1291 | addr += reg_byte_size; |
| 1292 | } |
| 1293 | |
| 1294 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1295 | context.arg0 = eRegisterKindGeneric; |
| 1296 | context.arg1 = LLDB_REGNUM_GENERIC_SP; |
| 1297 | context.arg2 = sp_offset; |
| 1298 | |
| 1299 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
| 1300 | return false; |
| 1301 | } |
| 1302 | return true; |
| 1303 | } |
| 1304 | |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1305 | // SVC (previously SWI) |
| 1306 | bool |
| 1307 | EmulateInstructionARM::EmulateSVC (ARMEncoding encoding) |
| 1308 | { |
| 1309 | #if 0 |
| 1310 | // ARM pseudo code... |
| 1311 | if (ConditionPassed()) |
| 1312 | { |
| 1313 | EncodingSpecificOperations(); |
| 1314 | CallSupervisor(); |
| 1315 | } |
| 1316 | #endif |
| 1317 | |
| 1318 | bool success = false; |
| 1319 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1320 | if (!success) |
| 1321 | return false; |
| 1322 | |
| 1323 | if (ConditionPassed()) |
| 1324 | { |
| 1325 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1326 | addr_t lr; // next instruction address |
| 1327 | if (!success) |
| 1328 | return false; |
| 1329 | uint32_t imm32; // the immediate constant |
| 1330 | uint32_t mode; // ARM or Thumb mode |
| 1331 | switch (encoding) { |
| 1332 | case eEncodingT1: |
| 1333 | lr = (pc + 2) | 1u; // return address |
| 1334 | imm32 = Bits32(opcode, 7, 0); |
| 1335 | mode = eModeThumb; |
| 1336 | break; |
| 1337 | case eEncodingA1: |
| 1338 | lr = pc + 4; // return address |
| 1339 | imm32 = Bits32(opcode, 23, 0); |
| 1340 | mode = eModeARM; |
| 1341 | break; |
| 1342 | default: |
| 1343 | return false; |
| 1344 | } |
| 1345 | EmulateInstruction::Context context = { EmulateInstruction::eContextSupervisorCall, mode, imm32, 0}; |
| 1346 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1347 | return false; |
| 1348 | } |
| 1349 | return true; |
| 1350 | } |
| 1351 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1352 | // If Then makes up to four following instructions (the IT block) conditional. |
| 1353 | bool |
| 1354 | EmulateInstructionARM::EmulateIT (ARMEncoding encoding) |
| 1355 | { |
| 1356 | #if 0 |
| 1357 | // ARM pseudo code... |
| 1358 | EncodingSpecificOperations(); |
| 1359 | ITSTATE.IT<7:0> = firstcond:mask; |
| 1360 | #endif |
| 1361 | |
| 1362 | bool success = false; |
| 1363 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1364 | if (!success) |
| 1365 | return false; |
| 1366 | |
| 1367 | m_it_session.InitIT(Bits32(opcode, 7, 0)); |
| 1368 | return true; |
| 1369 | } |
| 1370 | |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1371 | // Branch causes a branch to a target address. |
| 1372 | bool |
| 1373 | EmulateInstructionARM::EmulateB (ARMEncoding encoding) |
| 1374 | { |
| 1375 | #if 0 |
| 1376 | // ARM pseudo code... |
| 1377 | if (ConditionPassed()) |
| 1378 | { |
| 1379 | EncodingSpecificOperations(); |
| 1380 | BranchWritePC(PC + imm32); |
| 1381 | } |
| 1382 | #endif |
| 1383 | |
| 1384 | bool success = false; |
| 1385 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1386 | if (!success) |
| 1387 | return false; |
| 1388 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 1389 | if (ConditionPassed()) |
| 1390 | { |
| 1391 | EmulateInstruction::Context context = { EmulateInstruction::eContextRelativeBranchImmediate, 0, 0, 0}; |
| 1392 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1393 | addr_t target; // target address |
| 1394 | if (!success) |
| 1395 | return false; |
| 1396 | int32_t imm32; // PC-relative offset |
| 1397 | switch (encoding) { |
| 1398 | case eEncodingT1: |
| 1399 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1400 | imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); |
| 1401 | target = pc + 4 + imm32; |
| 1402 | context.arg1 = 4 + imm32; // signed offset |
| 1403 | context.arg2 = eModeThumb; // target instruction set |
| 1404 | break; |
| 1405 | case eEncodingT2: |
| 1406 | imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0)); |
| 1407 | target = pc + 4 + imm32; |
| 1408 | context.arg1 = 4 + imm32; // signed offset |
| 1409 | context.arg2 = eModeThumb; // target instruction set |
| 1410 | break; |
| 1411 | case eEncodingT3: |
| 1412 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1413 | { |
| 1414 | uint32_t S = Bits32(opcode, 26, 26); |
| 1415 | uint32_t imm6 = Bits32(opcode, 21, 16); |
| 1416 | uint32_t J1 = Bits32(opcode, 13, 13); |
| 1417 | uint32_t J2 = Bits32(opcode, 11, 11); |
| 1418 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1419 | uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) + (imm11 << 1); |
| 1420 | imm32 = llvm::SignExtend32<21>(imm21); |
| 1421 | target = pc + 4 + imm32; |
| 1422 | context.arg1 = eModeThumb; // target instruction set |
| 1423 | context.arg2 = 4 + imm32; // signed offset |
| 1424 | break; |
| 1425 | } |
| 1426 | case eEncodingT4: |
| 1427 | { |
| 1428 | uint32_t S = Bits32(opcode, 26, 26); |
| 1429 | uint32_t imm10 = Bits32(opcode, 25, 16); |
| 1430 | uint32_t J1 = Bits32(opcode, 13, 13); |
| 1431 | uint32_t J2 = Bits32(opcode, 11, 11); |
| 1432 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1433 | uint32_t I1 = !(J1 ^ S); |
| 1434 | uint32_t I2 = !(J2 ^ S); |
| 1435 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) + (imm11 << 1); |
| 1436 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1437 | target = pc + 4 + imm32; |
| 1438 | context.arg1 = eModeThumb; // target instruction set |
| 1439 | context.arg2 = 4 + imm32; // signed offset |
| 1440 | break; |
| 1441 | } |
| 1442 | case eEncodingA1: |
| 1443 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
| 1444 | target = pc + 8 + imm32; |
| 1445 | context.arg1 = eModeARM; // target instruction set |
| 1446 | context.arg2 = 8 + imm32; // signed offset |
| 1447 | break; |
| 1448 | default: |
| 1449 | return false; |
| 1450 | } |
| 1451 | if (!BranchWritePC(context, target)) |
| 1452 | return false; |
| 1453 | } |
| 1454 | return true; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1455 | } |
| 1456 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1457 | EmulateInstructionARM::ARMOpcode* |
| 1458 | EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1459 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1460 | static ARMOpcode |
| 1461 | g_arm_opcodes[] = |
| 1462 | { |
| 1463 | //---------------------------------------------------------------------- |
| 1464 | // Prologue instructions |
| 1465 | //---------------------------------------------------------------------- |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1466 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1467 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1468 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
| 1469 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePush, "push <register>" }, |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 1470 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1471 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1472 | { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #<const>" }, |
| 1473 | { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubR7IPImmediate, "sub r7, ip, #<const>"}, |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1474 | // set ip to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1475 | { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMovRdSP, "mov ip, sp" }, |
| 1476 | { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add ip, sp, #<const>" }, |
| 1477 | { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubIPSPImmediate, "sub ip, sp, #<const>"}, |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1478 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1479 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1480 | { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub sp, sp, #<const>"}, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1481 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1482 | // push one register |
| 1483 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1484 | { 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" }, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1485 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1486 | // vector push consecutive extension register(s) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1487 | { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 1488 | { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 1489 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1490 | //---------------------------------------------------------------------- |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1491 | // Epilogue instructions |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1492 | //---------------------------------------------------------------------- |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 1493 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1494 | // To resolve ambiguity, "blx <label>" should come before "bl <label>". |
| 1495 | { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 1496 | { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 1497 | { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1498 | { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
| 1499 | { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePop, "pop <register>"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1500 | { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1501 | { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 1502 | |
| 1503 | //---------------------------------------------------------------------- |
| 1504 | // Supervisor Call (previously Software Interrupt) |
| 1505 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1506 | { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, |
| 1507 | |
| 1508 | //---------------------------------------------------------------------- |
| 1509 | // Branch instructions |
| 1510 | //---------------------------------------------------------------------- |
| 1511 | { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "b #imm24"} |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1512 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1513 | }; |
| 1514 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
| 1515 | |
| 1516 | for (size_t i=0; i<k_num_arm_opcodes; ++i) |
| 1517 | { |
| 1518 | if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) |
| 1519 | return &g_arm_opcodes[i]; |
| 1520 | } |
| 1521 | return NULL; |
| 1522 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1523 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1524 | |
| 1525 | EmulateInstructionARM::ARMOpcode* |
| 1526 | EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 1527 | { |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1528 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1529 | static ARMOpcode |
| 1530 | g_thumb_opcodes[] = |
| 1531 | { |
| 1532 | //---------------------------------------------------------------------- |
| 1533 | // Prologue instructions |
| 1534 | //---------------------------------------------------------------------- |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 1535 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1536 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1537 | { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
| 1538 | { 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <registers>" }, |
| 1539 | { 0xffff0fff, 0xf84d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <register>" }, |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1540 | // move from high register to low register |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1541 | { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovLowHigh, "mov r0-r7, r8-r15" }, |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 1542 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1543 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1544 | { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #imm" }, |
| 1545 | { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdSP, "mov r7, sp" }, |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1546 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1547 | // PC relative load into register (see also EmulateAddSPRm) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1548 | { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRdPCRelative, "ldr <Rd>, [PC, #imm]"}, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1549 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1550 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1551 | { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPRm, "add sp, <Rm>"}, |
| 1552 | { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSubSPImmdiate, "add sp, sp, #imm"}, |
| 1553 | { 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub.w sp, sp, #<const>"}, |
| 1554 | { 0xfbff8f00, 0xf2ad0d00, ARMv6T2|ARMv7, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "subw sp, sp, #imm12"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1555 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1556 | // vector push consecutive extension register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1557 | { 0xffbf0f00, 0xed2d0b00, ARMv6T2|ARMv7, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 1558 | { 0xffbf0f00, 0xed2d0a00, ARMv6T2|ARMv7, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 1559 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1560 | //---------------------------------------------------------------------- |
| 1561 | // Epilogue instructions |
| 1562 | //---------------------------------------------------------------------- |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 1563 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1564 | { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPImmediate, "add sp, #imm"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1565 | { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
| 1566 | // J1 == J2 == 1 |
| 1567 | { 0xf800e801, 0xf000e800, ARMV5_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 1568 | { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
| 1569 | { 0xffff0000, 0xe8bd0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <registers>" }, |
| 1570 | { 0xffff0fff, 0xf85d0d04, ARMv6T2|ARMv7, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <register>" }, |
| 1571 | { 0xffbf0f00, 0xecbd0b00, ARMv6T2|ARMv7, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1572 | { 0xffbf0f00, 0xecbd0a00, ARMv6T2|ARMv7, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 1573 | |
| 1574 | //---------------------------------------------------------------------- |
| 1575 | // Supervisor Call (previously Software Interrupt) |
| 1576 | //---------------------------------------------------------------------- |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1577 | { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, |
| 1578 | |
| 1579 | //---------------------------------------------------------------------- |
| 1580 | // If Then makes up to four following instructions conditional. |
| 1581 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1582 | { 0xffffff00, 0x0000bf00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, |
| 1583 | |
| 1584 | //---------------------------------------------------------------------- |
| 1585 | // Branch instructions |
| 1586 | //---------------------------------------------------------------------- |
| 1587 | // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". |
| 1588 | { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, |
| 1589 | { 0xffff8000, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b #imm11 (outside or last in IT)"}, |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 1590 | { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"}, |
| 1591 | { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"} |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1592 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1593 | }; |
| 1594 | |
| 1595 | const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
| 1596 | for (size_t i=0; i<k_num_thumb_opcodes; ++i) |
| 1597 | { |
| 1598 | if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) |
| 1599 | return &g_thumb_opcodes[i]; |
| 1600 | } |
| 1601 | return NULL; |
| 1602 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1603 | |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 1604 | bool |
| 1605 | EmulateInstructionARM::SetTargetTriple (const ConstString &triple) |
| 1606 | { |
| 1607 | m_arm_isa = 0; |
| 1608 | const char *triple_cstr = triple.GetCString(); |
| 1609 | if (triple_cstr) |
| 1610 | { |
| 1611 | const char *dash = ::strchr (triple_cstr, '-'); |
| 1612 | if (dash) |
| 1613 | { |
| 1614 | std::string arch (triple_cstr, dash); |
| 1615 | const char *arch_cstr = arch.c_str(); |
| 1616 | if (strcasecmp(arch_cstr, "armv4t") == 0) |
| 1617 | m_arm_isa = ARMv4T; |
| 1618 | else if (strcasecmp(arch_cstr, "armv4") == 0) |
| 1619 | m_arm_isa = ARMv4; |
| 1620 | else if (strcasecmp(arch_cstr, "armv5tej") == 0) |
| 1621 | m_arm_isa = ARMv5TEJ; |
| 1622 | else if (strcasecmp(arch_cstr, "armv5te") == 0) |
| 1623 | m_arm_isa = ARMv5TE; |
| 1624 | else if (strcasecmp(arch_cstr, "armv5t") == 0) |
| 1625 | m_arm_isa = ARMv5T; |
| 1626 | else if (strcasecmp(arch_cstr, "armv6k") == 0) |
| 1627 | m_arm_isa = ARMv6K; |
| 1628 | else if (strcasecmp(arch_cstr, "armv6") == 0) |
| 1629 | m_arm_isa = ARMv6; |
| 1630 | else if (strcasecmp(arch_cstr, "armv6t2") == 0) |
| 1631 | m_arm_isa = ARMv6T2; |
| 1632 | else if (strcasecmp(arch_cstr, "armv7") == 0) |
| 1633 | m_arm_isa = ARMv7; |
| 1634 | else if (strcasecmp(arch_cstr, "armv8") == 0) |
| 1635 | m_arm_isa = ARMv8; |
| 1636 | } |
| 1637 | } |
| 1638 | return m_arm_isa != 0; |
| 1639 | } |
| 1640 | |
| 1641 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1642 | bool |
| 1643 | EmulateInstructionARM::ReadInstruction () |
| 1644 | { |
| 1645 | bool success = false; |
| 1646 | m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
| 1647 | if (success) |
| 1648 | { |
| 1649 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 1650 | if (success) |
| 1651 | { |
| 1652 | Context read_inst_context = {eContextReadOpcode, 0, 0}; |
| 1653 | if (m_inst_cpsr & MASK_CPSR_T) |
| 1654 | { |
| 1655 | m_inst_mode = eModeThumb; |
| 1656 | uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success); |
| 1657 | |
| 1658 | if (success) |
| 1659 | { |
| 1660 | if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0)) |
| 1661 | { |
| 1662 | m_inst.opcode_type = eOpcode16; |
| 1663 | m_inst.opcode.inst16 = thumb_opcode; |
| 1664 | } |
| 1665 | else |
| 1666 | { |
| 1667 | m_inst.opcode_type = eOpcode32; |
| 1668 | m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success); |
| 1669 | } |
| 1670 | } |
| 1671 | } |
| 1672 | else |
| 1673 | { |
| 1674 | m_inst_mode = eModeARM; |
| 1675 | m_inst.opcode_type = eOpcode32; |
| 1676 | m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success); |
| 1677 | } |
| 1678 | } |
| 1679 | } |
| 1680 | if (!success) |
| 1681 | { |
| 1682 | m_inst_mode = eModeInvalid; |
| 1683 | m_inst_pc = LLDB_INVALID_ADDRESS; |
| 1684 | } |
| 1685 | return success; |
| 1686 | } |
| 1687 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1688 | bool |
| 1689 | EmulateInstructionARM::ConditionPassed () |
| 1690 | { |
| 1691 | if (m_inst_cpsr == 0) |
| 1692 | return false; |
| 1693 | |
| 1694 | const uint32_t cond = CurrentCond (); |
| 1695 | |
| 1696 | if (cond == UINT32_MAX) |
| 1697 | return false; |
| 1698 | |
| 1699 | bool result = false; |
| 1700 | switch (UnsignedBits(cond, 3, 1)) |
| 1701 | { |
| 1702 | case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break; |
| 1703 | case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break; |
| 1704 | case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break; |
| 1705 | case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break; |
| 1706 | case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break; |
| 1707 | case 5: |
| 1708 | { |
| 1709 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 1710 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 1711 | result = n == v; |
| 1712 | } |
| 1713 | break; |
| 1714 | case 6: |
| 1715 | { |
| 1716 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 1717 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 1718 | result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0); |
| 1719 | } |
| 1720 | break; |
| 1721 | case 7: |
| 1722 | result = true; |
| 1723 | break; |
| 1724 | } |
| 1725 | |
| 1726 | if (cond & 1) |
| 1727 | result = !result; |
| 1728 | return result; |
| 1729 | } |
| 1730 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame^] | 1731 | uint32_t |
| 1732 | EmulateInstructionARM::CurrentCond () |
| 1733 | { |
| 1734 | switch (m_inst_mode) |
| 1735 | { |
| 1736 | default: |
| 1737 | case eModeInvalid: |
| 1738 | break; |
| 1739 | |
| 1740 | case eModeARM: |
| 1741 | return UnsignedBits(m_inst.opcode.inst32, 31, 28); |
| 1742 | |
| 1743 | case eModeThumb: |
| 1744 | // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit |
| 1745 | // 'cond' field of the encoding. |
| 1746 | if (m_inst.opcode_type == eOpcode16 && |
| 1747 | Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d && |
| 1748 | Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f) |
| 1749 | { |
| 1750 | return Bits32(m_inst.opcode.inst16, 11, 7); |
| 1751 | } |
| 1752 | else if (m_inst.opcode_type == eOpcode32 && |
| 1753 | Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e && |
| 1754 | Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 && |
| 1755 | Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 && |
| 1756 | Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d) |
| 1757 | { |
| 1758 | return Bits32(m_inst.opcode.inst32, 25, 22); |
| 1759 | } |
| 1760 | |
| 1761 | return m_it_session.GetCond(); |
| 1762 | } |
| 1763 | return UINT32_MAX; // Return invalid value |
| 1764 | } |
| 1765 | |
| 1766 | // API client must pass in a context whose arg2 field contains the target instruction set. |
| 1767 | bool |
| 1768 | EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr) |
| 1769 | { |
| 1770 | addr_t target; |
| 1771 | |
| 1772 | // Chech the target instruction set. |
| 1773 | switch (context.arg2) |
| 1774 | { |
| 1775 | default: |
| 1776 | assert(0 && "BranchWritePC expects context.arg1 with either eModeARM or eModeThumb"); |
| 1777 | return false; |
| 1778 | case eModeARM: |
| 1779 | target = addr & 0xfffffffc; |
| 1780 | break; |
| 1781 | case eModeThumb: |
| 1782 | target = addr & 0xfffffffe; |
| 1783 | break; |
| 1784 | } |
| 1785 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
| 1786 | return false; |
| 1787 | return false; |
| 1788 | } |
| 1789 | |
| 1790 | // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. |
| 1791 | bool |
| 1792 | EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr) |
| 1793 | { |
| 1794 | addr_t target; |
| 1795 | |
| 1796 | if (BitIsSet(addr, 0)) |
| 1797 | { |
| 1798 | target = addr & 0xfffffffe; |
| 1799 | context.arg2 = eModeThumb; |
| 1800 | } |
| 1801 | else if (BitIsClear(addr, 1)) |
| 1802 | { |
| 1803 | target = addr & 0xfffffffc; |
| 1804 | context.arg2 = eModeARM; |
| 1805 | } |
| 1806 | else |
| 1807 | return false; // address<1:0> == '10' => UNPREDICTABLE |
| 1808 | |
| 1809 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
| 1810 | return false; |
| 1811 | return false; |
| 1812 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1813 | |
| 1814 | bool |
| 1815 | EmulateInstructionARM::EvaluateInstruction () |
| 1816 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1817 | // Advance the ITSTATE bits to their values for the next instruction. |
| 1818 | if (m_inst_mode == eModeThumb && m_it_session.InITBlock()) |
| 1819 | m_it_session.ITAdvance(); |
| 1820 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1821 | return false; |
| 1822 | } |