Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10 | #include <stdlib.h> |
| 11 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 12 | #include "EmulateInstructionARM.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 13 | #include "lldb/Core/ConstString.h" |
| 14 | |
Greg Clayton | f29a08f | 2011-02-09 17:41:27 +0000 | [diff] [blame] | 15 | #include "Plugins/Process/Utility/ARMDefines.h" |
| 16 | #include "Plugins/Process/Utility/ARMUtils.h" |
| 17 | #include "Utility/ARM_DWARF_Registers.h" |
| 18 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 19 | #include "llvm/Support/MathExtras.h" // for SignExtend32 template function |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 20 | // and CountTrailingZeros_32 function |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 21 | |
| 22 | using namespace lldb; |
| 23 | using namespace lldb_private; |
| 24 | |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 25 | static inline uint32_t Align(uint32_t val, uint32_t alignment) |
| 26 | { |
| 27 | return alignment * (val / alignment); |
| 28 | } |
| 29 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 30 | //---------------------------------------------------------------------- |
| 31 | // |
| 32 | // ITSession implementation |
| 33 | // |
| 34 | //---------------------------------------------------------------------- |
| 35 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 36 | // A8.6.50 |
| 37 | // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. |
| 38 | static unsigned short CountITSize(unsigned ITMask) { |
| 39 | // First count the trailing zeros of the IT mask. |
| 40 | unsigned TZ = llvm::CountTrailingZeros_32(ITMask); |
| 41 | if (TZ > 3) |
| 42 | { |
| 43 | printf("Encoding error: IT Mask '0000'\n"); |
| 44 | return 0; |
| 45 | } |
| 46 | return (4 - TZ); |
| 47 | } |
| 48 | |
| 49 | // Init ITState. Note that at least one bit is always 1 in mask. |
| 50 | bool ITSession::InitIT(unsigned short bits7_0) |
| 51 | { |
| 52 | ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); |
| 53 | if (ITCounter == 0) |
| 54 | return false; |
| 55 | |
| 56 | // A8.6.50 IT |
| 57 | unsigned short FirstCond = Bits32(bits7_0, 7, 4); |
| 58 | if (FirstCond == 0xF) |
| 59 | { |
| 60 | printf("Encoding error: IT FirstCond '1111'\n"); |
| 61 | return false; |
| 62 | } |
| 63 | if (FirstCond == 0xE && ITCounter != 1) |
| 64 | { |
| 65 | printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n"); |
| 66 | return false; |
| 67 | } |
| 68 | |
| 69 | ITState = bits7_0; |
| 70 | return true; |
| 71 | } |
| 72 | |
| 73 | // Update ITState if necessary. |
| 74 | void ITSession::ITAdvance() |
| 75 | { |
| 76 | assert(ITCounter); |
| 77 | --ITCounter; |
| 78 | if (ITCounter == 0) |
| 79 | ITState = 0; |
| 80 | else |
| 81 | { |
| 82 | unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; |
| 83 | SetBits32(ITState, 4, 0, NewITState4_0); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | // Return true if we're inside an IT Block. |
| 88 | bool ITSession::InITBlock() |
| 89 | { |
| 90 | return ITCounter != 0; |
| 91 | } |
| 92 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 93 | // Return true if we're the last instruction inside an IT Block. |
| 94 | bool ITSession::LastInITBlock() |
| 95 | { |
| 96 | return ITCounter == 1; |
| 97 | } |
| 98 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 99 | // Get condition bits for the current thumb instruction. |
| 100 | uint32_t ITSession::GetCond() |
| 101 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 102 | if (InITBlock()) |
| 103 | return Bits32(ITState, 7, 4); |
| 104 | else |
| 105 | return COND_AL; |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 106 | } |
| 107 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 108 | // ARM constants used during decoding |
| 109 | #define REG_RD 0 |
| 110 | #define LDM_REGLIST 1 |
| 111 | #define PC_REG 15 |
| 112 | #define PC_REGLIST_BIT 0x8000 |
| 113 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 114 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 115 | #define ARMv4T (1u << 1) |
| 116 | #define ARMv5T (1u << 2) |
| 117 | #define ARMv5TE (1u << 3) |
| 118 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 119 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 120 | #define ARMv6K (1u << 6) |
| 121 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 122 | #define ARMv7 (1u << 8) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 123 | #define ARMv8 (1u << 9) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 124 | #define ARMvAll (0xffffffffu) |
| 125 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 126 | #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 127 | #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 128 | #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 129 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 130 | //---------------------------------------------------------------------- |
| 131 | // |
| 132 | // EmulateInstructionARM implementation |
| 133 | // |
| 134 | //---------------------------------------------------------------------- |
| 135 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 136 | void |
| 137 | EmulateInstructionARM::Initialize () |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 138 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 139 | } |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 140 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 141 | void |
| 142 | EmulateInstructionARM::Terminate () |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 143 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 146 | // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions. |
| 147 | bool |
| 148 | EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address) |
| 149 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 150 | EmulateInstruction::Context context; |
| 151 | context.type = EmulateInstruction::eContextWriteMemoryRandomBits; |
| 152 | context.SetNoArgs (); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 153 | |
| 154 | uint32_t random_data = rand (); |
| 155 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 156 | |
| 157 | if (!WriteMemoryUnsigned (context, address, random_data, addr_byte_size)) |
| 158 | return false; |
| 159 | |
| 160 | return true; |
| 161 | } |
| 162 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 163 | // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions. |
| 164 | bool |
| 165 | EmulateInstructionARM::WriteBits32Unknown (int n) |
| 166 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 167 | EmulateInstruction::Context context; |
| 168 | context.type = EmulateInstruction::eContextWriteRegisterRandomBits; |
| 169 | context.SetNoArgs (); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 170 | |
Johnny Chen | 62ff6f5 | 2011-02-11 18:11:22 +0000 | [diff] [blame] | 171 | bool success; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 172 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 173 | |
| 174 | if (!success) |
| 175 | return false; |
| 176 | |
| 177 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 178 | return false; |
| 179 | |
| 180 | return true; |
| 181 | } |
| 182 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 183 | // Push Multiple Registers stores multiple registers to the stack, storing to |
| 184 | // consecutive memory locations ending just below the address in SP, and updates |
| 185 | // SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 186 | bool |
| 187 | EmulateInstructionARM::EmulatePush (ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 188 | { |
| 189 | #if 0 |
| 190 | // ARM pseudo code... |
| 191 | if (ConditionPassed()) |
| 192 | { |
| 193 | EncodingSpecificOperations(); |
| 194 | NullCheckIfThumbEE(13); |
| 195 | address = SP - 4*BitCount(registers); |
| 196 | |
| 197 | for (i = 0 to 14) |
| 198 | { |
| 199 | if (registers<i> == ’1’) |
| 200 | { |
| 201 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 202 | MemA[address,4] = bits(32) UNKNOWN; |
| 203 | else |
| 204 | MemA[address,4] = R[i]; |
| 205 | address = address + 4; |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | if (registers<15> == ’1’) // Only possible for encoding A1 or A2 |
| 210 | MemA[address,4] = PCStoreValue(); |
| 211 | |
| 212 | SP = SP - 4*BitCount(registers); |
| 213 | } |
| 214 | #endif |
| 215 | |
| 216 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 217 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 218 | if (!success) |
| 219 | return false; |
| 220 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 221 | if (ConditionPassed()) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 222 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 223 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 224 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 225 | if (!success) |
| 226 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 227 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 228 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 229 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 230 | case eEncodingT1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 231 | registers = Bits32(opcode, 7, 0); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 232 | // The M bit represents LR. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 233 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 234 | registers |= (1u << 14); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 235 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 236 | if (BitCount(registers) < 1) |
| 237 | return false; |
| 238 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 239 | case eEncodingT2: |
| 240 | // Ignore bits 15 & 13. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 241 | registers = Bits32(opcode, 15, 0) & ~0xa000; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 242 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 243 | if (BitCount(registers) < 2) |
| 244 | return false; |
| 245 | break; |
| 246 | case eEncodingT3: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 247 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 248 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 249 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 250 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 251 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 252 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 253 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 254 | registers = Bits32(opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 255 | // Instead of return false, let's handle the following case as well, |
| 256 | // which amounts to pushing one reg onto the full descending stacks. |
| 257 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 258 | break; |
| 259 | case eEncodingA2: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 260 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 261 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 262 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 263 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 264 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 265 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 266 | default: |
| 267 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 268 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 269 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 270 | addr_t addr = sp - sp_offset; |
| 271 | uint32_t i; |
| 272 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 273 | EmulateInstruction::Context context; |
| 274 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 275 | Register dwarf_reg; |
| 276 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 277 | for (i=0; i<15; ++i) |
| 278 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 279 | if (BitIsSet (registers, i)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 280 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 281 | dwarf_reg.num = dwarf_r0 + i; |
| 282 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
| 283 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 284 | if (!success) |
| 285 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 286 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 287 | return false; |
| 288 | addr += addr_byte_size; |
| 289 | } |
| 290 | } |
| 291 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 292 | if (BitIsSet (registers, 15)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 293 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 294 | dwarf_reg.num = dwarf_pc; |
| 295 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 296 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 297 | if (!success) |
| 298 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 299 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 300 | return false; |
| 301 | } |
| 302 | |
| 303 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 304 | context.SetImmediateSigned (-sp_offset); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 305 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 306 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 307 | return false; |
| 308 | } |
| 309 | return true; |
| 310 | } |
| 311 | |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 312 | // Pop Multiple Registers loads multiple registers from the stack, loading from |
| 313 | // consecutive memory locations staring at the address in SP, and updates |
| 314 | // SP to point just above the loaded data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 315 | bool |
| 316 | EmulateInstructionARM::EmulatePop (ARMEncoding encoding) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 317 | { |
| 318 | #if 0 |
| 319 | // ARM pseudo code... |
| 320 | if (ConditionPassed()) |
| 321 | { |
| 322 | EncodingSpecificOperations(); NullCheckIfThumbEE(13); |
| 323 | address = SP; |
| 324 | for i = 0 to 14 |
| 325 | if registers<i> == ‘1’ then |
| 326 | R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; |
| 327 | if registers<15> == ‘1’ then |
| 328 | if UnalignedAllowed then |
| 329 | LoadWritePC(MemU[address,4]); |
| 330 | else |
| 331 | LoadWritePC(MemA[address,4]); |
| 332 | if registers<13> == ‘0’ then SP = SP + 4*BitCount(registers); |
| 333 | if registers<13> == ‘1’ then SP = bits(32) UNKNOWN; |
| 334 | } |
| 335 | #endif |
| 336 | |
| 337 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 338 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 339 | if (!success) |
| 340 | return false; |
| 341 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 342 | if (ConditionPassed()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 343 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 344 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 345 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 346 | if (!success) |
| 347 | return false; |
| 348 | uint32_t registers = 0; |
| 349 | uint32_t Rt; // the destination register |
| 350 | switch (encoding) { |
| 351 | case eEncodingT1: |
| 352 | registers = Bits32(opcode, 7, 0); |
| 353 | // The P bit represents PC. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 354 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 355 | registers |= (1u << 15); |
| 356 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 357 | if (BitCount(registers) < 1) |
| 358 | return false; |
| 359 | break; |
| 360 | case eEncodingT2: |
| 361 | // Ignore bit 13. |
| 362 | registers = Bits32(opcode, 15, 0) & ~0x2000; |
| 363 | // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 364 | if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 365 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 366 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 367 | if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock()) |
| 368 | return false; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 369 | break; |
| 370 | case eEncodingT3: |
| 371 | Rt = Bits32(opcode, 15, 12); |
| 372 | // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 373 | if (Rt == 13) |
| 374 | return false; |
| 375 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 376 | return false; |
| 377 | registers = (1u << Rt); |
| 378 | break; |
| 379 | case eEncodingA1: |
| 380 | registers = Bits32(opcode, 15, 0); |
| 381 | // Instead of return false, let's handle the following case as well, |
| 382 | // which amounts to popping one reg from the full descending stacks. |
| 383 | // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; |
| 384 | |
| 385 | // if registers<13> == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 386 | if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 387 | return false; |
| 388 | break; |
| 389 | case eEncodingA2: |
| 390 | Rt = Bits32(opcode, 15, 12); |
| 391 | // if t == 13 then UNPREDICTABLE; |
| 392 | if (Rt == dwarf_sp) |
| 393 | return false; |
| 394 | registers = (1u << Rt); |
| 395 | break; |
| 396 | default: |
| 397 | return false; |
| 398 | } |
| 399 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
| 400 | addr_t addr = sp; |
| 401 | uint32_t i, data; |
| 402 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 403 | EmulateInstruction::Context context; |
| 404 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 405 | Register dwarf_reg; |
| 406 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 407 | for (i=0; i<15; ++i) |
| 408 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 409 | if (BitIsSet (registers, i)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 410 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 411 | dwarf_reg.num = dwarf_r0 + i; |
| 412 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 413 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 414 | if (!success) |
| 415 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 416 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 417 | return false; |
| 418 | addr += addr_byte_size; |
| 419 | } |
| 420 | } |
| 421 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 422 | if (BitIsSet (registers, 15)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 423 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 424 | dwarf_reg.num = dwarf_pc; |
| 425 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 426 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 427 | if (!success) |
| 428 | return false; |
Johnny Chen | f3eaacf | 2011-02-09 19:30:49 +0000 | [diff] [blame] | 429 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 430 | if (!LoadWritePC(context, data, dwarf_reg)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 431 | return false; |
| 432 | addr += addr_byte_size; |
| 433 | } |
| 434 | |
| 435 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 436 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 437 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 438 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 439 | return false; |
| 440 | } |
| 441 | return true; |
| 442 | } |
| 443 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 444 | // Set r7 or ip to point to saved value residing within the stack. |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 445 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 446 | bool |
| 447 | EmulateInstructionARM::EmulateAddRdSPImmediate (ARMEncoding encoding) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 448 | { |
| 449 | #if 0 |
| 450 | // ARM pseudo code... |
| 451 | if (ConditionPassed()) |
| 452 | { |
| 453 | EncodingSpecificOperations(); |
| 454 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 455 | if d == 15 then |
| 456 | ALUWritePC(result); // setflags is always FALSE here |
| 457 | else |
| 458 | R[d] = result; |
| 459 | if setflags then |
| 460 | APSR.N = result<31>; |
| 461 | APSR.Z = IsZeroBit(result); |
| 462 | APSR.C = carry; |
| 463 | APSR.V = overflow; |
| 464 | } |
| 465 | #endif |
| 466 | |
| 467 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 468 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 469 | if (!success) |
| 470 | return false; |
| 471 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 472 | if (ConditionPassed()) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 473 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 474 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 475 | if (!success) |
| 476 | return false; |
| 477 | uint32_t Rd; // the destination register |
| 478 | uint32_t imm32; |
| 479 | switch (encoding) { |
| 480 | case eEncodingT1: |
| 481 | Rd = 7; |
| 482 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) |
| 483 | break; |
| 484 | case eEncodingA1: |
| 485 | Rd = Bits32(opcode, 15, 12); |
| 486 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 487 | break; |
| 488 | default: |
| 489 | return false; |
| 490 | } |
| 491 | addr_t sp_offset = imm32; |
| 492 | addr_t addr = sp + sp_offset; // a pointer to the stack area |
| 493 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 494 | EmulateInstruction::Context context; |
| 495 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 496 | Register sp_reg; |
| 497 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 498 | context.SetRegisterPlusOffset (sp_reg, sp_offset); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 499 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 500 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 501 | return false; |
| 502 | } |
| 503 | return true; |
| 504 | } |
| 505 | |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 506 | // Set r7 or ip to the current stack pointer. |
| 507 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 508 | bool |
| 509 | EmulateInstructionARM::EmulateMovRdSP (ARMEncoding encoding) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 510 | { |
| 511 | #if 0 |
| 512 | // ARM pseudo code... |
| 513 | if (ConditionPassed()) |
| 514 | { |
| 515 | EncodingSpecificOperations(); |
| 516 | result = R[m]; |
| 517 | if d == 15 then |
| 518 | ALUWritePC(result); // setflags is always FALSE here |
| 519 | else |
| 520 | R[d] = result; |
| 521 | if setflags then |
| 522 | APSR.N = result<31>; |
| 523 | APSR.Z = IsZeroBit(result); |
| 524 | // APSR.C unchanged |
| 525 | // APSR.V unchanged |
| 526 | } |
| 527 | #endif |
| 528 | |
| 529 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 530 | //const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 531 | //if (!success) |
| 532 | // return false; |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 533 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 534 | if (ConditionPassed()) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 535 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 536 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 537 | if (!success) |
| 538 | return false; |
| 539 | uint32_t Rd; // the destination register |
| 540 | switch (encoding) { |
| 541 | case eEncodingT1: |
| 542 | Rd = 7; |
| 543 | break; |
| 544 | case eEncodingA1: |
| 545 | Rd = 12; |
| 546 | break; |
| 547 | default: |
| 548 | return false; |
| 549 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 550 | |
| 551 | EmulateInstruction::Context context; |
| 552 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 553 | Register sp_reg; |
| 554 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 555 | context.SetRegisterPlusOffset (sp_reg, 0); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 556 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 557 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 558 | return false; |
| 559 | } |
| 560 | return true; |
| 561 | } |
| 562 | |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 563 | // Move from high register (r8-r15) to low register (r0-r7). |
| 564 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 565 | bool |
| 566 | EmulateInstructionARM::EmulateMovLowHigh (ARMEncoding encoding) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 567 | { |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 568 | return EmulateMovRdRm (encoding); |
| 569 | } |
| 570 | |
| 571 | // Move from register to register. |
| 572 | // MOV (register) |
| 573 | bool |
| 574 | EmulateInstructionARM::EmulateMovRdRm (ARMEncoding encoding) |
| 575 | { |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 576 | #if 0 |
| 577 | // ARM pseudo code... |
| 578 | if (ConditionPassed()) |
| 579 | { |
| 580 | EncodingSpecificOperations(); |
| 581 | result = R[m]; |
| 582 | if d == 15 then |
| 583 | ALUWritePC(result); // setflags is always FALSE here |
| 584 | else |
| 585 | R[d] = result; |
| 586 | if setflags then |
| 587 | APSR.N = result<31>; |
| 588 | APSR.Z = IsZeroBit(result); |
| 589 | // APSR.C unchanged |
| 590 | // APSR.V unchanged |
| 591 | } |
| 592 | #endif |
| 593 | |
| 594 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 595 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 596 | if (!success) |
| 597 | return false; |
| 598 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 599 | if (ConditionPassed()) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 600 | { |
| 601 | uint32_t Rm; // the source register |
| 602 | uint32_t Rd; // the destination register |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 603 | bool setflags; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 604 | switch (encoding) { |
| 605 | case eEncodingT1: |
| 606 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 607 | Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 1); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 608 | setflags = false; |
| 609 | break; |
| 610 | case eEncodingT2: |
| 611 | Rm = Bits32(opcode, 5, 3); |
| 612 | Rd = Bits32(opcode, 2, 1); |
| 613 | setflags = true; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 614 | break; |
| 615 | default: |
| 616 | return false; |
| 617 | } |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 618 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 619 | if (!success) |
| 620 | return false; |
| 621 | |
| 622 | // The context specifies that Rm is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 623 | EmulateInstruction::Context context; |
| 624 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 625 | Register dwarf_reg; |
| 626 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 627 | context.SetRegisterPlusOffset (dwarf_reg, 0); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 628 | |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 629 | if (Rd == 15) |
| 630 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 631 | if (!ALUWritePC (context, reg_value, dwarf_reg)) |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 632 | return false; |
| 633 | } |
| 634 | else |
| 635 | { |
| 636 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, reg_value)) |
| 637 | return false; |
| 638 | if (setflags) |
| 639 | { |
| 640 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 641 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(reg_value, CPSR_N)); |
| 642 | SetBit32(m_new_inst_cpsr, CPSR_Z, reg_value == 0 ? 1 : 0); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 643 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 644 | { |
| 645 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 646 | return false; |
| 647 | } |
| 648 | } |
| 649 | } |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 650 | } |
| 651 | return true; |
| 652 | } |
| 653 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 654 | // Move (immediate) writes an immediate value to the destination register. It |
| 655 | // can optionally update the condition flags based on the value. |
| 656 | // MOV (immediate) |
| 657 | bool |
| 658 | EmulateInstructionARM::EmulateMovRdImm (ARMEncoding encoding) |
| 659 | { |
| 660 | #if 0 |
| 661 | // ARM pseudo code... |
| 662 | if (ConditionPassed()) |
| 663 | { |
| 664 | EncodingSpecificOperations(); |
| 665 | result = imm32; |
| 666 | if d == 15 then // Can only occur for ARM encoding |
| 667 | ALUWritePC(result); // setflags is always FALSE here |
| 668 | else |
| 669 | R[d] = result; |
| 670 | if setflags then |
| 671 | APSR.N = result<31>; |
| 672 | APSR.Z = IsZeroBit(result); |
| 673 | APSR.C = carry; |
| 674 | // APSR.V unchanged |
| 675 | } |
| 676 | #endif |
| 677 | bool success = false; |
| 678 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 679 | if (!success) |
| 680 | return false; |
| 681 | |
| 682 | if (ConditionPassed()) |
| 683 | { |
| 684 | uint32_t Rd; // the destination register |
| 685 | uint32_t imm12; // some intermediate result |
| 686 | uint32_t imm32; // the immediate value to be written to Rd |
| 687 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C. |
| 688 | bool setflags; |
| 689 | switch (encoding) { |
| 690 | case eEncodingT1: |
| 691 | Rd = Bits32(opcode, 11, 8); |
| 692 | setflags = !InITBlock(); |
| 693 | imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) |
| 694 | carry = Bit32(m_inst_cpsr, CPSR_C); |
| 695 | break; |
| 696 | case eEncodingT2: |
| 697 | Rd = Bits32(opcode, 15, 12); |
| 698 | setflags = BitIsSet(opcode, 20); |
| 699 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
| 700 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
Johnny Chen | 9798cfc | 2011-02-14 23:33:58 +0000 | [diff] [blame] | 701 | if (BadReg(Rd)) |
| 702 | return false; |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 703 | break; |
| 704 | default: |
| 705 | return false; |
| 706 | } |
| 707 | uint32_t result = imm32; |
| 708 | |
| 709 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 710 | EmulateInstruction::Context context; |
| 711 | context.type = EmulateInstruction::eContextImmediate; |
| 712 | context.SetNoArgs (); |
| 713 | |
| 714 | Register dummy_reg; |
| 715 | dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0); |
| 716 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 717 | if (Rd == 15) |
| 718 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 719 | if (!ALUWritePC (context, result, dummy_reg)) |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 720 | return false; |
| 721 | } |
| 722 | else |
| 723 | { |
| 724 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 725 | return false; |
| 726 | if (setflags) |
| 727 | { |
| 728 | m_new_inst_cpsr = m_inst_cpsr; |
| 729 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 730 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 731 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 732 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 733 | { |
| 734 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 735 | return false; |
| 736 | } |
| 737 | } |
| 738 | } |
| 739 | } |
| 740 | return true; |
| 741 | } |
| 742 | |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 743 | // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to |
| 744 | // the destination register. It can optionally update the condition flags based |
| 745 | // on the value. |
| 746 | // MVN (immediate) |
| 747 | bool |
| 748 | EmulateInstructionARM::EmulateMvnRdImm (ARMEncoding encoding) |
| 749 | { |
| 750 | #if 0 |
| 751 | // ARM pseudo code... |
| 752 | if (ConditionPassed()) |
| 753 | { |
| 754 | EncodingSpecificOperations(); |
| 755 | result = NOT(imm32); |
| 756 | if d == 15 then // Can only occur for ARM encoding |
| 757 | ALUWritePC(result); // setflags is always FALSE here |
| 758 | else |
| 759 | R[d] = result; |
| 760 | if setflags then |
| 761 | APSR.N = result<31>; |
| 762 | APSR.Z = IsZeroBit(result); |
| 763 | APSR.C = carry; |
| 764 | // APSR.V unchanged |
| 765 | } |
| 766 | #endif |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 767 | bool success = false; |
| 768 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 769 | if (!success) |
| 770 | return false; |
| 771 | |
| 772 | if (ConditionPassed()) |
| 773 | { |
| 774 | uint32_t Rd; // the destination register |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 775 | uint32_t imm12; // the first operand to ThumbExpandImm_C or ARMExpandImm_C |
| 776 | uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C |
| 777 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 778 | bool setflags; |
| 779 | switch (encoding) { |
| 780 | case eEncodingT1: |
| 781 | Rd = Bits32(opcode, 11, 8); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 782 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 783 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 784 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 785 | break; |
| 786 | case eEncodingA1: |
| 787 | Rd = Bits32(opcode, 15, 12); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 788 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 789 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 790 | imm32 = ARMExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 791 | break; |
| 792 | default: |
| 793 | return false; |
| 794 | } |
| 795 | uint32_t result = ~imm32; |
| 796 | |
| 797 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 798 | EmulateInstruction::Context context; |
| 799 | context.type = EmulateInstruction::eContextImmediate; |
| 800 | context.SetNoArgs (); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 801 | |
| 802 | if (Rd == 15) |
| 803 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 804 | Register dummy_reg; |
| 805 | if (!ALUWritePC (context, result, dummy_reg)) |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 806 | return false; |
| 807 | } |
| 808 | else |
| 809 | { |
| 810 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 811 | return false; |
| 812 | if (setflags) |
| 813 | { |
| 814 | m_new_inst_cpsr = m_inst_cpsr; |
| 815 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 816 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 817 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 818 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 819 | { |
| 820 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 821 | return false; |
| 822 | } |
| 823 | } |
| 824 | } |
| 825 | } |
| 826 | return true; |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 827 | } |
| 828 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 829 | // PC relative immediate load into register, possibly followed by ADD (SP plus register). |
| 830 | // LDR (literal) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 831 | bool |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 832 | EmulateInstructionARM::EmulateLDRRtPCRelative (ARMEncoding encoding) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 833 | { |
| 834 | #if 0 |
| 835 | // ARM pseudo code... |
| 836 | if (ConditionPassed()) |
| 837 | { |
| 838 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 839 | base = Align(PC,4); |
| 840 | address = if add then (base + imm32) else (base - imm32); |
| 841 | data = MemU[address,4]; |
| 842 | if t == 15 then |
| 843 | if address<1:0> == ‘00’ then LoadWritePC(data); else UNPREDICTABLE; |
| 844 | elsif UnalignedSupport() || address<1:0> = ‘00’ then |
| 845 | R[t] = data; |
| 846 | else // Can only apply before ARMv7 |
| 847 | if CurrentInstrSet() == InstrSet_ARM then |
| 848 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 849 | else |
| 850 | R[t] = bits(32) UNKNOWN; |
| 851 | } |
| 852 | #endif |
| 853 | |
| 854 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 855 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 856 | if (!success) |
| 857 | return false; |
| 858 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 859 | if (ConditionPassed()) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 860 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 861 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 862 | if (!success) |
| 863 | return false; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 864 | |
| 865 | // PC relative immediate load context |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 866 | EmulateInstruction::Context context; |
| 867 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 868 | Register pc_reg; |
| 869 | pc_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 870 | context.SetRegisterPlusOffset (pc_reg, 0); |
| 871 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 872 | uint32_t Rt; // the destination register |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 873 | uint32_t imm32; // immediate offset from the PC |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 874 | bool add; // +imm32 or -imm32? |
| 875 | addr_t base; // the base address |
| 876 | addr_t address; // the PC relative address |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 877 | uint32_t data; // the literal data value from the PC relative load |
| 878 | switch (encoding) { |
| 879 | case eEncodingT1: |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 880 | Rt = Bits32(opcode, 10, 8); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 881 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 882 | add = true; |
| 883 | base = Align(pc + 4, 4); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 884 | context.SetRegisterPlusOffset (pc_reg, 4 + imm32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 885 | break; |
| 886 | case eEncodingT2: |
| 887 | Rt = Bits32(opcode, 15, 12); |
| 888 | imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); |
| 889 | add = BitIsSet(opcode, 23); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 890 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 891 | return false; |
| 892 | base = Align(pc + 4, 4); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 893 | context.SetRegisterPlusOffset (pc_reg, 4 + imm32); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 894 | break; |
| 895 | default: |
| 896 | return false; |
| 897 | } |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 898 | |
| 899 | if (add) |
| 900 | address = base + imm32; |
| 901 | else |
| 902 | address = base - imm32; |
| 903 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 904 | if (!success) |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 905 | return false; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 906 | |
| 907 | if (Rt == 15) |
| 908 | { |
| 909 | if (Bits32(address, 1, 0) == 0) |
| 910 | { |
| 911 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 912 | if (!LoadWritePC(context, data, pc_reg)) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 913 | return false; |
| 914 | } |
| 915 | else |
| 916 | return false; |
| 917 | } |
| 918 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 919 | { |
| 920 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 921 | return false; |
| 922 | } |
| 923 | else // We don't handle ARM for now. |
| 924 | return false; |
| 925 | |
| 926 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 927 | return false; |
| 928 | } |
| 929 | return true; |
| 930 | } |
| 931 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 932 | // An add operation to adjust the SP. |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 933 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 934 | bool |
| 935 | EmulateInstructionARM::EmulateAddSPImmediate (ARMEncoding encoding) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 936 | { |
| 937 | #if 0 |
| 938 | // ARM pseudo code... |
| 939 | if (ConditionPassed()) |
| 940 | { |
| 941 | EncodingSpecificOperations(); |
| 942 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 943 | if d == 15 then // Can only occur for ARM encoding |
| 944 | ALUWritePC(result); // setflags is always FALSE here |
| 945 | else |
| 946 | R[d] = result; |
| 947 | if setflags then |
| 948 | APSR.N = result<31>; |
| 949 | APSR.Z = IsZeroBit(result); |
| 950 | APSR.C = carry; |
| 951 | APSR.V = overflow; |
| 952 | } |
| 953 | #endif |
| 954 | |
| 955 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 956 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 957 | if (!success) |
| 958 | return false; |
| 959 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 960 | if (ConditionPassed()) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 961 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 962 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 963 | if (!success) |
| 964 | return false; |
| 965 | uint32_t imm32; // the immediate operand |
| 966 | switch (encoding) { |
| 967 | case eEncodingT2: |
| 968 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
| 969 | break; |
| 970 | default: |
| 971 | return false; |
| 972 | } |
| 973 | addr_t sp_offset = imm32; |
| 974 | addr_t addr = sp + sp_offset; // the adjusted stack pointer value |
| 975 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 976 | EmulateInstruction::Context context; |
| 977 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 978 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 979 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 980 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 981 | return false; |
| 982 | } |
| 983 | return true; |
| 984 | } |
| 985 | |
| 986 | // An add operation to adjust the SP. |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 987 | // ADD (SP plus register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 988 | bool |
| 989 | EmulateInstructionARM::EmulateAddSPRm (ARMEncoding encoding) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 990 | { |
| 991 | #if 0 |
| 992 | // ARM pseudo code... |
| 993 | if (ConditionPassed()) |
| 994 | { |
| 995 | EncodingSpecificOperations(); |
| 996 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 997 | (result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’); |
| 998 | if d == 15 then |
| 999 | ALUWritePC(result); // setflags is always FALSE here |
| 1000 | else |
| 1001 | R[d] = result; |
| 1002 | if setflags then |
| 1003 | APSR.N = result<31>; |
| 1004 | APSR.Z = IsZeroBit(result); |
| 1005 | APSR.C = carry; |
| 1006 | APSR.V = overflow; |
| 1007 | } |
| 1008 | #endif |
| 1009 | |
| 1010 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1011 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1012 | if (!success) |
| 1013 | return false; |
| 1014 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1015 | if (ConditionPassed()) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1016 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1017 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1018 | if (!success) |
| 1019 | return false; |
| 1020 | uint32_t Rm; // the second operand |
| 1021 | switch (encoding) { |
| 1022 | case eEncodingT2: |
| 1023 | Rm = Bits32(opcode, 6, 3); |
| 1024 | break; |
| 1025 | default: |
| 1026 | return false; |
| 1027 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1028 | int32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1029 | if (!success) |
| 1030 | return false; |
| 1031 | |
| 1032 | addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value |
| 1033 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1034 | EmulateInstruction::Context context; |
| 1035 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1036 | context.SetImmediateSigned (reg_value); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1037 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1038 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1039 | return false; |
| 1040 | } |
| 1041 | return true; |
| 1042 | } |
| 1043 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1044 | // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine |
| 1045 | // at a PC-relative address, and changes instruction set from ARM to Thumb, or |
| 1046 | // from Thumb to ARM. |
| 1047 | // BLX (immediate) |
| 1048 | bool |
| 1049 | EmulateInstructionARM::EmulateBLXImmediate (ARMEncoding encoding) |
| 1050 | { |
| 1051 | #if 0 |
| 1052 | // ARM pseudo code... |
| 1053 | if (ConditionPassed()) |
| 1054 | { |
| 1055 | EncodingSpecificOperations(); |
| 1056 | if CurrentInstrSet() == InstrSet_ARM then |
| 1057 | LR = PC - 4; |
| 1058 | else |
| 1059 | LR = PC<31:1> : '1'; |
| 1060 | if targetInstrSet == InstrSet_ARM then |
| 1061 | targetAddress = Align(PC,4) + imm32; |
| 1062 | else |
| 1063 | targetAddress = PC + imm32; |
| 1064 | SelectInstrSet(targetInstrSet); |
| 1065 | BranchWritePC(targetAddress); |
| 1066 | } |
| 1067 | #endif |
| 1068 | |
| 1069 | bool success = false; |
| 1070 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1071 | if (!success) |
| 1072 | return false; |
| 1073 | |
| 1074 | if (ConditionPassed()) |
| 1075 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1076 | EmulateInstruction::Context context; |
| 1077 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1078 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1079 | if (!success) |
| 1080 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1081 | addr_t lr; // next instruction address |
| 1082 | addr_t target; // target address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1083 | int32_t imm32; // PC-relative offset |
| 1084 | switch (encoding) { |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1085 | case eEncodingT1: |
| 1086 | { |
| 1087 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1088 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1089 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1090 | uint32_t J1 = Bit32(opcode, 13); |
| 1091 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1092 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1093 | uint32_t I1 = !(J1 ^ S); |
| 1094 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1095 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1096 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1097 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1098 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1099 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1100 | return false; |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1101 | break; |
| 1102 | } |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1103 | case eEncodingT2: |
| 1104 | { |
| 1105 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1106 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1107 | uint32_t imm10H = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1108 | uint32_t J1 = Bit32(opcode, 13); |
| 1109 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1110 | uint32_t imm10L = Bits32(opcode, 10, 1); |
| 1111 | uint32_t I1 = !(J1 ^ S); |
| 1112 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1113 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1114 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1115 | target = Align(pc + 4, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1116 | context.SetModeAndImmediateSigned (eModeARM, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1117 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1118 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1119 | break; |
| 1120 | } |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1121 | case eEncodingA1: |
| 1122 | lr = pc + 4; // return address |
| 1123 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1124 | target = Align(pc + 8, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1125 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1126 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1127 | case eEncodingA2: |
| 1128 | lr = pc + 4; // return address |
| 1129 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1); |
| 1130 | target = pc + 8 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1131 | context.SetModeAndImmediateSigned (eModeThumb, 8 + imm32); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1132 | break; |
| 1133 | default: |
| 1134 | return false; |
| 1135 | } |
| 1136 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1137 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1138 | if (!BranchWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1139 | return false; |
| 1140 | } |
| 1141 | return true; |
| 1142 | } |
| 1143 | |
| 1144 | // Branch with Link and Exchange (register) calls a subroutine at an address and |
| 1145 | // instruction set specified by a register. |
| 1146 | // BLX (register) |
| 1147 | bool |
| 1148 | EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding) |
| 1149 | { |
| 1150 | #if 0 |
| 1151 | // ARM pseudo code... |
| 1152 | if (ConditionPassed()) |
| 1153 | { |
| 1154 | EncodingSpecificOperations(); |
| 1155 | target = R[m]; |
| 1156 | if CurrentInstrSet() == InstrSet_ARM then |
| 1157 | next_instr_addr = PC - 4; |
| 1158 | LR = next_instr_addr; |
| 1159 | else |
| 1160 | next_instr_addr = PC - 2; |
| 1161 | LR = next_instr_addr<31:1> : ‘1’; |
| 1162 | BXWritePC(target); |
| 1163 | } |
| 1164 | #endif |
| 1165 | |
| 1166 | bool success = false; |
| 1167 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1168 | if (!success) |
| 1169 | return false; |
| 1170 | |
| 1171 | if (ConditionPassed()) |
| 1172 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1173 | EmulateInstruction::Context context; |
| 1174 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1175 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1176 | addr_t lr; // next instruction address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1177 | if (!success) |
| 1178 | return false; |
| 1179 | uint32_t Rm; // the register with the target address |
| 1180 | switch (encoding) { |
| 1181 | case eEncodingT1: |
| 1182 | lr = (pc + 2) | 1u; // return address |
| 1183 | Rm = Bits32(opcode, 6, 3); |
| 1184 | // if m == 15 then UNPREDICTABLE; |
| 1185 | if (Rm == 15) |
| 1186 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1187 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1188 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1189 | break; |
| 1190 | case eEncodingA1: |
| 1191 | lr = pc + 4; // return address |
| 1192 | Rm = Bits32(opcode, 3, 0); |
| 1193 | // if m == 15 then UNPREDICTABLE; |
| 1194 | if (Rm == 15) |
| 1195 | return false; |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1196 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1197 | default: |
| 1198 | return false; |
| 1199 | } |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1200 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1201 | if (!success) |
| 1202 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1203 | Register dwarf_reg; |
| 1204 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 1205 | context.SetRegister (dwarf_reg); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1206 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1207 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1208 | if (!BXWritePC(context, target, dwarf_reg)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1209 | return false; |
| 1210 | } |
| 1211 | return true; |
| 1212 | } |
| 1213 | |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1214 | // Branch and Exchange causes a branch to an address and instruction set specified by a register. |
| 1215 | // BX |
| 1216 | bool |
| 1217 | EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding) |
| 1218 | { |
| 1219 | #if 0 |
| 1220 | // ARM pseudo code... |
| 1221 | if (ConditionPassed()) |
| 1222 | { |
| 1223 | EncodingSpecificOperations(); |
| 1224 | BXWritePC(R[m]); |
| 1225 | } |
| 1226 | #endif |
| 1227 | |
| 1228 | bool success = false; |
| 1229 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1230 | if (!success) |
| 1231 | return false; |
| 1232 | |
| 1233 | if (ConditionPassed()) |
| 1234 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1235 | EmulateInstruction::Context context; |
| 1236 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1237 | uint32_t Rm; // the register with the target address |
| 1238 | switch (encoding) { |
| 1239 | case eEncodingT1: |
| 1240 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1241 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1242 | return false; |
| 1243 | break; |
| 1244 | case eEncodingA1: |
| 1245 | Rm = Bits32(opcode, 3, 0); |
| 1246 | break; |
| 1247 | default: |
| 1248 | return false; |
| 1249 | } |
| 1250 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1251 | if (!success) |
| 1252 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1253 | |
| 1254 | Register dwarf_reg; |
| 1255 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 1256 | if (!BXWritePC(context, target, dwarf_reg)) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1257 | return false; |
| 1258 | } |
| 1259 | return true; |
| 1260 | } |
| 1261 | |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1262 | // Set r7 to point to some ip offset. |
| 1263 | // SUB (immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1264 | bool |
| 1265 | EmulateInstructionARM::EmulateSubR7IPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1266 | { |
| 1267 | #if 0 |
| 1268 | // ARM pseudo code... |
| 1269 | if (ConditionPassed()) |
| 1270 | { |
| 1271 | EncodingSpecificOperations(); |
| 1272 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1273 | if d == 15 then // Can only occur for ARM encoding |
| 1274 | ALUWritePC(result); // setflags is always FALSE here |
| 1275 | else |
| 1276 | R[d] = result; |
| 1277 | if setflags then |
| 1278 | APSR.N = result<31>; |
| 1279 | APSR.Z = IsZeroBit(result); |
| 1280 | APSR.C = carry; |
| 1281 | APSR.V = overflow; |
| 1282 | } |
| 1283 | #endif |
| 1284 | |
| 1285 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1286 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1287 | if (!success) |
| 1288 | return false; |
| 1289 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1290 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1291 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1292 | const addr_t ip = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r12, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1293 | if (!success) |
| 1294 | return false; |
| 1295 | uint32_t imm32; |
| 1296 | switch (encoding) { |
| 1297 | case eEncodingA1: |
| 1298 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1299 | break; |
| 1300 | default: |
| 1301 | return false; |
| 1302 | } |
| 1303 | addr_t ip_offset = imm32; |
| 1304 | addr_t addr = ip - ip_offset; // the adjusted ip value |
| 1305 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1306 | EmulateInstruction::Context context; |
| 1307 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1308 | Register dwarf_reg; |
| 1309 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r12); |
| 1310 | context.SetRegisterPlusOffset (dwarf_reg, -ip_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1311 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1312 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1313 | return false; |
| 1314 | } |
| 1315 | return true; |
| 1316 | } |
| 1317 | |
| 1318 | // Set ip to point to some stack offset. |
| 1319 | // SUB (SP minus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1320 | bool |
| 1321 | EmulateInstructionARM::EmulateSubIPSPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1322 | { |
| 1323 | #if 0 |
| 1324 | // ARM pseudo code... |
| 1325 | if (ConditionPassed()) |
| 1326 | { |
| 1327 | EncodingSpecificOperations(); |
| 1328 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1329 | if d == 15 then // Can only occur for ARM encoding |
| 1330 | ALUWritePC(result); // setflags is always FALSE here |
| 1331 | else |
| 1332 | R[d] = result; |
| 1333 | if setflags then |
| 1334 | APSR.N = result<31>; |
| 1335 | APSR.Z = IsZeroBit(result); |
| 1336 | APSR.C = carry; |
| 1337 | APSR.V = overflow; |
| 1338 | } |
| 1339 | #endif |
| 1340 | |
| 1341 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1342 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1343 | if (!success) |
| 1344 | return false; |
| 1345 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1346 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1347 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1348 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1349 | if (!success) |
| 1350 | return false; |
| 1351 | uint32_t imm32; |
| 1352 | switch (encoding) { |
| 1353 | case eEncodingA1: |
| 1354 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1355 | break; |
| 1356 | default: |
| 1357 | return false; |
| 1358 | } |
| 1359 | addr_t sp_offset = imm32; |
| 1360 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1361 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1362 | EmulateInstruction::Context context; |
| 1363 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1364 | Register dwarf_reg; |
| 1365 | dwarf_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 1366 | context.SetRegisterPlusOffset (dwarf_reg, -sp_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1367 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1368 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1369 | return false; |
| 1370 | } |
| 1371 | return true; |
| 1372 | } |
| 1373 | |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1374 | // A sub operation to adjust the SP -- allocate space for local storage. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1375 | bool |
| 1376 | EmulateInstructionARM::EmulateSubSPImmdiate (ARMEncoding encoding) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1377 | { |
| 1378 | #if 0 |
| 1379 | // ARM pseudo code... |
| 1380 | if (ConditionPassed()) |
| 1381 | { |
| 1382 | EncodingSpecificOperations(); |
| 1383 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1384 | if d == 15 then // Can only occur for ARM encoding |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1385 | ALUWritePC(result); // setflags is always FALSE here |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1386 | else |
| 1387 | R[d] = result; |
| 1388 | if setflags then |
| 1389 | APSR.N = result<31>; |
| 1390 | APSR.Z = IsZeroBit(result); |
| 1391 | APSR.C = carry; |
| 1392 | APSR.V = overflow; |
| 1393 | } |
| 1394 | #endif |
| 1395 | |
| 1396 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1397 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1398 | if (!success) |
| 1399 | return false; |
| 1400 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1401 | if (ConditionPassed()) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1402 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1403 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1404 | if (!success) |
| 1405 | return false; |
| 1406 | uint32_t imm32; |
| 1407 | switch (encoding) { |
Johnny Chen | e445502 | 2011-01-26 00:08:59 +0000 | [diff] [blame] | 1408 | case eEncodingT1: |
| 1409 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1410 | case eEncodingT2: |
| 1411 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 1412 | break; |
| 1413 | case eEncodingT3: |
| 1414 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 1415 | break; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1416 | case eEncodingA1: |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1417 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1418 | break; |
| 1419 | default: |
| 1420 | return false; |
| 1421 | } |
| 1422 | addr_t sp_offset = imm32; |
| 1423 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1424 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1425 | EmulateInstruction::Context context; |
| 1426 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1427 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1428 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1429 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1430 | return false; |
| 1431 | } |
| 1432 | return true; |
| 1433 | } |
| 1434 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1435 | // A store operation to the stack that also updates the SP. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1436 | bool |
| 1437 | EmulateInstructionARM::EmulateSTRRtSP (ARMEncoding encoding) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1438 | { |
| 1439 | #if 0 |
| 1440 | // ARM pseudo code... |
| 1441 | if (ConditionPassed()) |
| 1442 | { |
| 1443 | EncodingSpecificOperations(); |
| 1444 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 1445 | address = if index then offset_addr else R[n]; |
| 1446 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 1447 | if wback then R[n] = offset_addr; |
| 1448 | } |
| 1449 | #endif |
| 1450 | |
| 1451 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1452 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1453 | if (!success) |
| 1454 | return false; |
| 1455 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1456 | if (ConditionPassed()) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1457 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1458 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1459 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1460 | if (!success) |
| 1461 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1462 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1463 | uint32_t imm12; |
| 1464 | switch (encoding) { |
| 1465 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 1466 | Rt = Bits32(opcode, 15, 12); |
| 1467 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1468 | break; |
| 1469 | default: |
| 1470 | return false; |
| 1471 | } |
| 1472 | addr_t sp_offset = imm12; |
| 1473 | addr_t addr = sp - sp_offset; |
| 1474 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1475 | EmulateInstruction::Context context; |
| 1476 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 1477 | Register dwarf_reg; |
| 1478 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1479 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1480 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1481 | dwarf_reg.num = dwarf_r0 + Rt; |
| 1482 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
| 1483 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1484 | if (!success) |
| 1485 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1486 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1487 | return false; |
| 1488 | } |
| 1489 | else |
| 1490 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1491 | dwarf_reg.num = dwarf_pc; |
| 1492 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1493 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1494 | if (!success) |
| 1495 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1496 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1497 | return false; |
| 1498 | } |
| 1499 | |
| 1500 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1501 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1502 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1503 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1504 | return false; |
| 1505 | } |
| 1506 | return true; |
| 1507 | } |
| 1508 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1509 | // Vector Push stores multiple extension registers to the stack. |
| 1510 | // It also updates SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1511 | bool |
| 1512 | EmulateInstructionARM::EmulateVPUSH (ARMEncoding encoding) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1513 | { |
| 1514 | #if 0 |
| 1515 | // ARM pseudo code... |
| 1516 | if (ConditionPassed()) |
| 1517 | { |
| 1518 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1519 | address = SP - imm32; |
| 1520 | SP = SP - imm32; |
| 1521 | if single_regs then |
| 1522 | for r = 0 to regs-1 |
| 1523 | MemA[address,4] = S[d+r]; address = address+4; |
| 1524 | else |
| 1525 | for r = 0 to regs-1 |
| 1526 | // Store as two word-aligned words in the correct order for current endianness. |
| 1527 | MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>; |
| 1528 | MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>; |
| 1529 | address = address+8; |
| 1530 | } |
| 1531 | #endif |
| 1532 | |
| 1533 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1534 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1535 | if (!success) |
| 1536 | return false; |
| 1537 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1538 | if (ConditionPassed()) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1539 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1540 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1541 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1542 | if (!success) |
| 1543 | return false; |
| 1544 | bool single_regs; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1545 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1546 | uint32_t imm32; // stack offset |
| 1547 | uint32_t regs; // number of registers |
| 1548 | switch (encoding) { |
| 1549 | case eEncodingT1: |
| 1550 | case eEncodingA1: |
| 1551 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1552 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1553 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1554 | // If UInt(imm8) is odd, see "FSTMX". |
| 1555 | regs = Bits32(opcode, 7, 0) / 2; |
| 1556 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1557 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1558 | return false; |
| 1559 | break; |
| 1560 | case eEncodingT2: |
| 1561 | case eEncodingA2: |
| 1562 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1563 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1564 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1565 | regs = Bits32(opcode, 7, 0); |
| 1566 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1567 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1568 | return false; |
| 1569 | break; |
| 1570 | default: |
| 1571 | return false; |
| 1572 | } |
| 1573 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1574 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1575 | addr_t sp_offset = imm32; |
| 1576 | addr_t addr = sp - sp_offset; |
| 1577 | uint32_t i; |
| 1578 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1579 | EmulateInstruction::Context context; |
| 1580 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 1581 | Register dwarf_reg; |
| 1582 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1583 | for (i=d; i<regs; ++i) |
| 1584 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1585 | dwarf_reg.num = start_reg + i; |
| 1586 | context.SetRegisterPlusOffset ( dwarf_reg, addr - sp); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1587 | // uint64_t to accommodate 64-bit registers. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1588 | uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1589 | if (!success) |
| 1590 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1591 | if (!WriteMemoryUnsigned (context, addr, reg_value, reg_byte_size)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1592 | return false; |
| 1593 | addr += reg_byte_size; |
| 1594 | } |
| 1595 | |
| 1596 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1597 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1598 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1599 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1600 | return false; |
| 1601 | } |
| 1602 | return true; |
| 1603 | } |
| 1604 | |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1605 | // Vector Pop loads multiple extension registers from the stack. |
| 1606 | // It also updates SP to point just above the loaded data. |
| 1607 | bool |
| 1608 | EmulateInstructionARM::EmulateVPOP (ARMEncoding encoding) |
| 1609 | { |
| 1610 | #if 0 |
| 1611 | // ARM pseudo code... |
| 1612 | if (ConditionPassed()) |
| 1613 | { |
| 1614 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1615 | address = SP; |
| 1616 | SP = SP + imm32; |
| 1617 | if single_regs then |
| 1618 | for r = 0 to regs-1 |
| 1619 | S[d+r] = MemA[address,4]; address = address+4; |
| 1620 | else |
| 1621 | for r = 0 to regs-1 |
| 1622 | word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; |
| 1623 | // Combine the word-aligned words in the correct order for current endianness. |
| 1624 | D[d+r] = if BigEndian() then word1:word2 else word2:word1; |
| 1625 | } |
| 1626 | #endif |
| 1627 | |
| 1628 | bool success = false; |
| 1629 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1630 | if (!success) |
| 1631 | return false; |
| 1632 | |
| 1633 | if (ConditionPassed()) |
| 1634 | { |
| 1635 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1636 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 1637 | if (!success) |
| 1638 | return false; |
| 1639 | bool single_regs; |
| 1640 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
| 1641 | uint32_t imm32; // stack offset |
| 1642 | uint32_t regs; // number of registers |
| 1643 | switch (encoding) { |
| 1644 | case eEncodingT1: |
| 1645 | case eEncodingA1: |
| 1646 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1647 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1648 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1649 | // If UInt(imm8) is odd, see "FLDMX". |
| 1650 | regs = Bits32(opcode, 7, 0) / 2; |
| 1651 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1652 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1653 | return false; |
| 1654 | break; |
| 1655 | case eEncodingT2: |
| 1656 | case eEncodingA2: |
| 1657 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1658 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1659 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1660 | regs = Bits32(opcode, 7, 0); |
| 1661 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1662 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1663 | return false; |
| 1664 | break; |
| 1665 | default: |
| 1666 | return false; |
| 1667 | } |
| 1668 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1669 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1670 | addr_t sp_offset = imm32; |
| 1671 | addr_t addr = sp; |
| 1672 | uint32_t i; |
| 1673 | uint64_t data; // uint64_t to accomodate 64-bit registers. |
| 1674 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1675 | EmulateInstruction::Context context; |
| 1676 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 1677 | Register dwarf_reg; |
| 1678 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1679 | for (i=d; i<regs; ++i) |
| 1680 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1681 | dwarf_reg.num = start_reg + i; |
| 1682 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1683 | data = ReadMemoryUnsigned(context, addr, reg_byte_size, 0, &success); |
| 1684 | if (!success) |
| 1685 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1686 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1687 | return false; |
| 1688 | addr += reg_byte_size; |
| 1689 | } |
| 1690 | |
| 1691 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1692 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1693 | |
| 1694 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
| 1695 | return false; |
| 1696 | } |
| 1697 | return true; |
| 1698 | } |
| 1699 | |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1700 | // SVC (previously SWI) |
| 1701 | bool |
| 1702 | EmulateInstructionARM::EmulateSVC (ARMEncoding encoding) |
| 1703 | { |
| 1704 | #if 0 |
| 1705 | // ARM pseudo code... |
| 1706 | if (ConditionPassed()) |
| 1707 | { |
| 1708 | EncodingSpecificOperations(); |
| 1709 | CallSupervisor(); |
| 1710 | } |
| 1711 | #endif |
| 1712 | |
| 1713 | bool success = false; |
| 1714 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1715 | if (!success) |
| 1716 | return false; |
| 1717 | |
| 1718 | if (ConditionPassed()) |
| 1719 | { |
| 1720 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1721 | addr_t lr; // next instruction address |
| 1722 | if (!success) |
| 1723 | return false; |
| 1724 | uint32_t imm32; // the immediate constant |
| 1725 | uint32_t mode; // ARM or Thumb mode |
| 1726 | switch (encoding) { |
| 1727 | case eEncodingT1: |
| 1728 | lr = (pc + 2) | 1u; // return address |
| 1729 | imm32 = Bits32(opcode, 7, 0); |
| 1730 | mode = eModeThumb; |
| 1731 | break; |
| 1732 | case eEncodingA1: |
| 1733 | lr = pc + 4; // return address |
| 1734 | imm32 = Bits32(opcode, 23, 0); |
| 1735 | mode = eModeARM; |
| 1736 | break; |
| 1737 | default: |
| 1738 | return false; |
| 1739 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1740 | |
| 1741 | EmulateInstruction::Context context; |
| 1742 | context.type = EmulateInstruction::eContextSupervisorCall; |
| 1743 | context.SetModeAndImmediate (mode, imm32); |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1744 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1745 | return false; |
| 1746 | } |
| 1747 | return true; |
| 1748 | } |
| 1749 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1750 | // If Then makes up to four following instructions (the IT block) conditional. |
| 1751 | bool |
| 1752 | EmulateInstructionARM::EmulateIT (ARMEncoding encoding) |
| 1753 | { |
| 1754 | #if 0 |
| 1755 | // ARM pseudo code... |
| 1756 | EncodingSpecificOperations(); |
| 1757 | ITSTATE.IT<7:0> = firstcond:mask; |
| 1758 | #endif |
| 1759 | |
| 1760 | bool success = false; |
| 1761 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1762 | if (!success) |
| 1763 | return false; |
| 1764 | |
| 1765 | m_it_session.InitIT(Bits32(opcode, 7, 0)); |
| 1766 | return true; |
| 1767 | } |
| 1768 | |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1769 | // Branch causes a branch to a target address. |
| 1770 | bool |
| 1771 | EmulateInstructionARM::EmulateB (ARMEncoding encoding) |
| 1772 | { |
| 1773 | #if 0 |
| 1774 | // ARM pseudo code... |
| 1775 | if (ConditionPassed()) |
| 1776 | { |
| 1777 | EncodingSpecificOperations(); |
| 1778 | BranchWritePC(PC + imm32); |
| 1779 | } |
| 1780 | #endif |
| 1781 | |
| 1782 | bool success = false; |
| 1783 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1784 | if (!success) |
| 1785 | return false; |
| 1786 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1787 | if (ConditionPassed()) |
| 1788 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1789 | EmulateInstruction::Context context; |
| 1790 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1791 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1792 | if (!success) |
| 1793 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1794 | addr_t target; // target address |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1795 | int32_t imm32; // PC-relative offset |
| 1796 | switch (encoding) { |
| 1797 | case eEncodingT1: |
| 1798 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1799 | imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); |
| 1800 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1801 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1802 | break; |
| 1803 | case eEncodingT2: |
| 1804 | imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0)); |
| 1805 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1806 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1807 | break; |
| 1808 | case eEncodingT3: |
| 1809 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1810 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1811 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1812 | uint32_t imm6 = Bits32(opcode, 21, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1813 | uint32_t J1 = Bit32(opcode, 13); |
| 1814 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1815 | uint32_t imm11 = Bits32(opcode, 10, 0); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1816 | uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1817 | imm32 = llvm::SignExtend32<21>(imm21); |
| 1818 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1819 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1820 | break; |
| 1821 | } |
| 1822 | case eEncodingT4: |
| 1823 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1824 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1825 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1826 | uint32_t J1 = Bit32(opcode, 13); |
| 1827 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1828 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1829 | uint32_t I1 = !(J1 ^ S); |
| 1830 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1831 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1832 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1833 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1834 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1835 | break; |
| 1836 | } |
| 1837 | case eEncodingA1: |
| 1838 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
| 1839 | target = pc + 8 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1840 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1841 | break; |
| 1842 | default: |
| 1843 | return false; |
| 1844 | } |
| 1845 | if (!BranchWritePC(context, target)) |
| 1846 | return false; |
| 1847 | } |
| 1848 | return true; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1849 | } |
| 1850 | |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1851 | // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with |
| 1852 | // zero and conditionally branch forward a constant value. They do not affect the condition flags. |
| 1853 | // CBNZ, CBZ |
| 1854 | bool |
| 1855 | EmulateInstructionARM::EmulateCB (ARMEncoding encoding) |
| 1856 | { |
| 1857 | #if 0 |
| 1858 | // ARM pseudo code... |
| 1859 | EncodingSpecificOperations(); |
| 1860 | if nonzero ^ IsZero(R[n]) then |
| 1861 | BranchWritePC(PC + imm32); |
| 1862 | #endif |
| 1863 | |
| 1864 | bool success = false; |
| 1865 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1866 | if (!success) |
| 1867 | return false; |
| 1868 | |
| 1869 | // Read the register value from the operand register Rn. |
| 1870 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Bits32(opcode, 2, 0), 0, &success); |
| 1871 | if (!success) |
| 1872 | return false; |
| 1873 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1874 | EmulateInstruction::Context context; |
| 1875 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1876 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1877 | if (!success) |
| 1878 | return false; |
| 1879 | |
| 1880 | addr_t target; // target address |
| 1881 | uint32_t imm32; // PC-relative offset to branch forward |
| 1882 | bool nonzero; |
| 1883 | switch (encoding) { |
| 1884 | case eEncodingT1: |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1885 | imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1886 | nonzero = BitIsSet(opcode, 11); |
| 1887 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1888 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1889 | break; |
| 1890 | default: |
| 1891 | return false; |
| 1892 | } |
| 1893 | if (nonzero ^ (reg_val == 0)) |
| 1894 | if (!BranchWritePC(context, target)) |
| 1895 | return false; |
| 1896 | |
| 1897 | return true; |
| 1898 | } |
| 1899 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1900 | // ADD <Rdn>, <Rm> |
| 1901 | // where <Rdn> the destination register is also the first operand register |
| 1902 | // and <Rm> is the second operand register. |
| 1903 | bool |
| 1904 | EmulateInstructionARM::EmulateAddRdnRm (ARMEncoding encoding) |
| 1905 | { |
| 1906 | #if 0 |
| 1907 | // ARM pseudo code... |
| 1908 | if ConditionPassed() then |
| 1909 | EncodingSpecificOperations(); |
| 1910 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 1911 | (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); |
| 1912 | if d == 15 then |
| 1913 | ALUWritePC(result); // setflags is always FALSE here |
| 1914 | else |
| 1915 | R[d] = result; |
| 1916 | if setflags then |
| 1917 | APSR.N = result<31>; |
| 1918 | APSR.Z = IsZeroBit(result); |
| 1919 | APSR.C = carry; |
| 1920 | APSR.V = overflow; |
| 1921 | #endif |
| 1922 | |
| 1923 | bool success = false; |
| 1924 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1925 | if (!success) |
| 1926 | return false; |
| 1927 | |
| 1928 | if (ConditionPassed()) |
| 1929 | { |
| 1930 | uint32_t Rd, Rn, Rm; |
| 1931 | //bool setflags = false; |
| 1932 | switch (encoding) |
| 1933 | { |
| 1934 | case eEncodingT2: |
| 1935 | // setflags = FALSE |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1936 | Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1937 | Rm = Bits32(opcode, 6, 3); |
| 1938 | if (Rn == 15 && Rm == 15) |
| 1939 | return false; |
| 1940 | break; |
| 1941 | default: |
| 1942 | return false; |
| 1943 | } |
| 1944 | |
| 1945 | int32_t result, val1, val2; |
| 1946 | // Read the first operand. |
| 1947 | if (Rn == 15) |
| 1948 | val1 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1949 | else |
| 1950 | val1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 1951 | if (!success) |
| 1952 | return false; |
| 1953 | |
| 1954 | // Read the second operand. |
| 1955 | if (Rm == 15) |
| 1956 | val2 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1957 | else |
| 1958 | val2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1959 | if (!success) |
| 1960 | return false; |
| 1961 | |
| 1962 | result = val1 + val2; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1963 | |
| 1964 | EmulateInstruction::Context context; |
| 1965 | context.type = EmulateInstruction::eContextImmediate; |
| 1966 | context.SetNoArgs (); |
| 1967 | Register dummy_reg; |
| 1968 | dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1969 | |
| 1970 | if (Rd == 15) |
| 1971 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1972 | if (!ALUWritePC (context, result, dummy_reg)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1973 | return false; |
| 1974 | } |
| 1975 | else |
| 1976 | { |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 1977 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1978 | return false; |
| 1979 | } |
| 1980 | } |
| 1981 | return true; |
| 1982 | } |
| 1983 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 1984 | // CMP (immediate) |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 1985 | bool |
| 1986 | EmulateInstructionARM::EmulateCmpRnImm (ARMEncoding encoding) |
| 1987 | { |
| 1988 | #if 0 |
| 1989 | // ARM pseudo code... |
| 1990 | if ConditionPassed() then |
| 1991 | EncodingSpecificOperations(); |
| 1992 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 1993 | APSR.N = result<31>; |
| 1994 | APSR.Z = IsZeroBit(result); |
| 1995 | APSR.C = carry; |
| 1996 | APSR.V = overflow; |
| 1997 | #endif |
| 1998 | |
| 1999 | bool success = false; |
| 2000 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2001 | if (!success) |
| 2002 | return false; |
| 2003 | |
| 2004 | uint32_t Rn; // the first operand |
| 2005 | uint32_t imm32; // the immediate value to be compared with |
| 2006 | switch (encoding) { |
| 2007 | case eEncodingT1: |
| 2008 | Rn = Bits32(opcode, 10, 8); |
| 2009 | imm32 = Bits32(opcode, 7, 0); |
| 2010 | break; |
| 2011 | default: |
| 2012 | return false; |
| 2013 | } |
| 2014 | // Read the register value from the operand register Rn. |
| 2015 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2016 | if (!success) |
| 2017 | return false; |
| 2018 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2019 | EmulateInstruction::Context context; |
| 2020 | context.type = EmulateInstruction::eContextImmediate; |
| 2021 | context.SetNoArgs (); |
| 2022 | |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2023 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 2024 | m_new_inst_cpsr = m_inst_cpsr; |
| 2025 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2026 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2027 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2028 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2029 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2030 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2031 | EmulateInstruction::Context context; |
| 2032 | context.type = EmulateInstruction::eContextImmediate; |
| 2033 | context.SetNoArgs (); |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2034 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2035 | return false; |
| 2036 | } |
| 2037 | return true; |
| 2038 | } |
| 2039 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2040 | // CMP (register) |
| 2041 | bool |
| 2042 | EmulateInstructionARM::EmulateCmpRnRm (ARMEncoding encoding) |
| 2043 | { |
| 2044 | #if 0 |
| 2045 | // ARM pseudo code... |
| 2046 | if ConditionPassed() then |
| 2047 | EncodingSpecificOperations(); |
| 2048 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2049 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); |
| 2050 | APSR.N = result<31>; |
| 2051 | APSR.Z = IsZeroBit(result); |
| 2052 | APSR.C = carry; |
| 2053 | APSR.V = overflow; |
| 2054 | #endif |
| 2055 | |
| 2056 | bool success = false; |
| 2057 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2058 | if (!success) |
| 2059 | return false; |
| 2060 | |
| 2061 | uint32_t Rn; // the first operand |
| 2062 | uint32_t Rm; // the second operand |
| 2063 | switch (encoding) { |
| 2064 | case eEncodingT1: |
| 2065 | Rn = Bits32(opcode, 2, 0); |
| 2066 | Rm = Bits32(opcode, 5, 3); |
| 2067 | break; |
| 2068 | case eEncodingT2: |
| 2069 | Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
| 2070 | Rm = Bits32(opcode, 6, 3); |
| 2071 | if (Rn < 8 && Rm < 8) |
| 2072 | return false; |
| 2073 | if (Rn == 15 || Rm == 15) |
| 2074 | return false; |
| 2075 | break; |
| 2076 | default: |
| 2077 | return false; |
| 2078 | } |
| 2079 | // Read the register value from register Rn. |
| 2080 | uint32_t reg_val1 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2081 | if (!success) |
| 2082 | return false; |
| 2083 | // Read the register value from register Rm. |
| 2084 | // The register value is not being shifted since we don't handle ARM for now. |
| 2085 | uint32_t reg_val2 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 2086 | if (!success) |
| 2087 | return false; |
| 2088 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2089 | EmulateInstruction::Context context; |
| 2090 | context.type = EmulateInstruction::eContextImmediate; |
| 2091 | context.SetNoArgs(); |
| 2092 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2093 | AddWithCarryResult res = AddWithCarry(reg_val1, reg_val2, 1); |
| 2094 | m_new_inst_cpsr = m_inst_cpsr; |
| 2095 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2096 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2097 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2098 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2099 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2100 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2101 | EmulateInstruction::Context context; |
| 2102 | context.type = EmulateInstruction::eContextImmediate; |
| 2103 | context.SetNoArgs (); |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2104 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2105 | return false; |
| 2106 | } |
| 2107 | return true; |
| 2108 | } |
| 2109 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2110 | // LDM loads multiple registers from consecutive memory locations, using an |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2111 | // address from a base register. Optionally the address just above the highest of those locations |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2112 | // can be written back to the base register. |
| 2113 | bool |
| 2114 | EmulateInstructionARM::EmulateLDM (ARMEncoding encoding) |
| 2115 | { |
| 2116 | #if 0 |
| 2117 | // ARM pseudo code... |
| 2118 | if ConditionPassed() |
| 2119 | EncodingSpecificOperations(); NullCheckIfThumbEE (n); |
| 2120 | address = R[n]; |
| 2121 | |
| 2122 | for i = 0 to 14 |
| 2123 | if registers<i> == '1' then |
| 2124 | R[i] = MemA[address, 4]; address = address + 4; |
| 2125 | if registers<15> == '1' then |
| 2126 | LoadWritePC (MemA[address, 4]); |
| 2127 | |
| 2128 | if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers); |
| 2129 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2130 | |
| 2131 | #endif |
| 2132 | |
| 2133 | bool success = false; |
| 2134 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2135 | if (!success) |
| 2136 | return false; |
| 2137 | |
| 2138 | if (ConditionPassed()) |
| 2139 | { |
| 2140 | uint32_t n; |
| 2141 | uint32_t registers = 0; |
| 2142 | bool wback; |
| 2143 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2144 | switch (encoding) |
| 2145 | { |
| 2146 | case eEncodingT1: |
| 2147 | n = Bits32 (opcode, 10, 8); |
| 2148 | registers = Bits32 (opcode, 7, 0); |
| 2149 | wback = BitIsClear (registers, n); |
| 2150 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 2151 | if (BitCount(registers) < 1) |
| 2152 | return false; |
| 2153 | break; |
| 2154 | case eEncodingT2: |
| 2155 | n = Bits32 (opcode, 19, 16); |
| 2156 | registers = Bits32 (opcode, 15, 0); |
| 2157 | wback = BitIsSet (opcode, 21); |
| 2158 | if ((n == 15) |
| 2159 | || (BitCount (registers) < 2) |
| 2160 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2161 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2162 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2163 | return false; |
| 2164 | if (wback |
| 2165 | && BitIsSet (registers, n)) |
| 2166 | return false; |
| 2167 | break; |
| 2168 | case eEncodingA1: |
| 2169 | n = Bits32 (opcode, 19, 16); |
| 2170 | registers = Bits32 (opcode, 15, 0); |
| 2171 | wback = BitIsSet (opcode, 21); |
| 2172 | if ((n == 15) |
| 2173 | || (BitCount (registers) < 1)) |
| 2174 | return false; |
| 2175 | break; |
| 2176 | default: |
| 2177 | return false; |
| 2178 | } |
| 2179 | |
| 2180 | int32_t offset = 0; |
| 2181 | const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2182 | if (!success) |
| 2183 | return false; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2184 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2185 | EmulateInstruction::Context context; |
| 2186 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2187 | Register dwarf_reg; |
| 2188 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2189 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2190 | |
| 2191 | for (int i = 0; i < 14; ++i) |
| 2192 | { |
| 2193 | if (BitIsSet (registers, i)) |
| 2194 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2195 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2196 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2197 | if (wback && (n == 13)) // Pop Instruction |
| 2198 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 2199 | |
| 2200 | // R[i] = MemA [address, 4]; address = address + 4; |
| 2201 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2202 | if (!success) |
| 2203 | return false; |
| 2204 | |
| 2205 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2206 | return false; |
| 2207 | |
| 2208 | offset += addr_byte_size; |
| 2209 | } |
| 2210 | } |
| 2211 | |
| 2212 | if (BitIsSet (registers, 15)) |
| 2213 | { |
| 2214 | //LoadWritePC (MemA [address, 4]); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2215 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2216 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2217 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2218 | if (!success) |
| 2219 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2220 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2221 | if (!LoadWritePC(context, data, dwarf_reg)) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2222 | return false; |
| 2223 | } |
| 2224 | |
| 2225 | if (wback && BitIsClear (registers, n)) |
| 2226 | { |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2227 | // R[n] = R[n] + 4 * BitCount (registers) |
| 2228 | int32_t offset = addr_byte_size * BitCount (registers); |
| 2229 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2230 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2231 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2232 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset)) |
| 2233 | return false; |
| 2234 | } |
| 2235 | if (wback && BitIsSet (registers, n)) |
| 2236 | // R[n] bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2237 | return WriteBits32Unknown (n); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2238 | } |
| 2239 | return true; |
| 2240 | } |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2241 | |
| 2242 | // LDMDA loads multiple registers from consecutive memory locations using an address from a base registers. |
| 2243 | // The consecutive memorty locations end at this address and the address just below the lowest of those locations |
| 2244 | // can optionally be written back tot he base registers. |
| 2245 | bool |
| 2246 | EmulateInstructionARM::EmulateLDMDA (ARMEncoding encoding) |
| 2247 | { |
| 2248 | #if 0 |
| 2249 | // ARM pseudo code... |
| 2250 | if ConditionPassed() then |
| 2251 | EncodingSpecificOperations(); |
| 2252 | address = R[n] - 4*BitCount(registers) + 4; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2253 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2254 | for i = 0 to 14 |
| 2255 | if registers<i> == ’1’ then |
| 2256 | R[i] = MemA[address,4]; address = address + 4; |
| 2257 | |
| 2258 | if registers<15> == ’1’ then |
| 2259 | LoadWritePC(MemA[address,4]); |
| 2260 | |
| 2261 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2262 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2263 | #endif |
| 2264 | |
| 2265 | bool success = false; |
| 2266 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2267 | if (!success) |
| 2268 | return false; |
| 2269 | |
| 2270 | if (ConditionPassed()) |
| 2271 | { |
| 2272 | uint32_t n; |
| 2273 | uint32_t registers = 0; |
| 2274 | bool wback; |
| 2275 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2276 | |
| 2277 | // EncodingSpecificOperations(); |
| 2278 | switch (encoding) |
| 2279 | { |
| 2280 | case eEncodingA1: |
| 2281 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2282 | n = Bits32 (opcode, 19, 16); |
| 2283 | registers = Bits32 (opcode, 15, 0); |
| 2284 | wback = BitIsSet (opcode, 21); |
| 2285 | |
| 2286 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2287 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2288 | return false; |
| 2289 | |
| 2290 | break; |
| 2291 | |
| 2292 | default: |
| 2293 | return false; |
| 2294 | } |
| 2295 | // address = R[n] - 4*BitCount(registers) + 4; |
| 2296 | |
| 2297 | int32_t offset = 0; |
| 2298 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2299 | |
| 2300 | if (!success) |
| 2301 | return false; |
| 2302 | |
| 2303 | address = address - (addr_byte_size * BitCount (registers)) + addr_byte_size; |
| 2304 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2305 | EmulateInstruction::Context context; |
| 2306 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2307 | Register dwarf_reg; |
| 2308 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2309 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2310 | |
| 2311 | // for i = 0 to 14 |
| 2312 | for (int i = 0; i < 14; ++i) |
| 2313 | { |
| 2314 | // if registers<i> == ’1’ then |
| 2315 | if (BitIsSet (registers, i)) |
| 2316 | { |
| 2317 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2318 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2319 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2320 | if (!success) |
| 2321 | return false; |
| 2322 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2323 | return false; |
| 2324 | offset += addr_byte_size; |
| 2325 | } |
| 2326 | } |
| 2327 | |
| 2328 | // if registers<15> == ’1’ then |
| 2329 | // LoadWritePC(MemA[address,4]); |
| 2330 | if (BitIsSet (registers, 15)) |
| 2331 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2332 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2333 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2334 | if (!success) |
| 2335 | return false; |
Johnny Chen | 44c10f0 | 2011-02-11 19:37:03 +0000 | [diff] [blame] | 2336 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2337 | if (!LoadWritePC(context, data, dwarf_reg)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2338 | return false; |
| 2339 | } |
| 2340 | |
| 2341 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2342 | if (wback && BitIsClear (registers, n)) |
| 2343 | { |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2344 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2345 | if (!success) |
| 2346 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2347 | |
| 2348 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2349 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2350 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2351 | addr = addr + offset; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2352 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2353 | return false; |
| 2354 | } |
| 2355 | |
| 2356 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2357 | if (wback && BitIsSet (registers, n)) |
| 2358 | return WriteBits32Unknown (n); |
| 2359 | } |
| 2360 | return true; |
| 2361 | } |
| 2362 | |
| 2363 | // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2364 | // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can |
| 2365 | // be optionally written back to the base register. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2366 | bool |
| 2367 | EmulateInstructionARM::EmulateLDMDB (ARMEncoding encoding) |
| 2368 | { |
| 2369 | #if 0 |
| 2370 | // ARM pseudo code... |
| 2371 | if ConditionPassed() then |
| 2372 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2373 | address = R[n] - 4*BitCount(registers); |
| 2374 | |
| 2375 | for i = 0 to 14 |
| 2376 | if registers<i> == ’1’ then |
| 2377 | R[i] = MemA[address,4]; address = address + 4; |
| 2378 | if registers<15> == ’1’ then |
| 2379 | LoadWritePC(MemA[address,4]); |
| 2380 | |
| 2381 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2382 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2383 | #endif |
| 2384 | |
| 2385 | bool success = false; |
| 2386 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2387 | if (!success) |
| 2388 | return false; |
| 2389 | |
| 2390 | if (ConditionPassed()) |
| 2391 | { |
| 2392 | uint32_t n; |
| 2393 | uint32_t registers = 0; |
| 2394 | bool wback; |
| 2395 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2396 | switch (encoding) |
| 2397 | { |
| 2398 | case eEncodingT1: |
| 2399 | // n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ’1’); |
| 2400 | n = Bits32 (opcode, 19, 16); |
| 2401 | registers = Bits32 (opcode, 15, 0); |
| 2402 | wback = BitIsSet (opcode, 21); |
| 2403 | |
| 2404 | // if n == 15 || BitCount(registers) < 2 || (P == ’1’ && M == ’1’) then UNPREDICTABLE; |
| 2405 | if ((n == 15) |
| 2406 | || (BitCount (registers) < 2) |
| 2407 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2408 | return false; |
| 2409 | |
| 2410 | // if registers<15> == ’1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2411 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2412 | return false; |
| 2413 | |
| 2414 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 2415 | if (wback && BitIsSet (registers, n)) |
| 2416 | return false; |
| 2417 | |
| 2418 | break; |
| 2419 | |
| 2420 | case eEncodingA1: |
| 2421 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2422 | n = Bits32 (opcode, 19, 16); |
| 2423 | registers = Bits32 (opcode, 15, 0); |
| 2424 | wback = BitIsSet (opcode, 21); |
| 2425 | |
| 2426 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2427 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2428 | return false; |
| 2429 | |
| 2430 | break; |
| 2431 | |
| 2432 | default: |
| 2433 | return false; |
| 2434 | } |
| 2435 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2436 | // address = R[n] - 4*BitCount(registers); |
| 2437 | |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2438 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2439 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2440 | |
| 2441 | if (!success) |
| 2442 | return false; |
| 2443 | |
| 2444 | address = address - (addr_byte_size * BitCount (registers)); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2445 | EmulateInstruction::Context context; |
| 2446 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2447 | Register dwarf_reg; |
| 2448 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2449 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2450 | |
| 2451 | for (int i = 0; i < 14; ++i) |
| 2452 | { |
| 2453 | if (BitIsSet (registers, i)) |
| 2454 | { |
| 2455 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2456 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2457 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2458 | if (!success) |
| 2459 | return false; |
| 2460 | |
| 2461 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2462 | return false; |
| 2463 | |
| 2464 | offset += addr_byte_size; |
| 2465 | } |
| 2466 | } |
| 2467 | |
| 2468 | // if registers<15> == ’1’ then |
| 2469 | // LoadWritePC(MemA[address,4]); |
| 2470 | if (BitIsSet (registers, 15)) |
| 2471 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2472 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2473 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2474 | if (!success) |
| 2475 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2476 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2477 | if (!LoadWritePC(context, data, dwarf_reg)) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2478 | return false; |
| 2479 | } |
| 2480 | |
| 2481 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2482 | if (wback && BitIsClear (registers, n)) |
| 2483 | { |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2484 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2485 | if (!success) |
| 2486 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2487 | |
| 2488 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2489 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2490 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2491 | addr = addr + offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2492 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2493 | return false; |
| 2494 | } |
| 2495 | |
| 2496 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2497 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2498 | return WriteBits32Unknown (n); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2499 | } |
| 2500 | return true; |
| 2501 | } |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2502 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2503 | // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2504 | // consecutive memory locations start just above this address, and thea ddress of the last of those locations can |
| 2505 | // optinoally be written back to the base register. |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2506 | bool |
| 2507 | EmulateInstructionARM::EmulateLDMIB (ARMEncoding encoding) |
| 2508 | { |
| 2509 | #if 0 |
| 2510 | if ConditionPassed() then |
| 2511 | EncodingSpecificOperations(); |
| 2512 | address = R[n] + 4; |
| 2513 | |
| 2514 | for i = 0 to 14 |
| 2515 | if registers<i> == ’1’ then |
| 2516 | R[i] = MemA[address,4]; address = address + 4; |
| 2517 | if registers<15> == ’1’ then |
| 2518 | LoadWritePC(MemA[address,4]); |
| 2519 | |
| 2520 | if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 2521 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2522 | #endif |
| 2523 | |
| 2524 | bool success = false; |
| 2525 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2526 | if (!success) |
| 2527 | return false; |
| 2528 | |
| 2529 | if (ConditionPassed()) |
| 2530 | { |
| 2531 | uint32_t n; |
| 2532 | uint32_t registers = 0; |
| 2533 | bool wback; |
| 2534 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2535 | switch (encoding) |
| 2536 | { |
| 2537 | case eEncodingA1: |
| 2538 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2539 | n = Bits32 (opcode, 19, 16); |
| 2540 | registers = Bits32 (opcode, 15, 0); |
| 2541 | wback = BitIsSet (opcode, 21); |
| 2542 | |
| 2543 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2544 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2545 | return false; |
| 2546 | |
| 2547 | break; |
| 2548 | default: |
| 2549 | return false; |
| 2550 | } |
| 2551 | // address = R[n] + 4; |
| 2552 | |
| 2553 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2554 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2555 | |
| 2556 | if (!success) |
| 2557 | return false; |
| 2558 | |
| 2559 | address = address + addr_byte_size; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2560 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2561 | EmulateInstruction::Context context; |
| 2562 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2563 | Register dwarf_reg; |
| 2564 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2565 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2566 | |
| 2567 | for (int i = 0; i < 14; ++i) |
| 2568 | { |
| 2569 | if (BitIsSet (registers, i)) |
| 2570 | { |
| 2571 | // R[i] = MemA[address,4]; address = address + 4; |
| 2572 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2573 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2574 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2575 | if (!success) |
| 2576 | return false; |
| 2577 | |
| 2578 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2579 | return false; |
| 2580 | |
| 2581 | offset += addr_byte_size; |
| 2582 | } |
| 2583 | } |
| 2584 | |
| 2585 | // if registers<15> == ’1’ then |
| 2586 | // LoadWritePC(MemA[address,4]); |
| 2587 | if (BitIsSet (registers, 15)) |
| 2588 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2589 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2590 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2591 | if (!success) |
| 2592 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2593 | // In ARMv5T and above, this is an interworking branch. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2594 | if (!LoadWritePC(context, data, dwarf_reg)) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2595 | return false; |
| 2596 | } |
| 2597 | |
| 2598 | // if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 2599 | if (wback && BitIsClear (registers, n)) |
| 2600 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2601 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2602 | if (!success) |
| 2603 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2604 | |
| 2605 | offset = addr_byte_size * BitCount (registers); |
| 2606 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2607 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2608 | addr = addr + offset; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2609 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2610 | return false; |
| 2611 | } |
| 2612 | |
| 2613 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2614 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2615 | return WriteBits32Unknown (n); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2616 | } |
| 2617 | return true; |
| 2618 | } |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2619 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2620 | // Load Register (immediate) calculates an address from a base register value and |
| 2621 | // an immediate offset, loads a word from memory, and writes to a register. |
| 2622 | // LDR (immediate, Thumb) |
| 2623 | bool |
| 2624 | EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding) |
| 2625 | { |
| 2626 | #if 0 |
| 2627 | // ARM pseudo code... |
| 2628 | if (ConditionPassed()) |
| 2629 | { |
| 2630 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 2631 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 2632 | address = if index then offset_addr else R[n]; |
| 2633 | data = MemU[address,4]; |
| 2634 | if wback then R[n] = offset_addr; |
| 2635 | if t == 15 then |
| 2636 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 2637 | elsif UnalignedSupport() || address<1:0> = '00' then |
| 2638 | R[t] = data; |
| 2639 | else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7 |
| 2640 | } |
| 2641 | #endif |
| 2642 | |
| 2643 | bool success = false; |
| 2644 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2645 | if (!success) |
| 2646 | return false; |
| 2647 | |
| 2648 | if (ConditionPassed()) |
| 2649 | { |
| 2650 | uint32_t Rt; // the destination register |
| 2651 | uint32_t Rn; // the base register |
| 2652 | uint32_t imm32; // the immediate offset used to form the address |
| 2653 | addr_t offset_addr; // the offset address |
| 2654 | addr_t address; // the calculated address |
| 2655 | uint32_t data; // the literal data value from memory load |
| 2656 | bool add, index, wback; |
| 2657 | switch (encoding) { |
| 2658 | case eEncodingT1: |
| 2659 | Rt = Bits32(opcode, 5, 3); |
| 2660 | Rn = Bits32(opcode, 2, 0); |
| 2661 | imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); |
| 2662 | // index = TRUE; add = TRUE; wback = FALSE |
| 2663 | add = true; |
| 2664 | index = true; |
| 2665 | wback = false; |
| 2666 | break; |
| 2667 | default: |
| 2668 | return false; |
| 2669 | } |
| 2670 | uint32_t base = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2671 | if (!success) |
| 2672 | return false; |
| 2673 | if (add) |
| 2674 | offset_addr = base + imm32; |
| 2675 | else |
| 2676 | offset_addr = base - imm32; |
| 2677 | |
| 2678 | address = (index ? offset_addr : base); |
| 2679 | |
| 2680 | if (wback) |
| 2681 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2682 | EmulateInstruction::Context ctx; |
| 2683 | ctx.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2684 | Register dwarf_reg; |
| 2685 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn); |
| 2686 | ctx.SetRegisterPlusOffset (dwarf_reg, (int32_t) (offset_addr - base)); |
| 2687 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2688 | if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr)) |
| 2689 | return false; |
| 2690 | } |
| 2691 | |
| 2692 | // Prepare to write to the Rt register. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2693 | EmulateInstruction::Context context; |
| 2694 | context.type = EmulateInstruction::eContextImmediate; |
| 2695 | context.SetNoArgs (); |
| 2696 | Register dummy_reg; |
| 2697 | dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2698 | |
| 2699 | // Read memory from the address. |
| 2700 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
| 2701 | if (!success) |
| 2702 | return false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2703 | |
| 2704 | if (Rt == 15) |
| 2705 | { |
| 2706 | if (Bits32(address, 1, 0) == 0) |
| 2707 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2708 | if (!LoadWritePC(context, data, dummy_reg)) |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 2709 | return false; |
| 2710 | } |
| 2711 | else |
| 2712 | return false; |
| 2713 | } |
| 2714 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 2715 | { |
| 2716 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 2717 | return false; |
| 2718 | } |
| 2719 | else |
| 2720 | return false; |
| 2721 | } |
| 2722 | return true; |
| 2723 | } |
| 2724 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2725 | // STM stores multiple registers to consecutive memory locations using an address from a base register. The |
| 2726 | // consecutive memory locations start at this address, and teh address just above the last of those locations can |
| 2727 | // optionally be written back to the base register. |
| 2728 | bool |
| 2729 | EmulateInstructionARM::EmulateSTM (ARMEncoding encoding) |
| 2730 | { |
| 2731 | #if 0 |
| 2732 | if ConditionPassed() then |
| 2733 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2734 | address = R[n]; |
| 2735 | |
| 2736 | for i = 0 to 14 |
| 2737 | if registers<i> == ’1’ then |
| 2738 | if i == n && wback && i != LowestSetBit(registers) then |
| 2739 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 2740 | else |
| 2741 | MemA[address,4] = R[i]; |
| 2742 | address = address + 4; |
| 2743 | |
| 2744 | if registers<15> == ’1’ then // Only possible for encoding A1 |
| 2745 | MemA[address,4] = PCStoreValue(); |
| 2746 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 2747 | #endif |
| 2748 | |
| 2749 | bool success = false; |
| 2750 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2751 | if (!success) |
| 2752 | return false; |
| 2753 | |
| 2754 | if (ConditionPassed ()) |
| 2755 | { |
| 2756 | uint32_t n; |
| 2757 | uint32_t registers = 0; |
| 2758 | bool wback; |
| 2759 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2760 | |
| 2761 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2762 | switch (encoding) |
| 2763 | { |
| 2764 | case eEncodingT1: |
| 2765 | // n = UInt(Rn); registers = ’00000000’:register_list; wback = TRUE; |
| 2766 | n = Bits32 (opcode, 10, 8); |
| 2767 | registers = Bits32 (opcode, 7, 0); |
| 2768 | wback = true; |
| 2769 | |
| 2770 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 2771 | if (BitCount (registers) < 1) |
| 2772 | return false; |
| 2773 | |
| 2774 | break; |
| 2775 | |
| 2776 | case eEncodingT2: |
| 2777 | // n = UInt(Rn); registers = ’0’:M:’0’:register_list; wback = (W == ’1’); |
| 2778 | n = Bits32 (opcode, 19, 16); |
| 2779 | registers = Bits32 (opcode, 15, 0); |
| 2780 | wback = BitIsSet (opcode, 21); |
| 2781 | |
| 2782 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 2783 | if ((n == 15) || (BitCount (registers) < 2)) |
| 2784 | return false; |
| 2785 | |
| 2786 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 2787 | if (wback && BitIsSet (registers, n)) |
| 2788 | return false; |
| 2789 | |
| 2790 | break; |
| 2791 | |
| 2792 | case eEncodingA1: |
| 2793 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2794 | n = Bits32 (opcode, 19, 16); |
| 2795 | registers = Bits32 (opcode, 15, 0); |
| 2796 | wback = BitIsSet (opcode, 21); |
| 2797 | |
| 2798 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2799 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2800 | return false; |
| 2801 | |
| 2802 | break; |
| 2803 | |
| 2804 | default: |
| 2805 | return false; |
| 2806 | } |
| 2807 | |
| 2808 | // address = R[n]; |
| 2809 | int32_t offset = 0; |
| 2810 | const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2811 | if (!success) |
| 2812 | return false; |
| 2813 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2814 | EmulateInstruction::Context context; |
| 2815 | context.type = EmulateInstruction::eContextRegisterStore; |
| 2816 | Register base_reg; |
| 2817 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2818 | |
| 2819 | // for i = 0 to 14 |
| 2820 | for (int i = 0; i < 14; ++i) |
| 2821 | { |
| 2822 | int lowest_set_bit = 14; |
| 2823 | // if registers<i> == ’1’ then |
| 2824 | if (BitIsSet (registers, i)) |
| 2825 | { |
| 2826 | if (i < lowest_set_bit) |
| 2827 | lowest_set_bit = i; |
| 2828 | // if i == n && wback && i != LowestSetBit(registers) then |
| 2829 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 2830 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 2831 | WriteBits32UnknownToMemory (address + offset); |
| 2832 | else |
| 2833 | { |
| 2834 | // MemA[address,4] = R[i]; |
| 2835 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 2836 | if (!success) |
| 2837 | return false; |
| 2838 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2839 | Register data_reg; |
| 2840 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 2841 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2842 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 2843 | return false; |
| 2844 | } |
| 2845 | |
| 2846 | // address = address + 4; |
| 2847 | offset += addr_byte_size; |
| 2848 | } |
| 2849 | } |
| 2850 | |
| 2851 | // if registers<15> == ’1’ then // Only possible for encoding A1 |
| 2852 | // MemA[address,4] = PCStoreValue(); |
| 2853 | if (BitIsSet (registers, 15)) |
| 2854 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2855 | Register pc_reg; |
| 2856 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 2857 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2858 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 2859 | if (!success) |
| 2860 | return false; |
| 2861 | |
| 2862 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 2863 | return false; |
| 2864 | } |
| 2865 | |
| 2866 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 2867 | if (wback) |
| 2868 | { |
| 2869 | offset = addr_byte_size * BitCount (registers); |
| 2870 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2871 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2872 | addr_t data = address + offset; |
| 2873 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 2874 | return false; |
| 2875 | } |
| 2876 | } |
| 2877 | return true; |
| 2878 | } |
| 2879 | |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 2880 | // STMDA stores multiple registers to consecutive memory locations using an address from a base register. The |
| 2881 | // consecutive memory locations end at this address, and the address just below the lowest of those locations can |
| 2882 | // optionally be written back to the base register. |
| 2883 | bool |
| 2884 | EmulateInstructionARM::EmulateSTMDA (ARMEncoding encoding) |
| 2885 | { |
| 2886 | #if 0 |
| 2887 | if ConditionPassed() then |
| 2888 | EncodingSpecificOperations(); |
| 2889 | address = R[n] - 4*BitCount(registers) + 4; |
| 2890 | |
| 2891 | for i = 0 to 14 |
| 2892 | if registers<i> == ’1’ then |
| 2893 | if i == n && wback && i != LowestSetBit(registers) then |
| 2894 | MemA[address,4] = bits(32) UNKNOWN; |
| 2895 | else |
| 2896 | MemA[address,4] = R[i]; |
| 2897 | address = address + 4; |
| 2898 | |
| 2899 | if registers<15> == ’1’ then |
| 2900 | MemA[address,4] = PCStoreValue(); |
| 2901 | |
| 2902 | if wback then R[n] = R[n] - 4*BitCount(registers); |
| 2903 | #endif |
| 2904 | |
| 2905 | bool success = false; |
| 2906 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2907 | if (!success) |
| 2908 | return false; |
| 2909 | |
| 2910 | if (ConditionPassed ()) |
| 2911 | { |
| 2912 | uint32_t n; |
| 2913 | uint32_t registers = 0; |
| 2914 | bool wback; |
| 2915 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2916 | |
| 2917 | // EncodingSpecificOperations(); |
| 2918 | switch (encoding) |
| 2919 | { |
| 2920 | case eEncodingA1: |
| 2921 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2922 | n = Bits32 (opcode, 19, 16); |
| 2923 | registers = Bits32 (opcode, 15, 0); |
| 2924 | wback = BitIsSet (opcode, 21); |
| 2925 | |
| 2926 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2927 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2928 | return false; |
| 2929 | break; |
| 2930 | default: |
| 2931 | return false; |
| 2932 | } |
| 2933 | |
| 2934 | // address = R[n] - 4*BitCount(registers) + 4; |
| 2935 | int32_t offset = 0; |
| 2936 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2937 | if (!success) |
| 2938 | return false; |
| 2939 | |
| 2940 | address = address - (addr_byte_size * BitCount (registers)) + 4; |
| 2941 | |
| 2942 | EmulateInstruction::Context context; |
| 2943 | context.type = EmulateInstruction::eContextRegisterStore; |
| 2944 | Register base_reg; |
| 2945 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2946 | |
| 2947 | // for i = 0 to 14 |
| 2948 | for (int i = 0; i < 14; ++i) |
| 2949 | { |
| 2950 | int lowest_bit_set = 14; |
| 2951 | // if registers<i> == ’1’ then |
| 2952 | if (BitIsSet (registers, i)) |
| 2953 | { |
| 2954 | if (i < lowest_bit_set) |
| 2955 | lowest_bit_set = i; |
| 2956 | //if i == n && wback && i != LowestSetBit(registers) then |
| 2957 | if ((i == n) && wback && (i != lowest_bit_set)) |
| 2958 | // MemA[address,4] = bits(32) UNKNOWN; |
| 2959 | WriteBits32UnknownToMemory (address + offset); |
| 2960 | else |
| 2961 | { |
| 2962 | // MemA[address,4] = R[i]; |
| 2963 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 2964 | if (!success) |
| 2965 | return false; |
| 2966 | |
| 2967 | Register data_reg; |
| 2968 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 2969 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
| 2970 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 2971 | return false; |
| 2972 | } |
| 2973 | |
| 2974 | // address = address + 4; |
| 2975 | offset += addr_byte_size; |
| 2976 | } |
| 2977 | } |
| 2978 | |
| 2979 | // if registers<15> == ’1’ then |
| 2980 | // MemA[address,4] = PCStoreValue(); |
| 2981 | if (BitIsSet (registers, 15)) |
| 2982 | { |
| 2983 | Register pc_reg; |
| 2984 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 2985 | context.SetRegisterPlusOffset (pc_reg, 8); |
| 2986 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 2987 | if (!success) |
| 2988 | return false; |
| 2989 | |
| 2990 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 2991 | return false; |
| 2992 | } |
| 2993 | |
| 2994 | // if wback then R[n] = R[n] - 4*BitCount(registers); |
| 2995 | if (wback) |
| 2996 | { |
| 2997 | offset = addr_byte_size * BitCount (registers); |
| 2998 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 2999 | context.SetImmediateSigned (offset); |
| 3000 | addr_t data = address + offset; |
| 3001 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3002 | return false; |
| 3003 | } |
| 3004 | } |
| 3005 | return true; |
| 3006 | } |
| 3007 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3008 | EmulateInstructionARM::ARMOpcode* |
| 3009 | EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3010 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3011 | static ARMOpcode |
| 3012 | g_arm_opcodes[] = |
| 3013 | { |
| 3014 | //---------------------------------------------------------------------- |
| 3015 | // Prologue instructions |
| 3016 | //---------------------------------------------------------------------- |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 3017 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3018 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3019 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
| 3020 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePush, "push <register>" }, |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 3021 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3022 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3023 | { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #<const>" }, |
| 3024 | { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubR7IPImmediate, "sub r7, ip, #<const>"}, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 3025 | // copy the stack pointer to ip |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3026 | { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMovRdSP, "mov ip, sp" }, |
| 3027 | { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add ip, sp, #<const>" }, |
| 3028 | { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubIPSPImmediate, "sub ip, sp, #<const>"}, |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 3029 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3030 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3031 | { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub sp, sp, #<const>"}, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 3032 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3033 | // push one register |
| 3034 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3035 | { 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" }, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 3036 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3037 | // vector push consecutive extension register(s) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 3038 | { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 3039 | { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 3040 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3041 | //---------------------------------------------------------------------- |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 3042 | // Epilogue instructions |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3043 | //---------------------------------------------------------------------- |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 3044 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3045 | { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
| 3046 | { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePop, "pop <register>"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 3047 | { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 3048 | { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 3049 | |
| 3050 | //---------------------------------------------------------------------- |
| 3051 | // Supervisor Call (previously Software Interrupt) |
| 3052 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 3053 | { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, |
| 3054 | |
| 3055 | //---------------------------------------------------------------------- |
| 3056 | // Branch instructions |
| 3057 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3058 | { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "b #imm24"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 3059 | // To resolve ambiguity, "blx <label>" should come before "bl <label>". |
| 3060 | { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 3061 | { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 3062 | { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 3063 | // for example, "bx lr" |
| 3064 | { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 3065 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3066 | //---------------------------------------------------------------------- |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 3067 | // Data-processing instructions |
| 3068 | //---------------------------------------------------------------------- |
| 3069 | // move bitwise not |
| 3070 | { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
| 3071 | |
| 3072 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3073 | // Load instructions |
| 3074 | //---------------------------------------------------------------------- |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3075 | { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3076 | { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3077 | { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3078 | { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" }, |
| 3079 | |
| 3080 | //---------------------------------------------------------------------- |
| 3081 | // Store instructions |
| 3082 | //---------------------------------------------------------------------- |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3083 | { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
| 3084 | { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" } |
| 3085 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3086 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3087 | }; |
| 3088 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
| 3089 | |
| 3090 | for (size_t i=0; i<k_num_arm_opcodes; ++i) |
| 3091 | { |
| 3092 | if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) |
| 3093 | return &g_arm_opcodes[i]; |
| 3094 | } |
| 3095 | return NULL; |
| 3096 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3097 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3098 | |
| 3099 | EmulateInstructionARM::ARMOpcode* |
| 3100 | EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 3101 | { |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 3102 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3103 | static ARMOpcode |
| 3104 | g_thumb_opcodes[] = |
| 3105 | { |
| 3106 | //---------------------------------------------------------------------- |
| 3107 | // Prologue instructions |
| 3108 | //---------------------------------------------------------------------- |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 3109 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3110 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3111 | { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 3112 | { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <registers>" }, |
| 3113 | { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <register>" }, |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 3114 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3115 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3116 | { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #imm" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 3117 | // copy the stack pointer to r7 |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3118 | { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdSP, "mov r7, sp" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 3119 | // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity) |
| 3120 | { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovLowHigh, "mov r0-r7, r8-r15" }, |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 3121 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 3122 | // PC-relative load into register (see also EmulateAddSPRm) |
| 3123 | { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"}, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 3124 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3125 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3126 | { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPRm, "add sp, <Rm>"}, |
| 3127 | { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSubSPImmdiate, "add sp, sp, #imm"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 3128 | { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub.w sp, sp, #<const>"}, |
| 3129 | { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "subw sp, sp, #imm12"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 3130 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3131 | // vector push consecutive extension register(s) |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 3132 | { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 3133 | { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 3134 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3135 | //---------------------------------------------------------------------- |
| 3136 | // Epilogue instructions |
| 3137 | //---------------------------------------------------------------------- |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 3138 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 3139 | { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPImmediate, "add sp, #imm"}, |
| 3140 | { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 3141 | { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <registers>" }, |
| 3142 | { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <register>" }, |
| 3143 | { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
| 3144 | { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 3145 | |
| 3146 | //---------------------------------------------------------------------- |
| 3147 | // Supervisor Call (previously Software Interrupt) |
| 3148 | //---------------------------------------------------------------------- |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 3149 | { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, |
| 3150 | |
| 3151 | //---------------------------------------------------------------------- |
| 3152 | // If Then makes up to four following instructions conditional. |
| 3153 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 3154 | { 0xffffff00, 0x0000bf00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, |
| 3155 | |
| 3156 | //---------------------------------------------------------------------- |
| 3157 | // Branch instructions |
| 3158 | //---------------------------------------------------------------------- |
| 3159 | // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". |
| 3160 | { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, |
| 3161 | { 0xffff8000, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b #imm11 (outside or last in IT)"}, |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3162 | { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3163 | { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 3164 | // J1 == J2 == 1 |
| 3165 | { 0xf800f800, 0xf000f800, ARMV4T_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 3166 | // J1 == J2 == 1 |
| 3167 | { 0xf800e800, 0xf000e800, ARMV5_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 3168 | { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 3169 | // for example, "bx lr" |
| 3170 | { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3171 | // compare and branch |
| 3172 | { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3173 | |
| 3174 | //---------------------------------------------------------------------- |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3175 | // Data-processing instructions |
| 3176 | //---------------------------------------------------------------------- |
| 3177 | // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two. |
| 3178 | { 0xffffff00, 0x00004400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdnRm, "add <Rdn>, <Rm>"}, |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 3179 | // move from high register to high register |
| 3180 | { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "mov<c> <Rd>, <Rm>"}, |
| 3181 | // move from low register to low register |
| 3182 | { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "movs <Rd>, <Rm>"}, |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 3183 | // move immediate |
| 3184 | { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdImm, "movs|mov<c> <Rd>, #imm8"}, |
| 3185 | { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMovRdImm, "mov{s}<c>.w <Rd>, #<const>"}, |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 3186 | // move bitwise not |
| 3187 | { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 3188 | // compare a register with immediate |
| 3189 | { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnImm, "cmp<c> <Rn>, #imm8"}, |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 3190 | // compare Rn with Rm (Rn and Rm both from r0-r7) |
| 3191 | { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
| 3192 | // compare Rn with Rm (Rn and Rm not both from r0-r7) |
| 3193 | { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3194 | |
| 3195 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3196 | // Load instructions |
| 3197 | //---------------------------------------------------------------------- |
| 3198 | { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3199 | { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" }, |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3200 | { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 3201 | { 0xfffff800, 0x00006800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"}, |
| 3202 | // Thumb2 PC-relative load into register |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3203 | { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"}, |
| 3204 | |
| 3205 | //---------------------------------------------------------------------- |
| 3206 | // Store instructions |
| 3207 | //---------------------------------------------------------------------- |
| 3208 | { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
| 3209 | { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" } |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 3210 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 3211 | }; |
| 3212 | |
| 3213 | const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
| 3214 | for (size_t i=0; i<k_num_thumb_opcodes; ++i) |
| 3215 | { |
| 3216 | if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) |
| 3217 | return &g_thumb_opcodes[i]; |
| 3218 | } |
| 3219 | return NULL; |
| 3220 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3221 | |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 3222 | bool |
| 3223 | EmulateInstructionARM::SetTargetTriple (const ConstString &triple) |
| 3224 | { |
| 3225 | m_arm_isa = 0; |
| 3226 | const char *triple_cstr = triple.GetCString(); |
| 3227 | if (triple_cstr) |
| 3228 | { |
| 3229 | const char *dash = ::strchr (triple_cstr, '-'); |
| 3230 | if (dash) |
| 3231 | { |
| 3232 | std::string arch (triple_cstr, dash); |
| 3233 | const char *arch_cstr = arch.c_str(); |
| 3234 | if (strcasecmp(arch_cstr, "armv4t") == 0) |
| 3235 | m_arm_isa = ARMv4T; |
| 3236 | else if (strcasecmp(arch_cstr, "armv4") == 0) |
| 3237 | m_arm_isa = ARMv4; |
| 3238 | else if (strcasecmp(arch_cstr, "armv5tej") == 0) |
| 3239 | m_arm_isa = ARMv5TEJ; |
| 3240 | else if (strcasecmp(arch_cstr, "armv5te") == 0) |
| 3241 | m_arm_isa = ARMv5TE; |
| 3242 | else if (strcasecmp(arch_cstr, "armv5t") == 0) |
| 3243 | m_arm_isa = ARMv5T; |
| 3244 | else if (strcasecmp(arch_cstr, "armv6k") == 0) |
| 3245 | m_arm_isa = ARMv6K; |
| 3246 | else if (strcasecmp(arch_cstr, "armv6") == 0) |
| 3247 | m_arm_isa = ARMv6; |
| 3248 | else if (strcasecmp(arch_cstr, "armv6t2") == 0) |
| 3249 | m_arm_isa = ARMv6T2; |
| 3250 | else if (strcasecmp(arch_cstr, "armv7") == 0) |
| 3251 | m_arm_isa = ARMv7; |
| 3252 | else if (strcasecmp(arch_cstr, "armv8") == 0) |
| 3253 | m_arm_isa = ARMv8; |
| 3254 | } |
| 3255 | } |
| 3256 | return m_arm_isa != 0; |
| 3257 | } |
| 3258 | |
| 3259 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3260 | bool |
| 3261 | EmulateInstructionARM::ReadInstruction () |
| 3262 | { |
| 3263 | bool success = false; |
| 3264 | m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
| 3265 | if (success) |
| 3266 | { |
| 3267 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 3268 | if (success) |
| 3269 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3270 | Context read_inst_context; |
| 3271 | read_inst_context.type = eContextReadOpcode; |
| 3272 | read_inst_context.SetNoArgs (); |
| 3273 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3274 | if (m_inst_cpsr & MASK_CPSR_T) |
| 3275 | { |
| 3276 | m_inst_mode = eModeThumb; |
| 3277 | uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success); |
| 3278 | |
| 3279 | if (success) |
| 3280 | { |
| 3281 | if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0)) |
| 3282 | { |
| 3283 | m_inst.opcode_type = eOpcode16; |
| 3284 | m_inst.opcode.inst16 = thumb_opcode; |
| 3285 | } |
| 3286 | else |
| 3287 | { |
| 3288 | m_inst.opcode_type = eOpcode32; |
| 3289 | m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success); |
| 3290 | } |
| 3291 | } |
| 3292 | } |
| 3293 | else |
| 3294 | { |
| 3295 | m_inst_mode = eModeARM; |
| 3296 | m_inst.opcode_type = eOpcode32; |
| 3297 | m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success); |
| 3298 | } |
| 3299 | } |
| 3300 | } |
| 3301 | if (!success) |
| 3302 | { |
| 3303 | m_inst_mode = eModeInvalid; |
| 3304 | m_inst_pc = LLDB_INVALID_ADDRESS; |
| 3305 | } |
| 3306 | return success; |
| 3307 | } |
| 3308 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3309 | uint32_t |
| 3310 | EmulateInstructionARM::ArchVersion () |
| 3311 | { |
| 3312 | return m_arm_isa; |
| 3313 | } |
| 3314 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3315 | bool |
| 3316 | EmulateInstructionARM::ConditionPassed () |
| 3317 | { |
| 3318 | if (m_inst_cpsr == 0) |
| 3319 | return false; |
| 3320 | |
| 3321 | const uint32_t cond = CurrentCond (); |
| 3322 | |
| 3323 | if (cond == UINT32_MAX) |
| 3324 | return false; |
| 3325 | |
| 3326 | bool result = false; |
| 3327 | switch (UnsignedBits(cond, 3, 1)) |
| 3328 | { |
| 3329 | case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break; |
| 3330 | case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break; |
| 3331 | case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break; |
| 3332 | case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break; |
| 3333 | case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break; |
| 3334 | case 5: |
| 3335 | { |
| 3336 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 3337 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 3338 | result = n == v; |
| 3339 | } |
| 3340 | break; |
| 3341 | case 6: |
| 3342 | { |
| 3343 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 3344 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 3345 | result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0); |
| 3346 | } |
| 3347 | break; |
| 3348 | case 7: |
| 3349 | result = true; |
| 3350 | break; |
| 3351 | } |
| 3352 | |
| 3353 | if (cond & 1) |
| 3354 | result = !result; |
| 3355 | return result; |
| 3356 | } |
| 3357 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3358 | uint32_t |
| 3359 | EmulateInstructionARM::CurrentCond () |
| 3360 | { |
| 3361 | switch (m_inst_mode) |
| 3362 | { |
| 3363 | default: |
| 3364 | case eModeInvalid: |
| 3365 | break; |
| 3366 | |
| 3367 | case eModeARM: |
| 3368 | return UnsignedBits(m_inst.opcode.inst32, 31, 28); |
| 3369 | |
| 3370 | case eModeThumb: |
| 3371 | // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit |
| 3372 | // 'cond' field of the encoding. |
| 3373 | if (m_inst.opcode_type == eOpcode16 && |
| 3374 | Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d && |
| 3375 | Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f) |
| 3376 | { |
| 3377 | return Bits32(m_inst.opcode.inst16, 11, 7); |
| 3378 | } |
| 3379 | else if (m_inst.opcode_type == eOpcode32 && |
| 3380 | Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e && |
| 3381 | Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 && |
| 3382 | Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 && |
| 3383 | Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d) |
| 3384 | { |
| 3385 | return Bits32(m_inst.opcode.inst32, 25, 22); |
| 3386 | } |
| 3387 | |
| 3388 | return m_it_session.GetCond(); |
| 3389 | } |
| 3390 | return UINT32_MAX; // Return invalid value |
| 3391 | } |
| 3392 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3393 | bool |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 3394 | EmulateInstructionARM::InITBlock() |
| 3395 | { |
| 3396 | return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock(); |
| 3397 | } |
| 3398 | |
| 3399 | bool |
| 3400 | EmulateInstructionARM::LastInITBlock() |
| 3401 | { |
| 3402 | return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock(); |
| 3403 | } |
| 3404 | |
| 3405 | bool |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3406 | EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr) |
| 3407 | { |
| 3408 | addr_t target; |
| 3409 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3410 | // Check the current instruction set. |
| 3411 | if (CurrentInstrSet() == eModeARM) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3412 | target = addr & 0xfffffffc; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3413 | else |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3414 | target = addr & 0xfffffffe; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3415 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3416 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3417 | return false; |
| 3418 | |
| 3419 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3420 | } |
| 3421 | |
| 3422 | // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. |
| 3423 | bool |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3424 | EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register ®) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3425 | { |
| 3426 | addr_t target; |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3427 | // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, |
| 3428 | // we want to record it and issue a WriteRegister callback so the clients |
| 3429 | // can track the mode changes accordingly. |
| 3430 | bool cpsr_changed = false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3431 | |
| 3432 | if (BitIsSet(addr, 0)) |
| 3433 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3434 | if (CurrentInstrSet() != eModeThumb) |
| 3435 | { |
| 3436 | SelectInstrSet(eModeThumb); |
| 3437 | cpsr_changed = true; |
| 3438 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3439 | target = addr & 0xfffffffe; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3440 | context.SetModeAndRegister (eModeThumb, reg); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3441 | } |
| 3442 | else if (BitIsClear(addr, 1)) |
| 3443 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3444 | if (CurrentInstrSet() != eModeARM) |
| 3445 | { |
| 3446 | SelectInstrSet(eModeARM); |
| 3447 | cpsr_changed = true; |
| 3448 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3449 | target = addr & 0xfffffffc; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3450 | context.SetModeAndRegister (eModeARM, reg); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3451 | } |
| 3452 | else |
| 3453 | return false; // address<1:0> == '10' => UNPREDICTABLE |
| 3454 | |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3455 | if (cpsr_changed) |
| 3456 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3457 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 3458 | return false; |
| 3459 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3460 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 3461 | return false; |
| 3462 | |
| 3463 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 3464 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3465 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3466 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions. |
| 3467 | bool |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3468 | EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr, Register ®) |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3469 | { |
| 3470 | if (ArchVersion() >= ARMv5T) |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3471 | return BXWritePC(context, addr, reg); |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3472 | else |
| 3473 | return BranchWritePC((const Context)context, addr); |
| 3474 | } |
| 3475 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3476 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set. |
| 3477 | bool |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3478 | EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr, Register ®) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3479 | { |
| 3480 | if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3481 | return BXWritePC(context, addr, reg); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 3482 | else |
| 3483 | return BranchWritePC((const Context)context, addr); |
| 3484 | } |
| 3485 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3486 | EmulateInstructionARM::Mode |
| 3487 | EmulateInstructionARM::CurrentInstrSet () |
| 3488 | { |
| 3489 | return m_inst_mode; |
| 3490 | } |
| 3491 | |
| 3492 | // Set the 'T' bit of our CPSR. The m_inst_mode gets updated when the next |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3493 | // ReadInstruction() is performed. This function has a side effect of updating |
| 3494 | // the m_new_inst_cpsr member variable if necessary. |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3495 | bool |
| 3496 | EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb) |
| 3497 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3498 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3499 | switch (arm_or_thumb) |
| 3500 | { |
| 3501 | default: |
| 3502 | return false; |
| 3503 | eModeARM: |
| 3504 | // Clear the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3505 | m_new_inst_cpsr &= ~MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3506 | break; |
| 3507 | eModeThumb: |
| 3508 | // Set the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 3509 | m_new_inst_cpsr |= MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 3510 | break; |
| 3511 | } |
| 3512 | return true; |
| 3513 | } |
| 3514 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3515 | // This function returns TRUE if the processor currently provides support for |
| 3516 | // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7, |
| 3517 | // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6. |
| 3518 | bool |
| 3519 | EmulateInstructionARM::UnalignedSupport() |
| 3520 | { |
| 3521 | return (ArchVersion() >= ARMv7); |
| 3522 | } |
| 3523 | |
Johnny Chen | bf6ad17 | 2011-02-11 01:29:53 +0000 | [diff] [blame] | 3524 | // The main addition and subtraction instructions can produce status information |
| 3525 | // about both unsigned carry and signed overflow conditions. This status |
| 3526 | // information can be used to synthesize multi-word additions and subtractions. |
| 3527 | EmulateInstructionARM::AddWithCarryResult |
| 3528 | EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in) |
| 3529 | { |
| 3530 | uint32_t result; |
| 3531 | uint8_t carry_out; |
| 3532 | uint8_t overflow; |
| 3533 | |
| 3534 | uint64_t unsigned_sum = x + y + carry_in; |
| 3535 | int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in; |
| 3536 | |
| 3537 | result = UnsignedBits(unsigned_sum, 31, 0); |
| 3538 | carry_out = (result == unsigned_sum ? 0 : 1); |
| 3539 | overflow = ((int32_t)result == signed_sum ? 0 : 1); |
| 3540 | |
| 3541 | AddWithCarryResult res = { result, carry_out, overflow }; |
| 3542 | return res; |
| 3543 | } |
| 3544 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3545 | bool |
| 3546 | EmulateInstructionARM::EvaluateInstruction () |
| 3547 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 3548 | // Advance the ITSTATE bits to their values for the next instruction. |
| 3549 | if (m_inst_mode == eModeThumb && m_it_session.InITBlock()) |
| 3550 | m_it_session.ITAdvance(); |
| 3551 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 3552 | return false; |
| 3553 | } |