Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 10 | #include <stdlib.h> |
| 11 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 12 | #include "EmulateInstructionARM.h" |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 13 | #include "lldb/Core/ArchSpec.h" |
Greg Clayton | 8482ded | 2011-02-01 00:04:43 +0000 | [diff] [blame] | 14 | #include "lldb/Core/ConstString.h" |
| 15 | |
Greg Clayton | f29a08f | 2011-02-09 17:41:27 +0000 | [diff] [blame] | 16 | #include "Plugins/Process/Utility/ARMDefines.h" |
| 17 | #include "Plugins/Process/Utility/ARMUtils.h" |
| 18 | #include "Utility/ARM_DWARF_Registers.h" |
| 19 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 20 | #include "llvm/Support/MathExtras.h" // for SignExtend32 template function |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 21 | // and CountTrailingZeros_32 function |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace lldb; |
| 24 | using namespace lldb_private; |
| 25 | |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 26 | static inline uint32_t Align(uint32_t val, uint32_t alignment) |
| 27 | { |
| 28 | return alignment * (val / alignment); |
| 29 | } |
| 30 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 31 | //---------------------------------------------------------------------- |
| 32 | // |
| 33 | // ITSession implementation |
| 34 | // |
| 35 | //---------------------------------------------------------------------- |
| 36 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 37 | // A8.6.50 |
| 38 | // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition. |
| 39 | static unsigned short CountITSize(unsigned ITMask) { |
| 40 | // First count the trailing zeros of the IT mask. |
| 41 | unsigned TZ = llvm::CountTrailingZeros_32(ITMask); |
| 42 | if (TZ > 3) |
| 43 | { |
| 44 | printf("Encoding error: IT Mask '0000'\n"); |
| 45 | return 0; |
| 46 | } |
| 47 | return (4 - TZ); |
| 48 | } |
| 49 | |
| 50 | // Init ITState. Note that at least one bit is always 1 in mask. |
| 51 | bool ITSession::InitIT(unsigned short bits7_0) |
| 52 | { |
| 53 | ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); |
| 54 | if (ITCounter == 0) |
| 55 | return false; |
| 56 | |
| 57 | // A8.6.50 IT |
| 58 | unsigned short FirstCond = Bits32(bits7_0, 7, 4); |
| 59 | if (FirstCond == 0xF) |
| 60 | { |
| 61 | printf("Encoding error: IT FirstCond '1111'\n"); |
| 62 | return false; |
| 63 | } |
| 64 | if (FirstCond == 0xE && ITCounter != 1) |
| 65 | { |
| 66 | printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n"); |
| 67 | return false; |
| 68 | } |
| 69 | |
| 70 | ITState = bits7_0; |
| 71 | return true; |
| 72 | } |
| 73 | |
| 74 | // Update ITState if necessary. |
| 75 | void ITSession::ITAdvance() |
| 76 | { |
| 77 | assert(ITCounter); |
| 78 | --ITCounter; |
| 79 | if (ITCounter == 0) |
| 80 | ITState = 0; |
| 81 | else |
| 82 | { |
| 83 | unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; |
| 84 | SetBits32(ITState, 4, 0, NewITState4_0); |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | // Return true if we're inside an IT Block. |
| 89 | bool ITSession::InITBlock() |
| 90 | { |
| 91 | return ITCounter != 0; |
| 92 | } |
| 93 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 94 | // Return true if we're the last instruction inside an IT Block. |
| 95 | bool ITSession::LastInITBlock() |
| 96 | { |
| 97 | return ITCounter == 1; |
| 98 | } |
| 99 | |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 100 | // Get condition bits for the current thumb instruction. |
| 101 | uint32_t ITSession::GetCond() |
| 102 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 103 | if (InITBlock()) |
| 104 | return Bits32(ITState, 7, 4); |
| 105 | else |
| 106 | return COND_AL; |
Johnny Chen | 9307047 | 2011-02-04 23:02:47 +0000 | [diff] [blame] | 107 | } |
| 108 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 109 | // ARM constants used during decoding |
| 110 | #define REG_RD 0 |
| 111 | #define LDM_REGLIST 1 |
| 112 | #define PC_REG 15 |
| 113 | #define PC_REGLIST_BIT 0x8000 |
| 114 | |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 115 | #define ARMv4 (1u << 0) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 116 | #define ARMv4T (1u << 1) |
| 117 | #define ARMv5T (1u << 2) |
| 118 | #define ARMv5TE (1u << 3) |
| 119 | #define ARMv5TEJ (1u << 4) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 120 | #define ARMv6 (1u << 5) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 121 | #define ARMv6K (1u << 6) |
| 122 | #define ARMv6T2 (1u << 7) |
Johnny Chen | 251af6a | 2011-01-21 22:47:25 +0000 | [diff] [blame] | 123 | #define ARMv7 (1u << 8) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 124 | #define ARMv8 (1u << 9) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 125 | #define ARMvAll (0xffffffffu) |
| 126 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 127 | #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 128 | #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) |
| 129 | #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 130 | |
Johnny Chen | 0e00af2 | 2011-02-10 19:40:42 +0000 | [diff] [blame] | 131 | //---------------------------------------------------------------------- |
| 132 | // |
| 133 | // EmulateInstructionARM implementation |
| 134 | // |
| 135 | //---------------------------------------------------------------------- |
| 136 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 137 | void |
| 138 | EmulateInstructionARM::Initialize () |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 139 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 140 | } |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 141 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 142 | void |
| 143 | EmulateInstructionARM::Terminate () |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 144 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 147 | // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions. |
| 148 | bool |
| 149 | EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address) |
| 150 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 151 | EmulateInstruction::Context context; |
| 152 | context.type = EmulateInstruction::eContextWriteMemoryRandomBits; |
| 153 | context.SetNoArgs (); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 154 | |
| 155 | uint32_t random_data = rand (); |
| 156 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 157 | |
| 158 | if (!WriteMemoryUnsigned (context, address, random_data, addr_byte_size)) |
| 159 | return false; |
| 160 | |
| 161 | return true; |
| 162 | } |
| 163 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 164 | // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions. |
| 165 | bool |
| 166 | EmulateInstructionARM::WriteBits32Unknown (int n) |
| 167 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 168 | EmulateInstruction::Context context; |
| 169 | context.type = EmulateInstruction::eContextWriteRegisterRandomBits; |
| 170 | context.SetNoArgs (); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 171 | |
Johnny Chen | 62ff6f5 | 2011-02-11 18:11:22 +0000 | [diff] [blame] | 172 | bool success; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 173 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 174 | |
| 175 | if (!success) |
| 176 | return false; |
| 177 | |
| 178 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 179 | return false; |
| 180 | |
| 181 | return true; |
| 182 | } |
| 183 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 184 | // Push Multiple Registers stores multiple registers to the stack, storing to |
| 185 | // consecutive memory locations ending just below the address in SP, and updates |
| 186 | // SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 187 | bool |
| 188 | EmulateInstructionARM::EmulatePush (ARMEncoding encoding) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 189 | { |
| 190 | #if 0 |
| 191 | // ARM pseudo code... |
| 192 | if (ConditionPassed()) |
| 193 | { |
| 194 | EncodingSpecificOperations(); |
| 195 | NullCheckIfThumbEE(13); |
| 196 | address = SP - 4*BitCount(registers); |
| 197 | |
| 198 | for (i = 0 to 14) |
| 199 | { |
| 200 | if (registers<i> == ’1’) |
| 201 | { |
| 202 | if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 |
| 203 | MemA[address,4] = bits(32) UNKNOWN; |
| 204 | else |
| 205 | MemA[address,4] = R[i]; |
| 206 | address = address + 4; |
| 207 | } |
| 208 | } |
| 209 | |
| 210 | if (registers<15> == ’1’) // Only possible for encoding A1 or A2 |
| 211 | MemA[address,4] = PCStoreValue(); |
| 212 | |
| 213 | SP = SP - 4*BitCount(registers); |
| 214 | } |
| 215 | #endif |
| 216 | |
| 217 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 218 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 219 | if (!success) |
| 220 | return false; |
| 221 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 222 | if (ConditionPassed()) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 223 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 224 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 225 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 226 | if (!success) |
| 227 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 228 | uint32_t registers = 0; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 229 | uint32_t Rt; // the source register |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 230 | switch (encoding) { |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 231 | case eEncodingT1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 232 | registers = Bits32(opcode, 7, 0); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 233 | // The M bit represents LR. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 234 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 235 | registers |= (1u << 14); |
Johnny Chen | aedde1c | 2011-01-24 20:38:45 +0000 | [diff] [blame] | 236 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 237 | if (BitCount(registers) < 1) |
| 238 | return false; |
| 239 | break; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 240 | case eEncodingT2: |
| 241 | // Ignore bits 15 & 13. |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 242 | registers = Bits32(opcode, 15, 0) & ~0xa000; |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 243 | // if BitCount(registers) < 2 then UNPREDICTABLE; |
| 244 | if (BitCount(registers) < 2) |
| 245 | return false; |
| 246 | break; |
| 247 | case eEncodingT3: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 248 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 249 | // if BadReg(t) then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 250 | if (BadReg(Rt)) |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 251 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 252 | registers = (1u << Rt); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 253 | break; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 254 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 255 | registers = Bits32(opcode, 15, 0); |
Johnny Chen | a33d484 | 2011-01-24 22:25:48 +0000 | [diff] [blame] | 256 | // Instead of return false, let's handle the following case as well, |
| 257 | // which amounts to pushing one reg onto the full descending stacks. |
| 258 | // if BitCount(register_list) < 2 then SEE STMDB / STMFD; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 259 | break; |
| 260 | case eEncodingA2: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 261 | Rt = Bits32(opcode, 15, 12); |
Johnny Chen | 7dc60e1 | 2011-01-24 19:46:32 +0000 | [diff] [blame] | 262 | // if t == 13 then UNPREDICTABLE; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 263 | if (Rt == dwarf_sp) |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 264 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 265 | registers = (1u << Rt); |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 266 | break; |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 267 | default: |
| 268 | return false; |
Johnny Chen | 3c75c76 | 2011-01-22 00:47:08 +0000 | [diff] [blame] | 269 | } |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 270 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 271 | addr_t addr = sp - sp_offset; |
| 272 | uint32_t i; |
| 273 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 274 | EmulateInstruction::Context context; |
| 275 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 276 | Register dwarf_reg; |
| 277 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 278 | for (i=0; i<15; ++i) |
| 279 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 280 | if (BitIsSet (registers, i)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 281 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 282 | dwarf_reg.num = dwarf_r0 + i; |
| 283 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
| 284 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 285 | if (!success) |
| 286 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 287 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 288 | return false; |
| 289 | addr += addr_byte_size; |
| 290 | } |
| 291 | } |
| 292 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 293 | if (BitIsSet (registers, 15)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 294 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 295 | dwarf_reg.num = dwarf_pc; |
| 296 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 297 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 298 | if (!success) |
| 299 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 300 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 301 | return false; |
| 302 | } |
| 303 | |
| 304 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 305 | context.SetImmediateSigned (-sp_offset); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 306 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 307 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 308 | return false; |
| 309 | } |
| 310 | return true; |
| 311 | } |
| 312 | |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 313 | // Pop Multiple Registers loads multiple registers from the stack, loading from |
| 314 | // consecutive memory locations staring at the address in SP, and updates |
| 315 | // SP to point just above the loaded data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 316 | bool |
| 317 | EmulateInstructionARM::EmulatePop (ARMEncoding encoding) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 318 | { |
| 319 | #if 0 |
| 320 | // ARM pseudo code... |
| 321 | if (ConditionPassed()) |
| 322 | { |
| 323 | EncodingSpecificOperations(); NullCheckIfThumbEE(13); |
| 324 | address = SP; |
| 325 | for i = 0 to 14 |
| 326 | if registers<i> == ‘1’ then |
| 327 | R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; |
| 328 | if registers<15> == ‘1’ then |
| 329 | if UnalignedAllowed then |
| 330 | LoadWritePC(MemU[address,4]); |
| 331 | else |
| 332 | LoadWritePC(MemA[address,4]); |
| 333 | if registers<13> == ‘0’ then SP = SP + 4*BitCount(registers); |
| 334 | if registers<13> == ‘1’ then SP = bits(32) UNKNOWN; |
| 335 | } |
| 336 | #endif |
| 337 | |
| 338 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 339 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 340 | if (!success) |
| 341 | return false; |
| 342 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 343 | if (ConditionPassed()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 344 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 345 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 346 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 347 | if (!success) |
| 348 | return false; |
| 349 | uint32_t registers = 0; |
| 350 | uint32_t Rt; // the destination register |
| 351 | switch (encoding) { |
| 352 | case eEncodingT1: |
| 353 | registers = Bits32(opcode, 7, 0); |
| 354 | // The P bit represents PC. |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 355 | if (Bit32(opcode, 8)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 356 | registers |= (1u << 15); |
| 357 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 358 | if (BitCount(registers) < 1) |
| 359 | return false; |
| 360 | break; |
| 361 | case eEncodingT2: |
| 362 | // Ignore bit 13. |
| 363 | registers = Bits32(opcode, 15, 0) & ~0x2000; |
| 364 | // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 365 | if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 366 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 367 | // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
| 368 | if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock()) |
| 369 | return false; |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 370 | break; |
| 371 | case eEncodingT3: |
| 372 | Rt = Bits32(opcode, 15, 12); |
| 373 | // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 374 | if (Rt == 13) |
| 375 | return false; |
| 376 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 377 | return false; |
| 378 | registers = (1u << Rt); |
| 379 | break; |
| 380 | case eEncodingA1: |
| 381 | registers = Bits32(opcode, 15, 0); |
| 382 | // Instead of return false, let's handle the following case as well, |
| 383 | // which amounts to popping one reg from the full descending stacks. |
| 384 | // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; |
| 385 | |
| 386 | // if registers<13> == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 387 | if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 388 | return false; |
| 389 | break; |
| 390 | case eEncodingA2: |
| 391 | Rt = Bits32(opcode, 15, 12); |
| 392 | // if t == 13 then UNPREDICTABLE; |
| 393 | if (Rt == dwarf_sp) |
| 394 | return false; |
| 395 | registers = (1u << Rt); |
| 396 | break; |
| 397 | default: |
| 398 | return false; |
| 399 | } |
| 400 | addr_t sp_offset = addr_byte_size * BitCount (registers); |
| 401 | addr_t addr = sp; |
| 402 | uint32_t i, data; |
| 403 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 404 | EmulateInstruction::Context context; |
| 405 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 406 | Register dwarf_reg; |
| 407 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 408 | for (i=0; i<15; ++i) |
| 409 | { |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 410 | if (BitIsSet (registers, i)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 411 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 412 | dwarf_reg.num = dwarf_r0 + i; |
| 413 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 414 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 415 | if (!success) |
| 416 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 417 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 418 | return false; |
| 419 | addr += addr_byte_size; |
| 420 | } |
| 421 | } |
| 422 | |
Johnny Chen | 7c1bf92 | 2011-02-08 23:49:37 +0000 | [diff] [blame] | 423 | if (BitIsSet (registers, 15)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 424 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 425 | dwarf_reg.num = dwarf_pc; |
| 426 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 427 | data = ReadMemoryUnsigned(context, addr, 4, 0, &success); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 428 | if (!success) |
| 429 | return false; |
Johnny Chen | f3eaacf | 2011-02-09 19:30:49 +0000 | [diff] [blame] | 430 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 431 | if (!LoadWritePC(context, data)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 432 | return false; |
| 433 | addr += addr_byte_size; |
| 434 | } |
| 435 | |
| 436 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 437 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 438 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 439 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 440 | return false; |
| 441 | } |
| 442 | return true; |
| 443 | } |
| 444 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 445 | // Set r7 or ip to point to saved value residing within the stack. |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 446 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 447 | bool |
| 448 | EmulateInstructionARM::EmulateAddRdSPImmediate (ARMEncoding encoding) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 449 | { |
| 450 | #if 0 |
| 451 | // ARM pseudo code... |
| 452 | if (ConditionPassed()) |
| 453 | { |
| 454 | EncodingSpecificOperations(); |
| 455 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 456 | if d == 15 then |
| 457 | ALUWritePC(result); // setflags is always FALSE here |
| 458 | else |
| 459 | R[d] = result; |
| 460 | if setflags then |
| 461 | APSR.N = result<31>; |
| 462 | APSR.Z = IsZeroBit(result); |
| 463 | APSR.C = carry; |
| 464 | APSR.V = overflow; |
| 465 | } |
| 466 | #endif |
| 467 | |
| 468 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 469 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 470 | if (!success) |
| 471 | return false; |
| 472 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 473 | if (ConditionPassed()) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 474 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 475 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 476 | if (!success) |
| 477 | return false; |
| 478 | uint32_t Rd; // the destination register |
| 479 | uint32_t imm32; |
| 480 | switch (encoding) { |
| 481 | case eEncodingT1: |
| 482 | Rd = 7; |
| 483 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) |
| 484 | break; |
| 485 | case eEncodingA1: |
| 486 | Rd = Bits32(opcode, 15, 12); |
| 487 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 488 | break; |
| 489 | default: |
| 490 | return false; |
| 491 | } |
| 492 | addr_t sp_offset = imm32; |
| 493 | addr_t addr = sp + sp_offset; // a pointer to the stack area |
| 494 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 495 | EmulateInstruction::Context context; |
| 496 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 497 | Register sp_reg; |
| 498 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 499 | context.SetRegisterPlusOffset (sp_reg, sp_offset); |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 500 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 501 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr)) |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 502 | return false; |
| 503 | } |
| 504 | return true; |
| 505 | } |
| 506 | |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 507 | // Set r7 or ip to the current stack pointer. |
| 508 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 509 | bool |
| 510 | EmulateInstructionARM::EmulateMovRdSP (ARMEncoding encoding) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 511 | { |
| 512 | #if 0 |
| 513 | // ARM pseudo code... |
| 514 | if (ConditionPassed()) |
| 515 | { |
| 516 | EncodingSpecificOperations(); |
| 517 | result = R[m]; |
| 518 | if d == 15 then |
| 519 | ALUWritePC(result); // setflags is always FALSE here |
| 520 | else |
| 521 | R[d] = result; |
| 522 | if setflags then |
| 523 | APSR.N = result<31>; |
| 524 | APSR.Z = IsZeroBit(result); |
| 525 | // APSR.C unchanged |
| 526 | // APSR.V unchanged |
| 527 | } |
| 528 | #endif |
| 529 | |
| 530 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 531 | //const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 532 | //if (!success) |
| 533 | // return false; |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 534 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 535 | if (ConditionPassed()) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 536 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 537 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 538 | if (!success) |
| 539 | return false; |
| 540 | uint32_t Rd; // the destination register |
| 541 | switch (encoding) { |
| 542 | case eEncodingT1: |
| 543 | Rd = 7; |
| 544 | break; |
| 545 | case eEncodingA1: |
| 546 | Rd = 12; |
| 547 | break; |
| 548 | default: |
| 549 | return false; |
| 550 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 551 | |
| 552 | EmulateInstruction::Context context; |
| 553 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 554 | Register sp_reg; |
| 555 | sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 556 | context.SetRegisterPlusOffset (sp_reg, 0); |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 557 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 558 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) |
Johnny Chen | 2ccad83 | 2011-01-28 19:57:25 +0000 | [diff] [blame] | 559 | return false; |
| 560 | } |
| 561 | return true; |
| 562 | } |
| 563 | |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 564 | // Move from high register (r8-r15) to low register (r0-r7). |
| 565 | // MOV (register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 566 | bool |
| 567 | EmulateInstructionARM::EmulateMovLowHigh (ARMEncoding encoding) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 568 | { |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 569 | return EmulateMovRdRm (encoding); |
| 570 | } |
| 571 | |
| 572 | // Move from register to register. |
| 573 | // MOV (register) |
| 574 | bool |
| 575 | EmulateInstructionARM::EmulateMovRdRm (ARMEncoding encoding) |
| 576 | { |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 577 | #if 0 |
| 578 | // ARM pseudo code... |
| 579 | if (ConditionPassed()) |
| 580 | { |
| 581 | EncodingSpecificOperations(); |
| 582 | result = R[m]; |
| 583 | if d == 15 then |
| 584 | ALUWritePC(result); // setflags is always FALSE here |
| 585 | else |
| 586 | R[d] = result; |
| 587 | if setflags then |
| 588 | APSR.N = result<31>; |
| 589 | APSR.Z = IsZeroBit(result); |
| 590 | // APSR.C unchanged |
| 591 | // APSR.V unchanged |
| 592 | } |
| 593 | #endif |
| 594 | |
| 595 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 596 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 597 | if (!success) |
| 598 | return false; |
| 599 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 600 | if (ConditionPassed()) |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 601 | { |
| 602 | uint32_t Rm; // the source register |
| 603 | uint32_t Rd; // the destination register |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 604 | bool setflags; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 605 | switch (encoding) { |
| 606 | case eEncodingT1: |
| 607 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 608 | Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 1); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 609 | setflags = false; |
| 610 | break; |
| 611 | case eEncodingT2: |
| 612 | Rm = Bits32(opcode, 5, 3); |
| 613 | Rd = Bits32(opcode, 2, 1); |
| 614 | setflags = true; |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 615 | break; |
| 616 | default: |
| 617 | return false; |
| 618 | } |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 619 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 620 | if (!success) |
| 621 | return false; |
| 622 | |
| 623 | // The context specifies that Rm is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 624 | EmulateInstruction::Context context; |
| 625 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 626 | Register dwarf_reg; |
| 627 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 628 | context.SetRegisterPlusOffset (dwarf_reg, 0); |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 629 | |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 630 | if (Rd == 15) |
| 631 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 632 | if (!ALUWritePC (context, reg_value)) |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 633 | return false; |
| 634 | } |
| 635 | else |
| 636 | { |
| 637 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, reg_value)) |
| 638 | return false; |
| 639 | if (setflags) |
| 640 | { |
| 641 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 642 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(reg_value, CPSR_N)); |
| 643 | SetBit32(m_new_inst_cpsr, CPSR_Z, reg_value == 0 ? 1 : 0); |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 644 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 645 | { |
| 646 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 647 | return false; |
| 648 | } |
| 649 | } |
| 650 | } |
Johnny Chen | 1c13b62 | 2011-01-29 00:11:15 +0000 | [diff] [blame] | 651 | } |
| 652 | return true; |
| 653 | } |
| 654 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 655 | // Move (immediate) writes an immediate value to the destination register. It |
| 656 | // can optionally update the condition flags based on the value. |
| 657 | // MOV (immediate) |
| 658 | bool |
| 659 | EmulateInstructionARM::EmulateMovRdImm (ARMEncoding encoding) |
| 660 | { |
| 661 | #if 0 |
| 662 | // ARM pseudo code... |
| 663 | if (ConditionPassed()) |
| 664 | { |
| 665 | EncodingSpecificOperations(); |
| 666 | result = imm32; |
| 667 | if d == 15 then // Can only occur for ARM encoding |
| 668 | ALUWritePC(result); // setflags is always FALSE here |
| 669 | else |
| 670 | R[d] = result; |
| 671 | if setflags then |
| 672 | APSR.N = result<31>; |
| 673 | APSR.Z = IsZeroBit(result); |
| 674 | APSR.C = carry; |
| 675 | // APSR.V unchanged |
| 676 | } |
| 677 | #endif |
| 678 | bool success = false; |
| 679 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 680 | if (!success) |
| 681 | return false; |
| 682 | |
| 683 | if (ConditionPassed()) |
| 684 | { |
| 685 | uint32_t Rd; // the destination register |
| 686 | uint32_t imm12; // some intermediate result |
| 687 | uint32_t imm32; // the immediate value to be written to Rd |
| 688 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C. |
| 689 | bool setflags; |
| 690 | switch (encoding) { |
| 691 | case eEncodingT1: |
| 692 | Rd = Bits32(opcode, 11, 8); |
| 693 | setflags = !InITBlock(); |
| 694 | imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) |
| 695 | carry = Bit32(m_inst_cpsr, CPSR_C); |
| 696 | break; |
| 697 | case eEncodingT2: |
| 698 | Rd = Bits32(opcode, 15, 12); |
| 699 | setflags = BitIsSet(opcode, 20); |
| 700 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
| 701 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
Johnny Chen | 9798cfc | 2011-02-14 23:33:58 +0000 | [diff] [blame] | 702 | if (BadReg(Rd)) |
| 703 | return false; |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 704 | break; |
| 705 | default: |
| 706 | return false; |
| 707 | } |
| 708 | uint32_t result = imm32; |
| 709 | |
| 710 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 711 | EmulateInstruction::Context context; |
| 712 | context.type = EmulateInstruction::eContextImmediate; |
| 713 | context.SetNoArgs (); |
| 714 | |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 715 | if (Rd == 15) |
| 716 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 717 | if (!ALUWritePC (context, result)) |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 718 | return false; |
| 719 | } |
| 720 | else |
| 721 | { |
| 722 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 723 | return false; |
| 724 | if (setflags) |
| 725 | { |
| 726 | m_new_inst_cpsr = m_inst_cpsr; |
| 727 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 728 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 729 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 730 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 731 | { |
| 732 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 733 | return false; |
| 734 | } |
| 735 | } |
| 736 | } |
| 737 | } |
| 738 | return true; |
| 739 | } |
| 740 | |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 741 | // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to |
| 742 | // the destination register. It can optionally update the condition flags based |
| 743 | // on the value. |
| 744 | // MVN (immediate) |
| 745 | bool |
| 746 | EmulateInstructionARM::EmulateMvnRdImm (ARMEncoding encoding) |
| 747 | { |
| 748 | #if 0 |
| 749 | // ARM pseudo code... |
| 750 | if (ConditionPassed()) |
| 751 | { |
| 752 | EncodingSpecificOperations(); |
| 753 | result = NOT(imm32); |
| 754 | if d == 15 then // Can only occur for ARM encoding |
| 755 | ALUWritePC(result); // setflags is always FALSE here |
| 756 | else |
| 757 | R[d] = result; |
| 758 | if setflags then |
| 759 | APSR.N = result<31>; |
| 760 | APSR.Z = IsZeroBit(result); |
| 761 | APSR.C = carry; |
| 762 | // APSR.V unchanged |
| 763 | } |
| 764 | #endif |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 765 | bool success = false; |
| 766 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 767 | if (!success) |
| 768 | return false; |
| 769 | |
| 770 | if (ConditionPassed()) |
| 771 | { |
| 772 | uint32_t Rd; // the destination register |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 773 | uint32_t imm12; // the first operand to ThumbExpandImm_C or ARMExpandImm_C |
| 774 | uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C |
| 775 | uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 776 | bool setflags; |
| 777 | switch (encoding) { |
| 778 | case eEncodingT1: |
| 779 | Rd = Bits32(opcode, 11, 8); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 780 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 781 | imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 782 | imm32 = ThumbExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 783 | break; |
| 784 | case eEncodingA1: |
| 785 | Rd = Bits32(opcode, 15, 12); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 786 | setflags = BitIsSet(opcode, 20); |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 787 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 788 | imm32 = ARMExpandImm_C(imm12, Bit32(m_inst_cpsr, CPSR_C), carry); |
| 789 | break; |
| 790 | default: |
| 791 | return false; |
| 792 | } |
| 793 | uint32_t result = ~imm32; |
| 794 | |
| 795 | // The context specifies that an immediate is to be moved into Rd. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 796 | EmulateInstruction::Context context; |
| 797 | context.type = EmulateInstruction::eContextImmediate; |
| 798 | context.SetNoArgs (); |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 799 | |
| 800 | if (Rd == 15) |
| 801 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 802 | if (!ALUWritePC (context, result)) |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 803 | return false; |
| 804 | } |
| 805 | else |
| 806 | { |
| 807 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 808 | return false; |
| 809 | if (setflags) |
| 810 | { |
| 811 | m_new_inst_cpsr = m_inst_cpsr; |
| 812 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 813 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 814 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 815 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 816 | { |
| 817 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 818 | return false; |
| 819 | } |
| 820 | } |
| 821 | } |
| 822 | } |
| 823 | return true; |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 824 | } |
| 825 | |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 826 | // PC relative immediate load into register, possibly followed by ADD (SP plus register). |
| 827 | // LDR (literal) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 828 | bool |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 829 | EmulateInstructionARM::EmulateLDRRtPCRelative (ARMEncoding encoding) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 830 | { |
| 831 | #if 0 |
| 832 | // ARM pseudo code... |
| 833 | if (ConditionPassed()) |
| 834 | { |
| 835 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 836 | base = Align(PC,4); |
| 837 | address = if add then (base + imm32) else (base - imm32); |
| 838 | data = MemU[address,4]; |
| 839 | if t == 15 then |
| 840 | if address<1:0> == ‘00’ then LoadWritePC(data); else UNPREDICTABLE; |
| 841 | elsif UnalignedSupport() || address<1:0> = ‘00’ then |
| 842 | R[t] = data; |
| 843 | else // Can only apply before ARMv7 |
| 844 | if CurrentInstrSet() == InstrSet_ARM then |
| 845 | R[t] = ROR(data, 8*UInt(address<1:0>)); |
| 846 | else |
| 847 | R[t] = bits(32) UNKNOWN; |
| 848 | } |
| 849 | #endif |
| 850 | |
| 851 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 852 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 853 | if (!success) |
| 854 | return false; |
| 855 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 856 | if (ConditionPassed()) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 857 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 858 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 859 | if (!success) |
| 860 | return false; |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 861 | |
| 862 | // PC relative immediate load context |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 863 | EmulateInstruction::Context context; |
| 864 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 865 | Register pc_reg; |
| 866 | pc_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC); |
| 867 | context.SetRegisterPlusOffset (pc_reg, 0); |
| 868 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 869 | uint32_t Rt; // the destination register |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 870 | uint32_t imm32; // immediate offset from the PC |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 871 | bool add; // +imm32 or -imm32? |
| 872 | addr_t base; // the base address |
| 873 | addr_t address; // the PC relative address |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 874 | uint32_t data; // the literal data value from the PC relative load |
| 875 | switch (encoding) { |
| 876 | case eEncodingT1: |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 877 | Rt = Bits32(opcode, 10, 8); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 878 | imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 879 | add = true; |
| 880 | base = Align(pc + 4, 4); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 881 | context.SetRegisterPlusOffset (pc_reg, 4 + imm32); |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 882 | break; |
| 883 | case eEncodingT2: |
| 884 | Rt = Bits32(opcode, 15, 12); |
| 885 | imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); |
| 886 | add = BitIsSet(opcode, 23); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 887 | if (Rt == 15 && InITBlock() && !LastInITBlock()) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 888 | return false; |
| 889 | base = Align(pc + 4, 4); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 890 | context.SetRegisterPlusOffset (pc_reg, 4 + imm32); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 891 | break; |
| 892 | default: |
| 893 | return false; |
| 894 | } |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 895 | |
| 896 | if (add) |
| 897 | address = base + imm32; |
| 898 | else |
| 899 | address = base - imm32; |
| 900 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 901 | if (!success) |
Johnny Chen | 809742e | 2011-01-28 00:32:27 +0000 | [diff] [blame] | 902 | return false; |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 903 | |
| 904 | if (Rt == 15) |
| 905 | { |
| 906 | if (Bits32(address, 1, 0) == 0) |
| 907 | { |
| 908 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 909 | if (!LoadWritePC(context, data)) |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 910 | return false; |
| 911 | } |
| 912 | else |
| 913 | return false; |
| 914 | } |
| 915 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 916 | { |
| 917 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 918 | return false; |
| 919 | } |
| 920 | else // We don't handle ARM for now. |
| 921 | return false; |
| 922 | |
| 923 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 924 | return false; |
| 925 | } |
| 926 | return true; |
| 927 | } |
| 928 | |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 929 | // An add operation to adjust the SP. |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 930 | // ADD (SP plus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 931 | bool |
| 932 | EmulateInstructionARM::EmulateAddSPImmediate (ARMEncoding encoding) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 933 | { |
| 934 | #if 0 |
| 935 | // ARM pseudo code... |
| 936 | if (ConditionPassed()) |
| 937 | { |
| 938 | EncodingSpecificOperations(); |
| 939 | (result, carry, overflow) = AddWithCarry(SP, imm32, ‘0’); |
| 940 | if d == 15 then // Can only occur for ARM encoding |
| 941 | ALUWritePC(result); // setflags is always FALSE here |
| 942 | else |
| 943 | R[d] = result; |
| 944 | if setflags then |
| 945 | APSR.N = result<31>; |
| 946 | APSR.Z = IsZeroBit(result); |
| 947 | APSR.C = carry; |
| 948 | APSR.V = overflow; |
| 949 | } |
| 950 | #endif |
| 951 | |
| 952 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 953 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 954 | if (!success) |
| 955 | return false; |
| 956 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 957 | if (ConditionPassed()) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 958 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 959 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 960 | if (!success) |
| 961 | return false; |
| 962 | uint32_t imm32; // the immediate operand |
| 963 | switch (encoding) { |
| 964 | case eEncodingT2: |
| 965 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
| 966 | break; |
| 967 | default: |
| 968 | return false; |
| 969 | } |
| 970 | addr_t sp_offset = imm32; |
| 971 | addr_t addr = sp + sp_offset; // the adjusted stack pointer value |
| 972 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 973 | EmulateInstruction::Context context; |
| 974 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 975 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 976 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 977 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 978 | return false; |
| 979 | } |
| 980 | return true; |
| 981 | } |
| 982 | |
| 983 | // An add operation to adjust the SP. |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 984 | // ADD (SP plus register) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 985 | bool |
| 986 | EmulateInstructionARM::EmulateAddSPRm (ARMEncoding encoding) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 987 | { |
| 988 | #if 0 |
| 989 | // ARM pseudo code... |
| 990 | if (ConditionPassed()) |
| 991 | { |
| 992 | EncodingSpecificOperations(); |
| 993 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 994 | (result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’); |
| 995 | if d == 15 then |
| 996 | ALUWritePC(result); // setflags is always FALSE here |
| 997 | else |
| 998 | R[d] = result; |
| 999 | if setflags then |
| 1000 | APSR.N = result<31>; |
| 1001 | APSR.Z = IsZeroBit(result); |
| 1002 | APSR.C = carry; |
| 1003 | APSR.V = overflow; |
| 1004 | } |
| 1005 | #endif |
| 1006 | |
| 1007 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1008 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1009 | if (!success) |
| 1010 | return false; |
| 1011 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1012 | if (ConditionPassed()) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1013 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1014 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1015 | if (!success) |
| 1016 | return false; |
| 1017 | uint32_t Rm; // the second operand |
| 1018 | switch (encoding) { |
| 1019 | case eEncodingT2: |
| 1020 | Rm = Bits32(opcode, 6, 3); |
| 1021 | break; |
| 1022 | default: |
| 1023 | return false; |
| 1024 | } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1025 | int32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1026 | if (!success) |
| 1027 | return false; |
| 1028 | |
| 1029 | addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value |
| 1030 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1031 | EmulateInstruction::Context context; |
| 1032 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1033 | context.SetImmediateSigned (reg_value); |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1034 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1035 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 5b442b7 | 2011-01-27 19:34:30 +0000 | [diff] [blame] | 1036 | return false; |
| 1037 | } |
| 1038 | return true; |
| 1039 | } |
| 1040 | |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1041 | // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine |
| 1042 | // at a PC-relative address, and changes instruction set from ARM to Thumb, or |
| 1043 | // from Thumb to ARM. |
| 1044 | // BLX (immediate) |
| 1045 | bool |
| 1046 | EmulateInstructionARM::EmulateBLXImmediate (ARMEncoding encoding) |
| 1047 | { |
| 1048 | #if 0 |
| 1049 | // ARM pseudo code... |
| 1050 | if (ConditionPassed()) |
| 1051 | { |
| 1052 | EncodingSpecificOperations(); |
| 1053 | if CurrentInstrSet() == InstrSet_ARM then |
| 1054 | LR = PC - 4; |
| 1055 | else |
| 1056 | LR = PC<31:1> : '1'; |
| 1057 | if targetInstrSet == InstrSet_ARM then |
| 1058 | targetAddress = Align(PC,4) + imm32; |
| 1059 | else |
| 1060 | targetAddress = PC + imm32; |
| 1061 | SelectInstrSet(targetInstrSet); |
| 1062 | BranchWritePC(targetAddress); |
| 1063 | } |
| 1064 | #endif |
| 1065 | |
| 1066 | bool success = false; |
| 1067 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1068 | if (!success) |
| 1069 | return false; |
| 1070 | |
| 1071 | if (ConditionPassed()) |
| 1072 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1073 | EmulateInstruction::Context context; |
| 1074 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1075 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1076 | if (!success) |
| 1077 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1078 | addr_t lr; // next instruction address |
| 1079 | addr_t target; // target address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1080 | int32_t imm32; // PC-relative offset |
| 1081 | switch (encoding) { |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1082 | case eEncodingT1: |
| 1083 | { |
| 1084 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1085 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1086 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1087 | uint32_t J1 = Bit32(opcode, 13); |
| 1088 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1089 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1090 | uint32_t I1 = !(J1 ^ S); |
| 1091 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1092 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1093 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1094 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1095 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1096 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1097 | return false; |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1098 | break; |
| 1099 | } |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1100 | case eEncodingT2: |
| 1101 | { |
| 1102 | lr = (pc + 4) | 1u; // return address |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1103 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1104 | uint32_t imm10H = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1105 | uint32_t J1 = Bit32(opcode, 13); |
| 1106 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1107 | uint32_t imm10L = Bits32(opcode, 10, 1); |
| 1108 | uint32_t I1 = !(J1 ^ S); |
| 1109 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1110 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1111 | imm32 = llvm::SignExtend32<25>(imm25); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1112 | target = Align(pc + 4, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1113 | context.SetModeAndImmediateSigned (eModeARM, 4 + imm32); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1114 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1115 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1116 | break; |
| 1117 | } |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1118 | case eEncodingA1: |
| 1119 | lr = pc + 4; // return address |
| 1120 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 1121 | target = Align(pc + 8, 4) + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1122 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | c47d0ca | 2011-02-08 18:58:31 +0000 | [diff] [blame] | 1123 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1124 | case eEncodingA2: |
| 1125 | lr = pc + 4; // return address |
| 1126 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1); |
| 1127 | target = pc + 8 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1128 | context.SetModeAndImmediateSigned (eModeThumb, 8 + imm32); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1129 | break; |
| 1130 | default: |
| 1131 | return false; |
| 1132 | } |
| 1133 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1134 | return false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1135 | if (!BranchWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1136 | return false; |
| 1137 | } |
| 1138 | return true; |
| 1139 | } |
| 1140 | |
| 1141 | // Branch with Link and Exchange (register) calls a subroutine at an address and |
| 1142 | // instruction set specified by a register. |
| 1143 | // BLX (register) |
| 1144 | bool |
| 1145 | EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding) |
| 1146 | { |
| 1147 | #if 0 |
| 1148 | // ARM pseudo code... |
| 1149 | if (ConditionPassed()) |
| 1150 | { |
| 1151 | EncodingSpecificOperations(); |
| 1152 | target = R[m]; |
| 1153 | if CurrentInstrSet() == InstrSet_ARM then |
| 1154 | next_instr_addr = PC - 4; |
| 1155 | LR = next_instr_addr; |
| 1156 | else |
| 1157 | next_instr_addr = PC - 2; |
| 1158 | LR = next_instr_addr<31:1> : ‘1’; |
| 1159 | BXWritePC(target); |
| 1160 | } |
| 1161 | #endif |
| 1162 | |
| 1163 | bool success = false; |
| 1164 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1165 | if (!success) |
| 1166 | return false; |
| 1167 | |
| 1168 | if (ConditionPassed()) |
| 1169 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1170 | EmulateInstruction::Context context; |
| 1171 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1172 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1173 | addr_t lr; // next instruction address |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1174 | if (!success) |
| 1175 | return false; |
| 1176 | uint32_t Rm; // the register with the target address |
| 1177 | switch (encoding) { |
| 1178 | case eEncodingT1: |
| 1179 | lr = (pc + 2) | 1u; // return address |
| 1180 | Rm = Bits32(opcode, 6, 3); |
| 1181 | // if m == 15 then UNPREDICTABLE; |
| 1182 | if (Rm == 15) |
| 1183 | return false; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1184 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1185 | return false; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1186 | break; |
| 1187 | case eEncodingA1: |
| 1188 | lr = pc + 4; // return address |
| 1189 | Rm = Bits32(opcode, 3, 0); |
| 1190 | // if m == 15 then UNPREDICTABLE; |
| 1191 | if (Rm == 15) |
| 1192 | return false; |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1193 | break; |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1194 | default: |
| 1195 | return false; |
| 1196 | } |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1197 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1198 | if (!success) |
| 1199 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1200 | Register dwarf_reg; |
| 1201 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
| 1202 | context.SetRegister (dwarf_reg); |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1203 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1204 | return false; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1205 | if (!BXWritePC(context, target)) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 1206 | return false; |
| 1207 | } |
| 1208 | return true; |
| 1209 | } |
| 1210 | |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1211 | // Branch and Exchange causes a branch to an address and instruction set specified by a register. |
| 1212 | // BX |
| 1213 | bool |
| 1214 | EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding) |
| 1215 | { |
| 1216 | #if 0 |
| 1217 | // ARM pseudo code... |
| 1218 | if (ConditionPassed()) |
| 1219 | { |
| 1220 | EncodingSpecificOperations(); |
| 1221 | BXWritePC(R[m]); |
| 1222 | } |
| 1223 | #endif |
| 1224 | |
| 1225 | bool success = false; |
| 1226 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1227 | if (!success) |
| 1228 | return false; |
| 1229 | |
| 1230 | if (ConditionPassed()) |
| 1231 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1232 | EmulateInstruction::Context context; |
| 1233 | context.type = EmulateInstruction::eContextAbsoluteBranchRegister; |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1234 | uint32_t Rm; // the register with the target address |
| 1235 | switch (encoding) { |
| 1236 | case eEncodingT1: |
| 1237 | Rm = Bits32(opcode, 6, 3); |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 1238 | if (InITBlock() && !LastInITBlock()) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1239 | return false; |
| 1240 | break; |
| 1241 | case eEncodingA1: |
| 1242 | Rm = Bits32(opcode, 3, 0); |
| 1243 | break; |
| 1244 | default: |
| 1245 | return false; |
| 1246 | } |
| 1247 | addr_t target = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1248 | if (!success) |
| 1249 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1250 | |
| 1251 | Register dwarf_reg; |
| 1252 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1253 | context.SetRegister (dwarf_reg); |
| 1254 | if (!BXWritePC(context, target)) |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 1255 | return false; |
| 1256 | } |
| 1257 | return true; |
| 1258 | } |
| 1259 | |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1260 | // Set r7 to point to some ip offset. |
| 1261 | // SUB (immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1262 | bool |
| 1263 | EmulateInstructionARM::EmulateSubR7IPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1264 | { |
| 1265 | #if 0 |
| 1266 | // ARM pseudo code... |
| 1267 | if (ConditionPassed()) |
| 1268 | { |
| 1269 | EncodingSpecificOperations(); |
| 1270 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1271 | if d == 15 then // Can only occur for ARM encoding |
| 1272 | ALUWritePC(result); // setflags is always FALSE here |
| 1273 | else |
| 1274 | R[d] = result; |
| 1275 | if setflags then |
| 1276 | APSR.N = result<31>; |
| 1277 | APSR.Z = IsZeroBit(result); |
| 1278 | APSR.C = carry; |
| 1279 | APSR.V = overflow; |
| 1280 | } |
| 1281 | #endif |
| 1282 | |
| 1283 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1284 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1285 | if (!success) |
| 1286 | return false; |
| 1287 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1288 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1289 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1290 | const addr_t ip = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r12, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1291 | if (!success) |
| 1292 | return false; |
| 1293 | uint32_t imm32; |
| 1294 | switch (encoding) { |
| 1295 | case eEncodingA1: |
| 1296 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1297 | break; |
| 1298 | default: |
| 1299 | return false; |
| 1300 | } |
| 1301 | addr_t ip_offset = imm32; |
| 1302 | addr_t addr = ip - ip_offset; // the adjusted ip value |
| 1303 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1304 | EmulateInstruction::Context context; |
| 1305 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1306 | Register dwarf_reg; |
| 1307 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r12); |
| 1308 | context.SetRegisterPlusOffset (dwarf_reg, -ip_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1309 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1310 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1311 | return false; |
| 1312 | } |
| 1313 | return true; |
| 1314 | } |
| 1315 | |
| 1316 | // Set ip to point to some stack offset. |
| 1317 | // SUB (SP minus immediate) |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1318 | bool |
| 1319 | EmulateInstructionARM::EmulateSubIPSPImmediate (ARMEncoding encoding) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1320 | { |
| 1321 | #if 0 |
| 1322 | // ARM pseudo code... |
| 1323 | if (ConditionPassed()) |
| 1324 | { |
| 1325 | EncodingSpecificOperations(); |
| 1326 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1327 | if d == 15 then // Can only occur for ARM encoding |
| 1328 | ALUWritePC(result); // setflags is always FALSE here |
| 1329 | else |
| 1330 | R[d] = result; |
| 1331 | if setflags then |
| 1332 | APSR.N = result<31>; |
| 1333 | APSR.Z = IsZeroBit(result); |
| 1334 | APSR.C = carry; |
| 1335 | APSR.V = overflow; |
| 1336 | } |
| 1337 | #endif |
| 1338 | |
| 1339 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1340 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1341 | if (!success) |
| 1342 | return false; |
| 1343 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1344 | if (ConditionPassed()) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1345 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1346 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1347 | if (!success) |
| 1348 | return false; |
| 1349 | uint32_t imm32; |
| 1350 | switch (encoding) { |
| 1351 | case eEncodingA1: |
| 1352 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
| 1353 | break; |
| 1354 | default: |
| 1355 | return false; |
| 1356 | } |
| 1357 | addr_t sp_offset = imm32; |
| 1358 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1359 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1360 | EmulateInstruction::Context context; |
| 1361 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 1362 | Register dwarf_reg; |
| 1363 | dwarf_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); |
| 1364 | context.SetRegisterPlusOffset (dwarf_reg, -sp_offset); |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1365 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1366 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr)) |
Johnny Chen | 0d0148e | 2011-01-28 02:26:08 +0000 | [diff] [blame] | 1367 | return false; |
| 1368 | } |
| 1369 | return true; |
| 1370 | } |
| 1371 | |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1372 | // A sub operation to adjust the SP -- allocate space for local storage. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1373 | bool |
| 1374 | EmulateInstructionARM::EmulateSubSPImmdiate (ARMEncoding encoding) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1375 | { |
| 1376 | #if 0 |
| 1377 | // ARM pseudo code... |
| 1378 | if (ConditionPassed()) |
| 1379 | { |
| 1380 | EncodingSpecificOperations(); |
| 1381 | (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ‘1’); |
| 1382 | if d == 15 then // Can only occur for ARM encoding |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1383 | ALUWritePC(result); // setflags is always FALSE here |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1384 | else |
| 1385 | R[d] = result; |
| 1386 | if setflags then |
| 1387 | APSR.N = result<31>; |
| 1388 | APSR.Z = IsZeroBit(result); |
| 1389 | APSR.C = carry; |
| 1390 | APSR.V = overflow; |
| 1391 | } |
| 1392 | #endif |
| 1393 | |
| 1394 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1395 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1396 | if (!success) |
| 1397 | return false; |
| 1398 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1399 | if (ConditionPassed()) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1400 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1401 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1402 | if (!success) |
| 1403 | return false; |
| 1404 | uint32_t imm32; |
| 1405 | switch (encoding) { |
Johnny Chen | e445502 | 2011-01-26 00:08:59 +0000 | [diff] [blame] | 1406 | case eEncodingT1: |
| 1407 | imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1408 | case eEncodingT2: |
| 1409 | imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) |
| 1410 | break; |
| 1411 | case eEncodingT3: |
| 1412 | imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) |
| 1413 | break; |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1414 | case eEncodingA1: |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 1415 | imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1416 | break; |
| 1417 | default: |
| 1418 | return false; |
| 1419 | } |
| 1420 | addr_t sp_offset = imm32; |
| 1421 | addr_t addr = sp - sp_offset; // the adjusted stack pointer value |
| 1422 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1423 | EmulateInstruction::Context context; |
| 1424 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
| 1425 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1426 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1427 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 1428 | return false; |
| 1429 | } |
| 1430 | return true; |
| 1431 | } |
| 1432 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1433 | // A store operation to the stack that also updates the SP. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1434 | bool |
| 1435 | EmulateInstructionARM::EmulateSTRRtSP (ARMEncoding encoding) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1436 | { |
| 1437 | #if 0 |
| 1438 | // ARM pseudo code... |
| 1439 | if (ConditionPassed()) |
| 1440 | { |
| 1441 | EncodingSpecificOperations(); |
| 1442 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 1443 | address = if index then offset_addr else R[n]; |
| 1444 | MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; |
| 1445 | if wback then R[n] = offset_addr; |
| 1446 | } |
| 1447 | #endif |
| 1448 | |
| 1449 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1450 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1451 | if (!success) |
| 1452 | return false; |
| 1453 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1454 | if (ConditionPassed()) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1455 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1456 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1457 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1458 | if (!success) |
| 1459 | return false; |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1460 | uint32_t Rt; // the source register |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1461 | uint32_t imm12; |
| 1462 | switch (encoding) { |
| 1463 | case eEncodingA1: |
Johnny Chen | 108d5aa | 2011-01-26 01:00:55 +0000 | [diff] [blame] | 1464 | Rt = Bits32(opcode, 15, 12); |
| 1465 | imm12 = Bits32(opcode, 11, 0); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1466 | break; |
| 1467 | default: |
| 1468 | return false; |
| 1469 | } |
| 1470 | addr_t sp_offset = imm12; |
| 1471 | addr_t addr = sp - sp_offset; |
| 1472 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1473 | EmulateInstruction::Context context; |
| 1474 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 1475 | Register dwarf_reg; |
| 1476 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 91d9986 | 2011-01-25 19:07:04 +0000 | [diff] [blame] | 1477 | if (Rt != 15) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1478 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1479 | dwarf_reg.num = dwarf_r0 + Rt; |
| 1480 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
| 1481 | uint32_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1482 | if (!success) |
| 1483 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1484 | if (!WriteMemoryUnsigned (context, addr, reg_value, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1485 | return false; |
| 1486 | } |
| 1487 | else |
| 1488 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1489 | dwarf_reg.num = dwarf_pc; |
| 1490 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1491 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1492 | if (!success) |
| 1493 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1494 | if (!WriteMemoryUnsigned (context, addr, pc + 8, addr_byte_size)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1495 | return false; |
| 1496 | } |
| 1497 | |
| 1498 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1499 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1500 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1501 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 1502 | return false; |
| 1503 | } |
| 1504 | return true; |
| 1505 | } |
| 1506 | |
Johnny Chen | 08c25e8 | 2011-01-31 18:02:28 +0000 | [diff] [blame] | 1507 | // Vector Push stores multiple extension registers to the stack. |
| 1508 | // It also updates SP to point to the start of the stored data. |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1509 | bool |
| 1510 | EmulateInstructionARM::EmulateVPUSH (ARMEncoding encoding) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1511 | { |
| 1512 | #if 0 |
| 1513 | // ARM pseudo code... |
| 1514 | if (ConditionPassed()) |
| 1515 | { |
| 1516 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1517 | address = SP - imm32; |
| 1518 | SP = SP - imm32; |
| 1519 | if single_regs then |
| 1520 | for r = 0 to regs-1 |
| 1521 | MemA[address,4] = S[d+r]; address = address+4; |
| 1522 | else |
| 1523 | for r = 0 to regs-1 |
| 1524 | // Store as two word-aligned words in the correct order for current endianness. |
| 1525 | MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>; |
| 1526 | MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>; |
| 1527 | address = address+8; |
| 1528 | } |
| 1529 | #endif |
| 1530 | |
| 1531 | bool success = false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1532 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1533 | if (!success) |
| 1534 | return false; |
| 1535 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1536 | if (ConditionPassed()) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1537 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1538 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1539 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1540 | if (!success) |
| 1541 | return false; |
| 1542 | bool single_regs; |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1543 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1544 | uint32_t imm32; // stack offset |
| 1545 | uint32_t regs; // number of registers |
| 1546 | switch (encoding) { |
| 1547 | case eEncodingT1: |
| 1548 | case eEncodingA1: |
| 1549 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1550 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1551 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1552 | // If UInt(imm8) is odd, see "FSTMX". |
| 1553 | regs = Bits32(opcode, 7, 0) / 2; |
| 1554 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1555 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1556 | return false; |
| 1557 | break; |
| 1558 | case eEncodingT2: |
| 1559 | case eEncodingA2: |
| 1560 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1561 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1562 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1563 | regs = Bits32(opcode, 7, 0); |
| 1564 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1565 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1566 | return false; |
| 1567 | break; |
| 1568 | default: |
| 1569 | return false; |
| 1570 | } |
| 1571 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1572 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1573 | addr_t sp_offset = imm32; |
| 1574 | addr_t addr = sp - sp_offset; |
| 1575 | uint32_t i; |
| 1576 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1577 | EmulateInstruction::Context context; |
| 1578 | context.type = EmulateInstruction::eContextPushRegisterOnStack; |
| 1579 | Register dwarf_reg; |
| 1580 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1581 | for (i=d; i<regs; ++i) |
| 1582 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1583 | dwarf_reg.num = start_reg + i; |
| 1584 | context.SetRegisterPlusOffset ( dwarf_reg, addr - sp); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1585 | // uint64_t to accommodate 64-bit registers. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1586 | uint64_t reg_value = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_reg.num, 0, &success); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1587 | if (!success) |
| 1588 | return false; |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1589 | if (!WriteMemoryUnsigned (context, addr, reg_value, reg_byte_size)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1590 | return false; |
| 1591 | addr += reg_byte_size; |
| 1592 | } |
| 1593 | |
| 1594 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1595 | context.SetImmediateSigned (-sp_offset); |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1596 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 1597 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset)) |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 1598 | return false; |
| 1599 | } |
| 1600 | return true; |
| 1601 | } |
| 1602 | |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1603 | // Vector Pop loads multiple extension registers from the stack. |
| 1604 | // It also updates SP to point just above the loaded data. |
| 1605 | bool |
| 1606 | EmulateInstructionARM::EmulateVPOP (ARMEncoding encoding) |
| 1607 | { |
| 1608 | #if 0 |
| 1609 | // ARM pseudo code... |
| 1610 | if (ConditionPassed()) |
| 1611 | { |
| 1612 | EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13); |
| 1613 | address = SP; |
| 1614 | SP = SP + imm32; |
| 1615 | if single_regs then |
| 1616 | for r = 0 to regs-1 |
| 1617 | S[d+r] = MemA[address,4]; address = address+4; |
| 1618 | else |
| 1619 | for r = 0 to regs-1 |
| 1620 | word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; |
| 1621 | // Combine the word-aligned words in the correct order for current endianness. |
| 1622 | D[d+r] = if BigEndian() then word1:word2 else word2:word1; |
| 1623 | } |
| 1624 | #endif |
| 1625 | |
| 1626 | bool success = false; |
| 1627 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1628 | if (!success) |
| 1629 | return false; |
| 1630 | |
| 1631 | if (ConditionPassed()) |
| 1632 | { |
| 1633 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 1634 | const addr_t sp = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, 0, &success); |
| 1635 | if (!success) |
| 1636 | return false; |
| 1637 | bool single_regs; |
| 1638 | uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register |
| 1639 | uint32_t imm32; // stack offset |
| 1640 | uint32_t regs; // number of registers |
| 1641 | switch (encoding) { |
| 1642 | case eEncodingT1: |
| 1643 | case eEncodingA1: |
| 1644 | single_regs = false; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1645 | d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1646 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1647 | // If UInt(imm8) is odd, see "FLDMX". |
| 1648 | regs = Bits32(opcode, 7, 0) / 2; |
| 1649 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1650 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1651 | return false; |
| 1652 | break; |
| 1653 | case eEncodingT2: |
| 1654 | case eEncodingA2: |
| 1655 | single_regs = true; |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1656 | d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1657 | imm32 = Bits32(opcode, 7, 0) * addr_byte_size; |
| 1658 | regs = Bits32(opcode, 7, 0); |
| 1659 | // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; |
| 1660 | if (regs == 0 || regs > 16 || (d + regs) > 32) |
| 1661 | return false; |
| 1662 | break; |
| 1663 | default: |
| 1664 | return false; |
| 1665 | } |
| 1666 | uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0; |
| 1667 | uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2; |
| 1668 | addr_t sp_offset = imm32; |
| 1669 | addr_t addr = sp; |
| 1670 | uint32_t i; |
| 1671 | uint64_t data; // uint64_t to accomodate 64-bit registers. |
| 1672 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1673 | EmulateInstruction::Context context; |
| 1674 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 1675 | Register dwarf_reg; |
| 1676 | dwarf_reg.SetRegister (eRegisterKindDWARF, 0); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1677 | for (i=d; i<regs; ++i) |
| 1678 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1679 | dwarf_reg.num = start_reg + i; |
| 1680 | context.SetRegisterPlusOffset (dwarf_reg, addr - sp); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1681 | data = ReadMemoryUnsigned(context, addr, reg_byte_size, 0, &success); |
| 1682 | if (!success) |
| 1683 | return false; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1684 | if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_reg.num, data)) |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1685 | return false; |
| 1686 | addr += reg_byte_size; |
| 1687 | } |
| 1688 | |
| 1689 | context.type = EmulateInstruction::eContextAdjustStackPointer; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1690 | context.SetImmediateSigned (sp_offset); |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 1691 | |
| 1692 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset)) |
| 1693 | return false; |
| 1694 | } |
| 1695 | return true; |
| 1696 | } |
| 1697 | |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1698 | // SVC (previously SWI) |
| 1699 | bool |
| 1700 | EmulateInstructionARM::EmulateSVC (ARMEncoding encoding) |
| 1701 | { |
| 1702 | #if 0 |
| 1703 | // ARM pseudo code... |
| 1704 | if (ConditionPassed()) |
| 1705 | { |
| 1706 | EncodingSpecificOperations(); |
| 1707 | CallSupervisor(); |
| 1708 | } |
| 1709 | #endif |
| 1710 | |
| 1711 | bool success = false; |
| 1712 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1713 | if (!success) |
| 1714 | return false; |
| 1715 | |
| 1716 | if (ConditionPassed()) |
| 1717 | { |
| 1718 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1719 | addr_t lr; // next instruction address |
| 1720 | if (!success) |
| 1721 | return false; |
| 1722 | uint32_t imm32; // the immediate constant |
| 1723 | uint32_t mode; // ARM or Thumb mode |
| 1724 | switch (encoding) { |
| 1725 | case eEncodingT1: |
| 1726 | lr = (pc + 2) | 1u; // return address |
| 1727 | imm32 = Bits32(opcode, 7, 0); |
| 1728 | mode = eModeThumb; |
| 1729 | break; |
| 1730 | case eEncodingA1: |
| 1731 | lr = pc + 4; // return address |
| 1732 | imm32 = Bits32(opcode, 23, 0); |
| 1733 | mode = eModeARM; |
| 1734 | break; |
| 1735 | default: |
| 1736 | return false; |
| 1737 | } |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1738 | |
| 1739 | EmulateInstruction::Context context; |
| 1740 | context.type = EmulateInstruction::eContextSupervisorCall; |
| 1741 | context.SetModeAndImmediate (mode, imm32); |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 1742 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) |
| 1743 | return false; |
| 1744 | } |
| 1745 | return true; |
| 1746 | } |
| 1747 | |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 1748 | // If Then makes up to four following instructions (the IT block) conditional. |
| 1749 | bool |
| 1750 | EmulateInstructionARM::EmulateIT (ARMEncoding encoding) |
| 1751 | { |
| 1752 | #if 0 |
| 1753 | // ARM pseudo code... |
| 1754 | EncodingSpecificOperations(); |
| 1755 | ITSTATE.IT<7:0> = firstcond:mask; |
| 1756 | #endif |
| 1757 | |
| 1758 | bool success = false; |
| 1759 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1760 | if (!success) |
| 1761 | return false; |
| 1762 | |
| 1763 | m_it_session.InitIT(Bits32(opcode, 7, 0)); |
| 1764 | return true; |
| 1765 | } |
| 1766 | |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1767 | // Branch causes a branch to a target address. |
| 1768 | bool |
| 1769 | EmulateInstructionARM::EmulateB (ARMEncoding encoding) |
| 1770 | { |
| 1771 | #if 0 |
| 1772 | // ARM pseudo code... |
| 1773 | if (ConditionPassed()) |
| 1774 | { |
| 1775 | EncodingSpecificOperations(); |
| 1776 | BranchWritePC(PC + imm32); |
| 1777 | } |
| 1778 | #endif |
| 1779 | |
| 1780 | bool success = false; |
| 1781 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1782 | if (!success) |
| 1783 | return false; |
| 1784 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1785 | if (ConditionPassed()) |
| 1786 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1787 | EmulateInstruction::Context context; |
| 1788 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1789 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1790 | if (!success) |
| 1791 | return false; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1792 | addr_t target; // target address |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1793 | int32_t imm32; // PC-relative offset |
| 1794 | switch (encoding) { |
| 1795 | case eEncodingT1: |
| 1796 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1797 | imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); |
| 1798 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1799 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1800 | break; |
| 1801 | case eEncodingT2: |
| 1802 | imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0)); |
| 1803 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1804 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1805 | break; |
| 1806 | case eEncodingT3: |
| 1807 | // The 'cond' field is handled in EmulateInstructionARM::CurrentCond(). |
| 1808 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1809 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1810 | uint32_t imm6 = Bits32(opcode, 21, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1811 | uint32_t J1 = Bit32(opcode, 13); |
| 1812 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1813 | uint32_t imm11 = Bits32(opcode, 10, 0); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1814 | uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1815 | imm32 = llvm::SignExtend32<21>(imm21); |
| 1816 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1817 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1818 | break; |
| 1819 | } |
| 1820 | case eEncodingT4: |
| 1821 | { |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1822 | uint32_t S = Bit32(opcode, 26); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1823 | uint32_t imm10 = Bits32(opcode, 25, 16); |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1824 | uint32_t J1 = Bit32(opcode, 13); |
| 1825 | uint32_t J2 = Bit32(opcode, 11); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1826 | uint32_t imm11 = Bits32(opcode, 10, 0); |
| 1827 | uint32_t I1 = !(J1 ^ S); |
| 1828 | uint32_t I2 = !(J2 ^ S); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1829 | uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1830 | imm32 = llvm::SignExtend32<25>(imm25); |
| 1831 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1832 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1833 | break; |
| 1834 | } |
| 1835 | case eEncodingA1: |
| 1836 | imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); |
| 1837 | target = pc + 8 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1838 | context.SetModeAndImmediateSigned (eModeARM, 8 + imm32); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 1839 | break; |
| 1840 | default: |
| 1841 | return false; |
| 1842 | } |
| 1843 | if (!BranchWritePC(context, target)) |
| 1844 | return false; |
| 1845 | } |
| 1846 | return true; |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 1847 | } |
| 1848 | |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1849 | // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with |
| 1850 | // zero and conditionally branch forward a constant value. They do not affect the condition flags. |
| 1851 | // CBNZ, CBZ |
| 1852 | bool |
| 1853 | EmulateInstructionARM::EmulateCB (ARMEncoding encoding) |
| 1854 | { |
| 1855 | #if 0 |
| 1856 | // ARM pseudo code... |
| 1857 | EncodingSpecificOperations(); |
| 1858 | if nonzero ^ IsZero(R[n]) then |
| 1859 | BranchWritePC(PC + imm32); |
| 1860 | #endif |
| 1861 | |
| 1862 | bool success = false; |
| 1863 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1864 | if (!success) |
| 1865 | return false; |
| 1866 | |
| 1867 | // Read the register value from the operand register Rn. |
| 1868 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Bits32(opcode, 2, 0), 0, &success); |
| 1869 | if (!success) |
| 1870 | return false; |
| 1871 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1872 | EmulateInstruction::Context context; |
| 1873 | context.type = EmulateInstruction::eContextRelativeBranchImmediate; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1874 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1875 | if (!success) |
| 1876 | return false; |
| 1877 | |
| 1878 | addr_t target; // target address |
| 1879 | uint32_t imm32; // PC-relative offset to branch forward |
| 1880 | bool nonzero; |
| 1881 | switch (encoding) { |
| 1882 | case eEncodingT1: |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1883 | imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1884 | nonzero = BitIsSet(opcode, 11); |
| 1885 | target = pc + 4 + imm32; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1886 | context.SetModeAndImmediateSigned (eModeThumb, 4 + imm32); |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 1887 | break; |
| 1888 | default: |
| 1889 | return false; |
| 1890 | } |
| 1891 | if (nonzero ^ (reg_val == 0)) |
| 1892 | if (!BranchWritePC(context, target)) |
| 1893 | return false; |
| 1894 | |
| 1895 | return true; |
| 1896 | } |
| 1897 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1898 | // ADD <Rdn>, <Rm> |
| 1899 | // where <Rdn> the destination register is also the first operand register |
| 1900 | // and <Rm> is the second operand register. |
| 1901 | bool |
| 1902 | EmulateInstructionARM::EmulateAddRdnRm (ARMEncoding encoding) |
| 1903 | { |
| 1904 | #if 0 |
| 1905 | // ARM pseudo code... |
| 1906 | if ConditionPassed() then |
| 1907 | EncodingSpecificOperations(); |
| 1908 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 1909 | (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); |
| 1910 | if d == 15 then |
| 1911 | ALUWritePC(result); // setflags is always FALSE here |
| 1912 | else |
| 1913 | R[d] = result; |
| 1914 | if setflags then |
| 1915 | APSR.N = result<31>; |
| 1916 | APSR.Z = IsZeroBit(result); |
| 1917 | APSR.C = carry; |
| 1918 | APSR.V = overflow; |
| 1919 | #endif |
| 1920 | |
| 1921 | bool success = false; |
| 1922 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1923 | if (!success) |
| 1924 | return false; |
| 1925 | |
| 1926 | if (ConditionPassed()) |
| 1927 | { |
| 1928 | uint32_t Rd, Rn, Rm; |
| 1929 | //bool setflags = false; |
| 1930 | switch (encoding) |
| 1931 | { |
| 1932 | case eEncodingT2: |
| 1933 | // setflags = FALSE |
Johnny Chen | bd59990 | 2011-02-10 21:39:01 +0000 | [diff] [blame] | 1934 | Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1935 | Rm = Bits32(opcode, 6, 3); |
| 1936 | if (Rn == 15 && Rm == 15) |
| 1937 | return false; |
| 1938 | break; |
| 1939 | default: |
| 1940 | return false; |
| 1941 | } |
| 1942 | |
| 1943 | int32_t result, val1, val2; |
| 1944 | // Read the first operand. |
| 1945 | if (Rn == 15) |
| 1946 | val1 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1947 | else |
| 1948 | val1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 1949 | if (!success) |
| 1950 | return false; |
| 1951 | |
| 1952 | // Read the second operand. |
| 1953 | if (Rm == 15) |
| 1954 | val2 = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 1955 | else |
| 1956 | val2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 1957 | if (!success) |
| 1958 | return false; |
| 1959 | |
| 1960 | result = val1 + val2; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 1961 | |
| 1962 | EmulateInstruction::Context context; |
| 1963 | context.type = EmulateInstruction::eContextImmediate; |
| 1964 | context.SetNoArgs (); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1965 | |
| 1966 | if (Rd == 15) |
| 1967 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 1968 | if (!ALUWritePC (context, result)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1969 | return false; |
| 1970 | } |
| 1971 | else |
| 1972 | { |
Johnny Chen | 33bf6ab | 2011-02-14 20:39:01 +0000 | [diff] [blame] | 1973 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 1974 | return false; |
| 1975 | } |
| 1976 | } |
| 1977 | return true; |
| 1978 | } |
| 1979 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 1980 | // CMP (immediate) |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 1981 | bool |
| 1982 | EmulateInstructionARM::EmulateCmpRnImm (ARMEncoding encoding) |
| 1983 | { |
| 1984 | #if 0 |
| 1985 | // ARM pseudo code... |
| 1986 | if ConditionPassed() then |
| 1987 | EncodingSpecificOperations(); |
| 1988 | (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); |
| 1989 | APSR.N = result<31>; |
| 1990 | APSR.Z = IsZeroBit(result); |
| 1991 | APSR.C = carry; |
| 1992 | APSR.V = overflow; |
| 1993 | #endif |
| 1994 | |
| 1995 | bool success = false; |
| 1996 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 1997 | if (!success) |
| 1998 | return false; |
| 1999 | |
| 2000 | uint32_t Rn; // the first operand |
| 2001 | uint32_t imm32; // the immediate value to be compared with |
| 2002 | switch (encoding) { |
| 2003 | case eEncodingT1: |
| 2004 | Rn = Bits32(opcode, 10, 8); |
| 2005 | imm32 = Bits32(opcode, 7, 0); |
| 2006 | break; |
| 2007 | default: |
| 2008 | return false; |
| 2009 | } |
| 2010 | // Read the register value from the operand register Rn. |
| 2011 | uint32_t reg_val = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2012 | if (!success) |
| 2013 | return false; |
| 2014 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2015 | EmulateInstruction::Context context; |
| 2016 | context.type = EmulateInstruction::eContextImmediate; |
| 2017 | context.SetNoArgs (); |
| 2018 | |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2019 | AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); |
| 2020 | m_new_inst_cpsr = m_inst_cpsr; |
| 2021 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2022 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2023 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2024 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2025 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2026 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2027 | EmulateInstruction::Context context; |
| 2028 | context.type = EmulateInstruction::eContextImmediate; |
| 2029 | context.SetNoArgs (); |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 2030 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2031 | return false; |
| 2032 | } |
| 2033 | return true; |
| 2034 | } |
| 2035 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2036 | // CMP (register) |
| 2037 | bool |
| 2038 | EmulateInstructionARM::EmulateCmpRnRm (ARMEncoding encoding) |
| 2039 | { |
| 2040 | #if 0 |
| 2041 | // ARM pseudo code... |
| 2042 | if ConditionPassed() then |
| 2043 | EncodingSpecificOperations(); |
| 2044 | shifted = Shift(R[m], shift_t, shift_n, APSR.C); |
| 2045 | (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); |
| 2046 | APSR.N = result<31>; |
| 2047 | APSR.Z = IsZeroBit(result); |
| 2048 | APSR.C = carry; |
| 2049 | APSR.V = overflow; |
| 2050 | #endif |
| 2051 | |
| 2052 | bool success = false; |
| 2053 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2054 | if (!success) |
| 2055 | return false; |
| 2056 | |
| 2057 | uint32_t Rn; // the first operand |
| 2058 | uint32_t Rm; // the second operand |
| 2059 | switch (encoding) { |
| 2060 | case eEncodingT1: |
| 2061 | Rn = Bits32(opcode, 2, 0); |
| 2062 | Rm = Bits32(opcode, 5, 3); |
| 2063 | break; |
| 2064 | case eEncodingT2: |
| 2065 | Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); |
| 2066 | Rm = Bits32(opcode, 6, 3); |
| 2067 | if (Rn < 8 && Rm < 8) |
| 2068 | return false; |
| 2069 | if (Rn == 15 || Rm == 15) |
| 2070 | return false; |
| 2071 | break; |
| 2072 | default: |
| 2073 | return false; |
| 2074 | } |
| 2075 | // Read the register value from register Rn. |
| 2076 | uint32_t reg_val1 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2077 | if (!success) |
| 2078 | return false; |
| 2079 | // Read the register value from register Rm. |
| 2080 | // The register value is not being shifted since we don't handle ARM for now. |
| 2081 | uint32_t reg_val2 = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 2082 | if (!success) |
| 2083 | return false; |
| 2084 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2085 | EmulateInstruction::Context context; |
| 2086 | context.type = EmulateInstruction::eContextImmediate; |
| 2087 | context.SetNoArgs(); |
| 2088 | |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2089 | AddWithCarryResult res = AddWithCarry(reg_val1, reg_val2, 1); |
| 2090 | m_new_inst_cpsr = m_inst_cpsr; |
| 2091 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(res.result, CPSR_N)); |
| 2092 | SetBit32(m_new_inst_cpsr, CPSR_Z, res.result == 0 ? 1 : 0); |
| 2093 | SetBit32(m_new_inst_cpsr, CPSR_C, res.carry_out); |
| 2094 | SetBit32(m_new_inst_cpsr, CPSR_V, res.overflow); |
| 2095 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2096 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2097 | EmulateInstruction::Context context; |
| 2098 | context.type = EmulateInstruction::eContextImmediate; |
| 2099 | context.SetNoArgs (); |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 2100 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2101 | return false; |
| 2102 | } |
| 2103 | return true; |
| 2104 | } |
| 2105 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2106 | // Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, |
| 2107 | // shifting in copies of its sign bit, and writes the result to the destination register. It can |
| 2108 | // optionally update the condition flags based on the result. |
| 2109 | bool |
| 2110 | EmulateInstructionARM::EmulateASRImm (ARMEncoding encoding) |
| 2111 | { |
| 2112 | #if 0 |
| 2113 | // ARM pseudo code... |
| 2114 | if ConditionPassed() then |
| 2115 | EncodingSpecificOperations(); |
| 2116 | (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C); |
| 2117 | if d == 15 then // Can only occur for ARM encoding |
| 2118 | ALUWritePC(result); // setflags is always FALSE here |
| 2119 | else |
| 2120 | R[d] = result; |
| 2121 | if setflags then |
| 2122 | APSR.N = result<31>; |
| 2123 | APSR.Z = IsZeroBit(result); |
| 2124 | APSR.C = carry; |
| 2125 | // APSR.V unchanged |
| 2126 | #endif |
| 2127 | |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2128 | return EmulateShiftImm(encoding, SRType_ASR); |
| 2129 | } |
| 2130 | |
| 2131 | // Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, |
| 2132 | // shifting in copies of its sign bit, and writes the result to the destination register. |
| 2133 | // The variable number of bits is read from the bottom byte of a register. It can optionally update |
| 2134 | // the condition flags based on the result. |
| 2135 | bool |
| 2136 | EmulateInstructionARM::EmulateASRReg (ARMEncoding encoding) |
| 2137 | { |
| 2138 | #if 0 |
| 2139 | // ARM pseudo code... |
| 2140 | if ConditionPassed() then |
| 2141 | EncodingSpecificOperations(); |
| 2142 | shift_n = UInt(R[m]<7:0>); |
| 2143 | (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C); |
| 2144 | R[d] = result; |
| 2145 | if setflags then |
| 2146 | APSR.N = result<31>; |
| 2147 | APSR.Z = IsZeroBit(result); |
| 2148 | APSR.C = carry; |
| 2149 | // APSR.V unchanged |
| 2150 | #endif |
| 2151 | |
| 2152 | return EmulateShiftReg(encoding, SRType_ASR); |
| 2153 | } |
| 2154 | |
| 2155 | // Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, |
| 2156 | // shifting in zeros, and writes the result to the destination register. It can optionally |
| 2157 | // update the condition flags based on the result. |
| 2158 | bool |
| 2159 | EmulateInstructionARM::EmulateLSLImm (ARMEncoding encoding) |
| 2160 | { |
| 2161 | #if 0 |
| 2162 | // ARM pseudo code... |
| 2163 | if ConditionPassed() then |
| 2164 | EncodingSpecificOperations(); |
| 2165 | (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C); |
| 2166 | if d == 15 then // Can only occur for ARM encoding |
| 2167 | ALUWritePC(result); // setflags is always FALSE here |
| 2168 | else |
| 2169 | R[d] = result; |
| 2170 | if setflags then |
| 2171 | APSR.N = result<31>; |
| 2172 | APSR.Z = IsZeroBit(result); |
| 2173 | APSR.C = carry; |
| 2174 | // APSR.V unchanged |
| 2175 | #endif |
| 2176 | |
| 2177 | return EmulateShiftImm(encoding, SRType_LSL); |
| 2178 | } |
| 2179 | |
| 2180 | // Logical Shift Left (register) shifts a register value left by a variable number of bits, |
| 2181 | // shifting in zeros, and writes the result to the destination register. The variable number |
| 2182 | // of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2183 | // flags based on the result. |
| 2184 | bool |
| 2185 | EmulateInstructionARM::EmulateLSLReg (ARMEncoding encoding) |
| 2186 | { |
| 2187 | #if 0 |
| 2188 | // ARM pseudo code... |
| 2189 | if ConditionPassed() then |
| 2190 | EncodingSpecificOperations(); |
| 2191 | shift_n = UInt(R[m]<7:0>); |
| 2192 | (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C); |
| 2193 | R[d] = result; |
| 2194 | if setflags then |
| 2195 | APSR.N = result<31>; |
| 2196 | APSR.Z = IsZeroBit(result); |
| 2197 | APSR.C = carry; |
| 2198 | // APSR.V unchanged |
| 2199 | #endif |
| 2200 | |
| 2201 | return EmulateShiftReg(encoding, SRType_LSL); |
| 2202 | } |
| 2203 | |
| 2204 | // Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, |
| 2205 | // shifting in zeros, and writes the result to the destination register. It can optionally |
| 2206 | // update the condition flags based on the result. |
| 2207 | bool |
| 2208 | EmulateInstructionARM::EmulateLSRImm (ARMEncoding encoding) |
| 2209 | { |
| 2210 | #if 0 |
| 2211 | // ARM pseudo code... |
| 2212 | if ConditionPassed() then |
| 2213 | EncodingSpecificOperations(); |
| 2214 | (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C); |
| 2215 | if d == 15 then // Can only occur for ARM encoding |
| 2216 | ALUWritePC(result); // setflags is always FALSE here |
| 2217 | else |
| 2218 | R[d] = result; |
| 2219 | if setflags then |
| 2220 | APSR.N = result<31>; |
| 2221 | APSR.Z = IsZeroBit(result); |
| 2222 | APSR.C = carry; |
| 2223 | // APSR.V unchanged |
| 2224 | #endif |
| 2225 | |
| 2226 | return EmulateShiftImm(encoding, SRType_LSR); |
| 2227 | } |
| 2228 | |
| 2229 | // Logical Shift Right (register) shifts a register value right by a variable number of bits, |
| 2230 | // shifting in zeros, and writes the result to the destination register. The variable number |
| 2231 | // of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2232 | // flags based on the result. |
| 2233 | bool |
| 2234 | EmulateInstructionARM::EmulateLSRReg (ARMEncoding encoding) |
| 2235 | { |
| 2236 | #if 0 |
| 2237 | // ARM pseudo code... |
| 2238 | if ConditionPassed() then |
| 2239 | EncodingSpecificOperations(); |
| 2240 | shift_n = UInt(R[m]<7:0>); |
| 2241 | (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C); |
| 2242 | R[d] = result; |
| 2243 | if setflags then |
| 2244 | APSR.N = result<31>; |
| 2245 | APSR.Z = IsZeroBit(result); |
| 2246 | APSR.C = carry; |
| 2247 | // APSR.V unchanged |
| 2248 | #endif |
| 2249 | |
| 2250 | return EmulateShiftReg(encoding, SRType_LSR); |
| 2251 | } |
| 2252 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2253 | // Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. |
| 2254 | // The bits that are rotated off the right end are inserted into the vacated bit positions on the left. |
| 2255 | // It can optionally update the condition flags based on the result. |
| 2256 | bool |
| 2257 | EmulateInstructionARM::EmulateRORImm (ARMEncoding encoding) |
| 2258 | { |
| 2259 | #if 0 |
| 2260 | // ARM pseudo code... |
| 2261 | if ConditionPassed() then |
| 2262 | EncodingSpecificOperations(); |
| 2263 | (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C); |
| 2264 | if d == 15 then // Can only occur for ARM encoding |
| 2265 | ALUWritePC(result); // setflags is always FALSE here |
| 2266 | else |
| 2267 | R[d] = result; |
| 2268 | if setflags then |
| 2269 | APSR.N = result<31>; |
| 2270 | APSR.Z = IsZeroBit(result); |
| 2271 | APSR.C = carry; |
| 2272 | // APSR.V unchanged |
| 2273 | #endif |
| 2274 | |
| 2275 | return EmulateShiftImm(encoding, SRType_ROR); |
| 2276 | } |
| 2277 | |
| 2278 | // Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. |
| 2279 | // The bits that are rotated off the right end are inserted into the vacated bit positions on the left. |
| 2280 | // The variable number of bits is read from the bottom byte of a register. It can optionally update the condition |
| 2281 | // flags based on the result. |
| 2282 | bool |
| 2283 | EmulateInstructionARM::EmulateRORReg (ARMEncoding encoding) |
| 2284 | { |
| 2285 | #if 0 |
| 2286 | // ARM pseudo code... |
| 2287 | if ConditionPassed() then |
| 2288 | EncodingSpecificOperations(); |
| 2289 | shift_n = UInt(R[m]<7:0>); |
| 2290 | (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C); |
| 2291 | R[d] = result; |
| 2292 | if setflags then |
| 2293 | APSR.N = result<31>; |
| 2294 | APSR.Z = IsZeroBit(result); |
| 2295 | APSR.C = carry; |
| 2296 | // APSR.V unchanged |
| 2297 | #endif |
| 2298 | |
| 2299 | return EmulateShiftReg(encoding, SRType_ROR); |
| 2300 | } |
| 2301 | |
| 2302 | // Rotate Right with Extend provides the value of the contents of a register shifted right by one place, |
| 2303 | // with the carry flag shifted into bit [31]. |
| 2304 | // |
| 2305 | // RRX can optionally update the condition flags based on the result. |
| 2306 | // In that case, bit [0] is shifted into the carry flag. |
| 2307 | bool |
| 2308 | EmulateInstructionARM::EmulateRRX (ARMEncoding encoding) |
| 2309 | { |
| 2310 | #if 0 |
| 2311 | // ARM pseudo code... |
| 2312 | if ConditionPassed() then |
| 2313 | EncodingSpecificOperations(); |
| 2314 | (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C); |
| 2315 | if d == 15 then // Can only occur for ARM encoding |
| 2316 | ALUWritePC(result); // setflags is always FALSE here |
| 2317 | else |
| 2318 | R[d] = result; |
| 2319 | if setflags then |
| 2320 | APSR.N = result<31>; |
| 2321 | APSR.Z = IsZeroBit(result); |
| 2322 | APSR.C = carry; |
| 2323 | // APSR.V unchanged |
| 2324 | #endif |
| 2325 | |
| 2326 | return EmulateShiftImm(encoding, SRType_RRX); |
| 2327 | } |
| 2328 | |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2329 | bool |
| 2330 | EmulateInstructionARM::EmulateShiftImm (ARMEncoding encoding, ARM_ShifterType shift_type) |
| 2331 | { |
| 2332 | assert(shift_type == SRType_ASR || shift_type == SRType_LSL || shift_type == SRType_LSR); |
| 2333 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2334 | bool success = false; |
| 2335 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2336 | if (!success) |
| 2337 | return false; |
| 2338 | |
| 2339 | if (ConditionPassed()) |
| 2340 | { |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 2341 | uint32_t Rd; // the destination register |
| 2342 | uint32_t Rm; // the first operand register |
| 2343 | uint32_t imm5; // encoding for the shift amount |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2344 | uint32_t carry; // the carry bit after the shift operation |
| 2345 | bool setflags; |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2346 | |
| 2347 | // Special case handling! |
| 2348 | // A8.6.139 ROR (immediate) -- Encoding T1 |
| 2349 | if (shift_type == SRType_ROR && encoding == eEncodingT1) |
| 2350 | { |
| 2351 | // Morph the T1 encoding from the ARM Architecture Manual into T2 encoding to |
| 2352 | // have the same decoding of bit fields as the other Thumb2 shift operations. |
| 2353 | encoding = eEncodingT2; |
| 2354 | } |
| 2355 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2356 | switch (encoding) { |
| 2357 | case eEncodingT1: |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2358 | // Due to the above special case handling! |
| 2359 | assert(shift_type != SRType_ROR); |
| 2360 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2361 | Rd = Bits32(opcode, 2, 0); |
| 2362 | Rm = Bits32(opcode, 5, 3); |
| 2363 | setflags = !InITBlock(); |
| 2364 | imm5 = Bits32(opcode, 10, 6); |
| 2365 | break; |
| 2366 | case eEncodingT2: |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2367 | // A8.6.141 RRX |
| 2368 | assert(shift_type != SRType_RRX); |
| 2369 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2370 | Rd = Bits32(opcode, 11, 8); |
| 2371 | Rm = Bits32(opcode, 3, 0); |
| 2372 | setflags = BitIsSet(opcode, 20); |
| 2373 | imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); |
| 2374 | if (BadReg(Rd) || BadReg(Rm)) |
| 2375 | return false; |
| 2376 | break; |
| 2377 | case eEncodingA1: |
| 2378 | Rd = Bits32(opcode, 15, 12); |
| 2379 | Rm = Bits32(opcode, 3, 0); |
| 2380 | setflags = BitIsSet(opcode, 20); |
| 2381 | imm5 = Bits32(opcode, 11, 7); |
| 2382 | break; |
| 2383 | default: |
| 2384 | return false; |
| 2385 | } |
| 2386 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2387 | // A8.6.139 ROR (immediate) |
| 2388 | if (shift_type == SRType_ROR && imm5 == 0) |
| 2389 | shift_type = SRType_RRX; |
| 2390 | |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2391 | // Get the first operand. |
| 2392 | uint32_t value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 2393 | if (!success) |
| 2394 | return false; |
| 2395 | |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 2396 | // Decode the shift amount if not RRX. |
| 2397 | uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2398 | |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2399 | uint32_t result = Shift_C(value, shift_type, amt, Bit32(m_inst_cpsr, CPSR_C), carry); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2400 | |
| 2401 | // The context specifies that an immediate is to be moved into Rd. |
| 2402 | EmulateInstruction::Context context; |
| 2403 | context.type = EmulateInstruction::eContextImmediate; |
| 2404 | context.SetNoArgs (); |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2405 | |
| 2406 | if (Rd == 15) |
| 2407 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 2408 | if (!ALUWritePC (context, result)) |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 2409 | return false; |
| 2410 | } |
| 2411 | else |
| 2412 | { |
| 2413 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 2414 | return false; |
| 2415 | if (setflags) |
| 2416 | { |
| 2417 | m_new_inst_cpsr = m_inst_cpsr; |
| 2418 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 2419 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 2420 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 2421 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2422 | { |
| 2423 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2424 | return false; |
| 2425 | } |
| 2426 | } |
| 2427 | } |
| 2428 | } |
| 2429 | return true; |
| 2430 | } |
| 2431 | |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 2432 | bool |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2433 | EmulateInstructionARM::EmulateShiftReg (ARMEncoding encoding, ARM_ShifterType shift_type) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 2434 | { |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2435 | assert(shift_type == SRType_ASR || shift_type == SRType_LSL || shift_type == SRType_LSR); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 2436 | |
| 2437 | bool success = false; |
| 2438 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2439 | if (!success) |
| 2440 | return false; |
| 2441 | |
| 2442 | if (ConditionPassed()) |
| 2443 | { |
| 2444 | uint32_t Rd; // the destination register |
| 2445 | uint32_t Rn; // the first operand register |
| 2446 | uint32_t Rm; // the register whose bottom byte contains the amount to shift by |
| 2447 | uint32_t carry; // the carry bit after the shift operation |
| 2448 | bool setflags; |
| 2449 | switch (encoding) { |
| 2450 | case eEncodingT1: |
| 2451 | Rd = Bits32(opcode, 2, 0); |
| 2452 | Rn = Rd; |
| 2453 | Rm = Bits32(opcode, 5, 3); |
| 2454 | setflags = !InITBlock(); |
| 2455 | break; |
| 2456 | case eEncodingT2: |
| 2457 | Rd = Bits32(opcode, 11, 8); |
| 2458 | Rn = Bits32(opcode, 19, 16); |
| 2459 | Rm = Bits32(opcode, 3, 0); |
| 2460 | setflags = BitIsSet(opcode, 20); |
| 2461 | if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) |
| 2462 | return false; |
| 2463 | break; |
| 2464 | case eEncodingA1: |
| 2465 | Rd = Bits32(opcode, 15, 12); |
| 2466 | Rn = Bits32(opcode, 3, 0); |
| 2467 | Rm = Bits32(opcode, 11, 8); |
| 2468 | setflags = BitIsSet(opcode, 20); |
| 2469 | if (Rd == 15 || Rn == 15 || Rm == 15) |
| 2470 | return false; |
| 2471 | break; |
| 2472 | default: |
| 2473 | return false; |
| 2474 | } |
| 2475 | |
| 2476 | // Get the first operand. |
| 2477 | uint32_t value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 2478 | if (!success) |
| 2479 | return false; |
| 2480 | // Get the Rm register content. |
| 2481 | uint32_t val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + Rm, 0, &success); |
| 2482 | if (!success) |
| 2483 | return false; |
| 2484 | |
| 2485 | // Get the shift amount. |
| 2486 | uint32_t amt = Bits32(val, 7, 0); |
| 2487 | |
Johnny Chen | 41a0a15 | 2011-02-16 01:27:54 +0000 | [diff] [blame] | 2488 | uint32_t result = Shift_C(value, shift_type, amt, Bit32(m_inst_cpsr, CPSR_C), carry); |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 2489 | |
| 2490 | // The context specifies that an immediate is to be moved into Rd. |
| 2491 | EmulateInstruction::Context context; |
| 2492 | context.type = EmulateInstruction::eContextImmediate; |
| 2493 | context.SetNoArgs (); |
| 2494 | |
| 2495 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) |
| 2496 | return false; |
| 2497 | if (setflags) |
| 2498 | { |
| 2499 | m_new_inst_cpsr = m_inst_cpsr; |
| 2500 | SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); |
| 2501 | SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); |
| 2502 | SetBit32(m_new_inst_cpsr, CPSR_C, carry); |
| 2503 | if (m_new_inst_cpsr != m_inst_cpsr) |
| 2504 | { |
| 2505 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
| 2506 | return false; |
| 2507 | } |
| 2508 | } |
| 2509 | } |
| 2510 | return true; |
| 2511 | } |
| 2512 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2513 | // LDM loads multiple registers from consecutive memory locations, using an |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2514 | // address from a base register. Optionally the address just above the highest of those locations |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2515 | // can be written back to the base register. |
| 2516 | bool |
| 2517 | EmulateInstructionARM::EmulateLDM (ARMEncoding encoding) |
| 2518 | { |
| 2519 | #if 0 |
| 2520 | // ARM pseudo code... |
| 2521 | if ConditionPassed() |
| 2522 | EncodingSpecificOperations(); NullCheckIfThumbEE (n); |
| 2523 | address = R[n]; |
| 2524 | |
| 2525 | for i = 0 to 14 |
| 2526 | if registers<i> == '1' then |
| 2527 | R[i] = MemA[address, 4]; address = address + 4; |
| 2528 | if registers<15> == '1' then |
| 2529 | LoadWritePC (MemA[address, 4]); |
| 2530 | |
| 2531 | if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers); |
| 2532 | if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2533 | |
| 2534 | #endif |
| 2535 | |
| 2536 | bool success = false; |
| 2537 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2538 | if (!success) |
| 2539 | return false; |
| 2540 | |
| 2541 | if (ConditionPassed()) |
| 2542 | { |
| 2543 | uint32_t n; |
| 2544 | uint32_t registers = 0; |
| 2545 | bool wback; |
| 2546 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2547 | switch (encoding) |
| 2548 | { |
| 2549 | case eEncodingT1: |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2550 | // n = UInt(Rn); registers = ’00000000’:register_list; wback = (registers<n> == ’0’); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2551 | n = Bits32 (opcode, 10, 8); |
| 2552 | registers = Bits32 (opcode, 7, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2553 | registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2554 | wback = BitIsClear (registers, n); |
| 2555 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 2556 | if (BitCount(registers) < 1) |
| 2557 | return false; |
| 2558 | break; |
| 2559 | case eEncodingT2: |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2560 | // if W == ’1’ && Rn == ’1101’ then SEE POP; |
| 2561 | // n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ’1’); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2562 | n = Bits32 (opcode, 19, 16); |
| 2563 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2564 | registers = registers & 0xdfff; // Make sure bit 13 is zero. |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2565 | wback = BitIsSet (opcode, 21); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2566 | |
| 2567 | // if n == 15 || BitCount(registers) < 2 || (P == ’1’ && M == ’1’) then UNPREDICTABLE; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2568 | if ((n == 15) |
| 2569 | || (BitCount (registers) < 2) |
| 2570 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2571 | return false; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2572 | |
| 2573 | // if registers<15> == ’1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2574 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2575 | return false; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2576 | |
| 2577 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2578 | if (wback |
| 2579 | && BitIsSet (registers, n)) |
| 2580 | return false; |
| 2581 | break; |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2582 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2583 | case eEncodingA1: |
| 2584 | n = Bits32 (opcode, 19, 16); |
| 2585 | registers = Bits32 (opcode, 15, 0); |
| 2586 | wback = BitIsSet (opcode, 21); |
| 2587 | if ((n == 15) |
| 2588 | || (BitCount (registers) < 1)) |
| 2589 | return false; |
| 2590 | break; |
| 2591 | default: |
| 2592 | return false; |
| 2593 | } |
| 2594 | |
| 2595 | int32_t offset = 0; |
| 2596 | const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2597 | if (!success) |
| 2598 | return false; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2599 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2600 | EmulateInstruction::Context context; |
| 2601 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2602 | Register dwarf_reg; |
| 2603 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2604 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2605 | |
| 2606 | for (int i = 0; i < 14; ++i) |
| 2607 | { |
| 2608 | if (BitIsSet (registers, i)) |
| 2609 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2610 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2611 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2612 | if (wback && (n == 13)) // Pop Instruction |
| 2613 | context.type = EmulateInstruction::eContextPopRegisterOffStack; |
| 2614 | |
| 2615 | // R[i] = MemA [address, 4]; address = address + 4; |
| 2616 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2617 | if (!success) |
| 2618 | return false; |
| 2619 | |
| 2620 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2621 | return false; |
| 2622 | |
| 2623 | offset += addr_byte_size; |
| 2624 | } |
| 2625 | } |
| 2626 | |
| 2627 | if (BitIsSet (registers, 15)) |
| 2628 | { |
| 2629 | //LoadWritePC (MemA [address, 4]); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2630 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2631 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2632 | uint32_t data = ReadMemoryUnsigned (context, base_address + offset, addr_byte_size, 0, &success); |
| 2633 | if (!success) |
| 2634 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2635 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 2636 | if (!LoadWritePC(context, data)) |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2637 | return false; |
| 2638 | } |
| 2639 | |
| 2640 | if (wback && BitIsClear (registers, n)) |
| 2641 | { |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2642 | // R[n] = R[n] + 4 * BitCount (registers) |
| 2643 | int32_t offset = addr_byte_size * BitCount (registers); |
| 2644 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2645 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2646 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2647 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset)) |
| 2648 | return false; |
| 2649 | } |
| 2650 | if (wback && BitIsSet (registers, n)) |
| 2651 | // R[n] bits(32) UNKNOWN; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2652 | return WriteBits32Unknown (n); |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2653 | } |
| 2654 | return true; |
| 2655 | } |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2656 | |
| 2657 | // LDMDA loads multiple registers from consecutive memory locations using an address from a base registers. |
| 2658 | // The consecutive memorty locations end at this address and the address just below the lowest of those locations |
| 2659 | // can optionally be written back tot he base registers. |
| 2660 | bool |
| 2661 | EmulateInstructionARM::EmulateLDMDA (ARMEncoding encoding) |
| 2662 | { |
| 2663 | #if 0 |
| 2664 | // ARM pseudo code... |
| 2665 | if ConditionPassed() then |
| 2666 | EncodingSpecificOperations(); |
| 2667 | address = R[n] - 4*BitCount(registers) + 4; |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 2668 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2669 | for i = 0 to 14 |
| 2670 | if registers<i> == ’1’ then |
| 2671 | R[i] = MemA[address,4]; address = address + 4; |
| 2672 | |
| 2673 | if registers<15> == ’1’ then |
| 2674 | LoadWritePC(MemA[address,4]); |
| 2675 | |
| 2676 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2677 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2678 | #endif |
| 2679 | |
| 2680 | bool success = false; |
| 2681 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2682 | if (!success) |
| 2683 | return false; |
| 2684 | |
| 2685 | if (ConditionPassed()) |
| 2686 | { |
| 2687 | uint32_t n; |
| 2688 | uint32_t registers = 0; |
| 2689 | bool wback; |
| 2690 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2691 | |
| 2692 | // EncodingSpecificOperations(); |
| 2693 | switch (encoding) |
| 2694 | { |
| 2695 | case eEncodingA1: |
| 2696 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2697 | n = Bits32 (opcode, 19, 16); |
| 2698 | registers = Bits32 (opcode, 15, 0); |
| 2699 | wback = BitIsSet (opcode, 21); |
| 2700 | |
| 2701 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2702 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2703 | return false; |
| 2704 | |
| 2705 | break; |
| 2706 | |
| 2707 | default: |
| 2708 | return false; |
| 2709 | } |
| 2710 | // address = R[n] - 4*BitCount(registers) + 4; |
| 2711 | |
| 2712 | int32_t offset = 0; |
| 2713 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2714 | |
| 2715 | if (!success) |
| 2716 | return false; |
| 2717 | |
| 2718 | address = address - (addr_byte_size * BitCount (registers)) + addr_byte_size; |
| 2719 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2720 | EmulateInstruction::Context context; |
| 2721 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2722 | Register dwarf_reg; |
| 2723 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2724 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2725 | |
| 2726 | // for i = 0 to 14 |
| 2727 | for (int i = 0; i < 14; ++i) |
| 2728 | { |
| 2729 | // if registers<i> == ’1’ then |
| 2730 | if (BitIsSet (registers, i)) |
| 2731 | { |
| 2732 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2733 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2734 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2735 | if (!success) |
| 2736 | return false; |
| 2737 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2738 | return false; |
| 2739 | offset += addr_byte_size; |
| 2740 | } |
| 2741 | } |
| 2742 | |
| 2743 | // if registers<15> == ’1’ then |
| 2744 | // LoadWritePC(MemA[address,4]); |
| 2745 | if (BitIsSet (registers, 15)) |
| 2746 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2747 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2748 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2749 | if (!success) |
| 2750 | return false; |
Johnny Chen | 44c10f0 | 2011-02-11 19:37:03 +0000 | [diff] [blame] | 2751 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 2752 | if (!LoadWritePC(context, data)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2753 | return false; |
| 2754 | } |
| 2755 | |
| 2756 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2757 | if (wback && BitIsClear (registers, n)) |
| 2758 | { |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2759 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2760 | if (!success) |
| 2761 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2762 | |
| 2763 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2764 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2765 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2766 | addr = addr + offset; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2767 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2768 | return false; |
| 2769 | } |
| 2770 | |
| 2771 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2772 | if (wback && BitIsSet (registers, n)) |
| 2773 | return WriteBits32Unknown (n); |
| 2774 | } |
| 2775 | return true; |
| 2776 | } |
| 2777 | |
| 2778 | // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2779 | // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can |
| 2780 | // be optionally written back to the base register. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2781 | bool |
| 2782 | EmulateInstructionARM::EmulateLDMDB (ARMEncoding encoding) |
| 2783 | { |
| 2784 | #if 0 |
| 2785 | // ARM pseudo code... |
| 2786 | if ConditionPassed() then |
| 2787 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 2788 | address = R[n] - 4*BitCount(registers); |
| 2789 | |
| 2790 | for i = 0 to 14 |
| 2791 | if registers<i> == ’1’ then |
| 2792 | R[i] = MemA[address,4]; address = address + 4; |
| 2793 | if registers<15> == ’1’ then |
| 2794 | LoadWritePC(MemA[address,4]); |
| 2795 | |
| 2796 | if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2797 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2798 | #endif |
| 2799 | |
| 2800 | bool success = false; |
| 2801 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2802 | if (!success) |
| 2803 | return false; |
| 2804 | |
| 2805 | if (ConditionPassed()) |
| 2806 | { |
| 2807 | uint32_t n; |
| 2808 | uint32_t registers = 0; |
| 2809 | bool wback; |
| 2810 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2811 | switch (encoding) |
| 2812 | { |
| 2813 | case eEncodingT1: |
| 2814 | // n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ’1’); |
| 2815 | n = Bits32 (opcode, 19, 16); |
| 2816 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 2817 | registers = registers & 0xdfff; // Make sure bit 13 is a zero. |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2818 | wback = BitIsSet (opcode, 21); |
| 2819 | |
| 2820 | // if n == 15 || BitCount(registers) < 2 || (P == ’1’ && M == ’1’) then UNPREDICTABLE; |
| 2821 | if ((n == 15) |
| 2822 | || (BitCount (registers) < 2) |
| 2823 | || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) |
| 2824 | return false; |
| 2825 | |
| 2826 | // if registers<15> == ’1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE; |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 2827 | if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2828 | return false; |
| 2829 | |
| 2830 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 2831 | if (wback && BitIsSet (registers, n)) |
| 2832 | return false; |
| 2833 | |
| 2834 | break; |
| 2835 | |
| 2836 | case eEncodingA1: |
| 2837 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2838 | n = Bits32 (opcode, 19, 16); |
| 2839 | registers = Bits32 (opcode, 15, 0); |
| 2840 | wback = BitIsSet (opcode, 21); |
| 2841 | |
| 2842 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2843 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2844 | return false; |
| 2845 | |
| 2846 | break; |
| 2847 | |
| 2848 | default: |
| 2849 | return false; |
| 2850 | } |
| 2851 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2852 | // address = R[n] - 4*BitCount(registers); |
| 2853 | |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2854 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2855 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2856 | |
| 2857 | if (!success) |
| 2858 | return false; |
| 2859 | |
| 2860 | address = address - (addr_byte_size * BitCount (registers)); |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2861 | EmulateInstruction::Context context; |
| 2862 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2863 | Register dwarf_reg; |
| 2864 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2865 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2866 | |
| 2867 | for (int i = 0; i < 14; ++i) |
| 2868 | { |
| 2869 | if (BitIsSet (registers, i)) |
| 2870 | { |
| 2871 | // R[i] = MemA[address,4]; address = address + 4; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2872 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2873 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2874 | if (!success) |
| 2875 | return false; |
| 2876 | |
| 2877 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2878 | return false; |
| 2879 | |
| 2880 | offset += addr_byte_size; |
| 2881 | } |
| 2882 | } |
| 2883 | |
| 2884 | // if registers<15> == ’1’ then |
| 2885 | // LoadWritePC(MemA[address,4]); |
| 2886 | if (BitIsSet (registers, 15)) |
| 2887 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2888 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2889 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2890 | if (!success) |
| 2891 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 2892 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 2893 | if (!LoadWritePC(context, data)) |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2894 | return false; |
| 2895 | } |
| 2896 | |
| 2897 | // if wback && registers<n> == ’0’ then R[n] = R[n] - 4*BitCount(registers); |
| 2898 | if (wback && BitIsClear (registers, n)) |
| 2899 | { |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2900 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2901 | if (!success) |
| 2902 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2903 | |
| 2904 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 2905 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2906 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 2907 | addr = addr + offset; |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2908 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 2909 | return false; |
| 2910 | } |
| 2911 | |
| 2912 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 2913 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2914 | return WriteBits32Unknown (n); |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 2915 | } |
| 2916 | return true; |
| 2917 | } |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2918 | |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2919 | // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The |
| 2920 | // consecutive memory locations start just above this address, and thea ddress of the last of those locations can |
| 2921 | // optinoally be written back to the base register. |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2922 | bool |
| 2923 | EmulateInstructionARM::EmulateLDMIB (ARMEncoding encoding) |
| 2924 | { |
| 2925 | #if 0 |
| 2926 | if ConditionPassed() then |
| 2927 | EncodingSpecificOperations(); |
| 2928 | address = R[n] + 4; |
| 2929 | |
| 2930 | for i = 0 to 14 |
| 2931 | if registers<i> == ’1’ then |
| 2932 | R[i] = MemA[address,4]; address = address + 4; |
| 2933 | if registers<15> == ’1’ then |
| 2934 | LoadWritePC(MemA[address,4]); |
| 2935 | |
| 2936 | if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 2937 | if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; |
| 2938 | #endif |
| 2939 | |
| 2940 | bool success = false; |
| 2941 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 2942 | if (!success) |
| 2943 | return false; |
| 2944 | |
| 2945 | if (ConditionPassed()) |
| 2946 | { |
| 2947 | uint32_t n; |
| 2948 | uint32_t registers = 0; |
| 2949 | bool wback; |
| 2950 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 2951 | switch (encoding) |
| 2952 | { |
| 2953 | case eEncodingA1: |
| 2954 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 2955 | n = Bits32 (opcode, 19, 16); |
| 2956 | registers = Bits32 (opcode, 15, 0); |
| 2957 | wback = BitIsSet (opcode, 21); |
| 2958 | |
| 2959 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 2960 | if ((n == 15) || (BitCount (registers) < 1)) |
| 2961 | return false; |
| 2962 | |
| 2963 | break; |
| 2964 | default: |
| 2965 | return false; |
| 2966 | } |
| 2967 | // address = R[n] + 4; |
| 2968 | |
| 2969 | int32_t offset = 0; |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 2970 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 2971 | |
| 2972 | if (!success) |
| 2973 | return false; |
| 2974 | |
| 2975 | address = address + addr_byte_size; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2976 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2977 | EmulateInstruction::Context context; |
| 2978 | context.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 2979 | Register dwarf_reg; |
| 2980 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 2981 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2982 | |
| 2983 | for (int i = 0; i < 14; ++i) |
| 2984 | { |
| 2985 | if (BitIsSet (registers, i)) |
| 2986 | { |
| 2987 | // R[i] = MemA[address,4]; address = address + 4; |
| 2988 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 2989 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 2990 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 2991 | if (!success) |
| 2992 | return false; |
| 2993 | |
| 2994 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data)) |
| 2995 | return false; |
| 2996 | |
| 2997 | offset += addr_byte_size; |
| 2998 | } |
| 2999 | } |
| 3000 | |
| 3001 | // if registers<15> == ’1’ then |
| 3002 | // LoadWritePC(MemA[address,4]); |
| 3003 | if (BitIsSet (registers, 15)) |
| 3004 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3005 | context.SetRegisterPlusOffset (dwarf_reg, offset); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3006 | uint32_t data = ReadMemoryUnsigned (context, address + offset, addr_byte_size, 0, &success); |
| 3007 | if (!success) |
| 3008 | return false; |
Johnny Chen | e62b50d | 2011-02-09 22:02:17 +0000 | [diff] [blame] | 3009 | // In ARMv5T and above, this is an interworking branch. |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3010 | if (!LoadWritePC(context, data)) |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3011 | return false; |
| 3012 | } |
| 3013 | |
| 3014 | // if wback && registers<n> == ’0’ then R[n] = R[n] + 4*BitCount(registers); |
| 3015 | if (wback && BitIsClear (registers, n)) |
| 3016 | { |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3017 | addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3018 | if (!success) |
| 3019 | return false; |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3020 | |
| 3021 | offset = addr_byte_size * BitCount (registers); |
| 3022 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3023 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3024 | addr = addr + offset; |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3025 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) |
| 3026 | return false; |
| 3027 | } |
| 3028 | |
| 3029 | // if wback && registers<n> == ’1’ then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 3030 | if (wback && BitIsSet (registers, n)) |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 3031 | return WriteBits32Unknown (n); |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 3032 | } |
| 3033 | return true; |
| 3034 | } |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 3035 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3036 | // Load Register (immediate) calculates an address from a base register value and |
| 3037 | // an immediate offset, loads a word from memory, and writes to a register. |
| 3038 | // LDR (immediate, Thumb) |
| 3039 | bool |
| 3040 | EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding) |
| 3041 | { |
| 3042 | #if 0 |
| 3043 | // ARM pseudo code... |
| 3044 | if (ConditionPassed()) |
| 3045 | { |
| 3046 | EncodingSpecificOperations(); NullCheckIfThumbEE(15); |
| 3047 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 3048 | address = if index then offset_addr else R[n]; |
| 3049 | data = MemU[address,4]; |
| 3050 | if wback then R[n] = offset_addr; |
| 3051 | if t == 15 then |
| 3052 | if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; |
| 3053 | elsif UnalignedSupport() || address<1:0> = '00' then |
| 3054 | R[t] = data; |
| 3055 | else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7 |
| 3056 | } |
| 3057 | #endif |
| 3058 | |
| 3059 | bool success = false; |
| 3060 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3061 | if (!success) |
| 3062 | return false; |
| 3063 | |
| 3064 | if (ConditionPassed()) |
| 3065 | { |
| 3066 | uint32_t Rt; // the destination register |
| 3067 | uint32_t Rn; // the base register |
| 3068 | uint32_t imm32; // the immediate offset used to form the address |
| 3069 | addr_t offset_addr; // the offset address |
| 3070 | addr_t address; // the calculated address |
| 3071 | uint32_t data; // the literal data value from memory load |
| 3072 | bool add, index, wback; |
| 3073 | switch (encoding) { |
| 3074 | case eEncodingT1: |
| 3075 | Rt = Bits32(opcode, 5, 3); |
| 3076 | Rn = Bits32(opcode, 2, 0); |
| 3077 | imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); |
| 3078 | // index = TRUE; add = TRUE; wback = FALSE |
| 3079 | add = true; |
| 3080 | index = true; |
| 3081 | wback = false; |
| 3082 | break; |
| 3083 | default: |
| 3084 | return false; |
| 3085 | } |
| 3086 | uint32_t base = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + Rn, 0, &success); |
| 3087 | if (!success) |
| 3088 | return false; |
| 3089 | if (add) |
| 3090 | offset_addr = base + imm32; |
| 3091 | else |
| 3092 | offset_addr = base - imm32; |
| 3093 | |
| 3094 | address = (index ? offset_addr : base); |
| 3095 | |
| 3096 | if (wback) |
| 3097 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3098 | EmulateInstruction::Context ctx; |
| 3099 | ctx.type = EmulateInstruction::eContextRegisterPlusOffset; |
| 3100 | Register dwarf_reg; |
| 3101 | dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rn); |
| 3102 | ctx.SetRegisterPlusOffset (dwarf_reg, (int32_t) (offset_addr - base)); |
| 3103 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3104 | if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr)) |
| 3105 | return false; |
| 3106 | } |
| 3107 | |
| 3108 | // Prepare to write to the Rt register. |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3109 | EmulateInstruction::Context context; |
| 3110 | context.type = EmulateInstruction::eContextImmediate; |
| 3111 | context.SetNoArgs (); |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3112 | |
| 3113 | // Read memory from the address. |
| 3114 | data = ReadMemoryUnsigned(context, address, 4, 0, &success); |
| 3115 | if (!success) |
| 3116 | return false; |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3117 | |
| 3118 | if (Rt == 15) |
| 3119 | { |
| 3120 | if (Bits32(address, 1, 0) == 0) |
| 3121 | { |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 3122 | if (!LoadWritePC(context, data)) |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 3123 | return false; |
| 3124 | } |
| 3125 | else |
| 3126 | return false; |
| 3127 | } |
| 3128 | else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) |
| 3129 | { |
| 3130 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data)) |
| 3131 | return false; |
| 3132 | } |
| 3133 | else |
| 3134 | return false; |
| 3135 | } |
| 3136 | return true; |
| 3137 | } |
| 3138 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3139 | // STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address |
| 3140 | // from a base register. The consecutive memory locations start at this address, and teh address just above the last |
| 3141 | // of those locations can optionally be written back to the base register. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3142 | bool |
| 3143 | EmulateInstructionARM::EmulateSTM (ARMEncoding encoding) |
| 3144 | { |
| 3145 | #if 0 |
| 3146 | if ConditionPassed() then |
| 3147 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3148 | address = R[n]; |
| 3149 | |
| 3150 | for i = 0 to 14 |
| 3151 | if registers<i> == ’1’ then |
| 3152 | if i == n && wback && i != LowestSetBit(registers) then |
| 3153 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 3154 | else |
| 3155 | MemA[address,4] = R[i]; |
| 3156 | address = address + 4; |
| 3157 | |
| 3158 | if registers<15> == ’1’ then // Only possible for encoding A1 |
| 3159 | MemA[address,4] = PCStoreValue(); |
| 3160 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3161 | #endif |
| 3162 | |
| 3163 | bool success = false; |
| 3164 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3165 | if (!success) |
| 3166 | return false; |
| 3167 | |
| 3168 | if (ConditionPassed ()) |
| 3169 | { |
| 3170 | uint32_t n; |
| 3171 | uint32_t registers = 0; |
| 3172 | bool wback; |
| 3173 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3174 | |
| 3175 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3176 | switch (encoding) |
| 3177 | { |
| 3178 | case eEncodingT1: |
| 3179 | // n = UInt(Rn); registers = ’00000000’:register_list; wback = TRUE; |
| 3180 | n = Bits32 (opcode, 10, 8); |
| 3181 | registers = Bits32 (opcode, 7, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3182 | registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3183 | wback = true; |
| 3184 | |
| 3185 | // if BitCount(registers) < 1 then UNPREDICTABLE; |
| 3186 | if (BitCount (registers) < 1) |
| 3187 | return false; |
| 3188 | |
| 3189 | break; |
| 3190 | |
| 3191 | case eEncodingT2: |
| 3192 | // n = UInt(Rn); registers = ’0’:M:’0’:register_list; wback = (W == ’1’); |
| 3193 | n = Bits32 (opcode, 19, 16); |
| 3194 | registers = Bits32 (opcode, 15, 0); |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3195 | registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3196 | wback = BitIsSet (opcode, 21); |
| 3197 | |
| 3198 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 3199 | if ((n == 15) || (BitCount (registers) < 2)) |
| 3200 | return false; |
| 3201 | |
| 3202 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 3203 | if (wback && BitIsSet (registers, n)) |
| 3204 | return false; |
| 3205 | |
| 3206 | break; |
| 3207 | |
| 3208 | case eEncodingA1: |
| 3209 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 3210 | n = Bits32 (opcode, 19, 16); |
| 3211 | registers = Bits32 (opcode, 15, 0); |
| 3212 | wback = BitIsSet (opcode, 21); |
| 3213 | |
| 3214 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3215 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3216 | return false; |
| 3217 | |
| 3218 | break; |
| 3219 | |
| 3220 | default: |
| 3221 | return false; |
| 3222 | } |
| 3223 | |
| 3224 | // address = R[n]; |
| 3225 | int32_t offset = 0; |
| 3226 | const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3227 | if (!success) |
| 3228 | return false; |
| 3229 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3230 | EmulateInstruction::Context context; |
| 3231 | context.type = EmulateInstruction::eContextRegisterStore; |
| 3232 | Register base_reg; |
| 3233 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3234 | |
| 3235 | // for i = 0 to 14 |
| 3236 | for (int i = 0; i < 14; ++i) |
| 3237 | { |
| 3238 | int lowest_set_bit = 14; |
| 3239 | // if registers<i> == ’1’ then |
| 3240 | if (BitIsSet (registers, i)) |
| 3241 | { |
| 3242 | if (i < lowest_set_bit) |
| 3243 | lowest_set_bit = i; |
| 3244 | // if i == n && wback && i != LowestSetBit(registers) then |
| 3245 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 3246 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 |
| 3247 | WriteBits32UnknownToMemory (address + offset); |
| 3248 | else |
| 3249 | { |
| 3250 | // MemA[address,4] = R[i]; |
| 3251 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 3252 | if (!success) |
| 3253 | return false; |
| 3254 | |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3255 | Register data_reg; |
| 3256 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 3257 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3258 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 3259 | return false; |
| 3260 | } |
| 3261 | |
| 3262 | // address = address + 4; |
| 3263 | offset += addr_byte_size; |
| 3264 | } |
| 3265 | } |
| 3266 | |
| 3267 | // if registers<15> == ’1’ then // Only possible for encoding A1 |
| 3268 | // MemA[address,4] = PCStoreValue(); |
| 3269 | if (BitIsSet (registers, 15)) |
| 3270 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3271 | Register pc_reg; |
| 3272 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 3273 | context.SetRegisterPlusOffset (pc_reg, 8); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3274 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 3275 | if (!success) |
| 3276 | return false; |
| 3277 | |
| 3278 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 3279 | return false; |
| 3280 | } |
| 3281 | |
| 3282 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3283 | if (wback) |
| 3284 | { |
| 3285 | offset = addr_byte_size * BitCount (registers); |
| 3286 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 3287 | context.SetImmediateSigned (offset); |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 3288 | addr_t data = address + offset; |
| 3289 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3290 | return false; |
| 3291 | } |
| 3292 | } |
| 3293 | return true; |
| 3294 | } |
| 3295 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3296 | // STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address |
| 3297 | // from a base register. The consecutive memory locations end at this address, and the address just below the lowest |
| 3298 | // of those locations can optionally be written back to the base register. |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3299 | bool |
| 3300 | EmulateInstructionARM::EmulateSTMDA (ARMEncoding encoding) |
| 3301 | { |
| 3302 | #if 0 |
| 3303 | if ConditionPassed() then |
| 3304 | EncodingSpecificOperations(); |
| 3305 | address = R[n] - 4*BitCount(registers) + 4; |
| 3306 | |
| 3307 | for i = 0 to 14 |
| 3308 | if registers<i> == ’1’ then |
| 3309 | if i == n && wback && i != LowestSetBit(registers) then |
| 3310 | MemA[address,4] = bits(32) UNKNOWN; |
| 3311 | else |
| 3312 | MemA[address,4] = R[i]; |
| 3313 | address = address + 4; |
| 3314 | |
| 3315 | if registers<15> == ’1’ then |
| 3316 | MemA[address,4] = PCStoreValue(); |
| 3317 | |
| 3318 | if wback then R[n] = R[n] - 4*BitCount(registers); |
| 3319 | #endif |
| 3320 | |
| 3321 | bool success = false; |
| 3322 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3323 | if (!success) |
| 3324 | return false; |
| 3325 | |
| 3326 | if (ConditionPassed ()) |
| 3327 | { |
| 3328 | uint32_t n; |
| 3329 | uint32_t registers = 0; |
| 3330 | bool wback; |
| 3331 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3332 | |
| 3333 | // EncodingSpecificOperations(); |
| 3334 | switch (encoding) |
| 3335 | { |
| 3336 | case eEncodingA1: |
| 3337 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 3338 | n = Bits32 (opcode, 19, 16); |
| 3339 | registers = Bits32 (opcode, 15, 0); |
| 3340 | wback = BitIsSet (opcode, 21); |
| 3341 | |
| 3342 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3343 | if ((n == 15) || (BitCount (registers) < 1)) |
| 3344 | return false; |
| 3345 | break; |
| 3346 | default: |
| 3347 | return false; |
| 3348 | } |
| 3349 | |
| 3350 | // address = R[n] - 4*BitCount(registers) + 4; |
| 3351 | int32_t offset = 0; |
| 3352 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3353 | if (!success) |
| 3354 | return false; |
| 3355 | |
| 3356 | address = address - (addr_byte_size * BitCount (registers)) + 4; |
| 3357 | |
| 3358 | EmulateInstruction::Context context; |
| 3359 | context.type = EmulateInstruction::eContextRegisterStore; |
| 3360 | Register base_reg; |
| 3361 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3362 | |
| 3363 | // for i = 0 to 14 |
| 3364 | for (int i = 0; i < 14; ++i) |
| 3365 | { |
| 3366 | int lowest_bit_set = 14; |
| 3367 | // if registers<i> == ’1’ then |
| 3368 | if (BitIsSet (registers, i)) |
| 3369 | { |
| 3370 | if (i < lowest_bit_set) |
| 3371 | lowest_bit_set = i; |
| 3372 | //if i == n && wback && i != LowestSetBit(registers) then |
| 3373 | if ((i == n) && wback && (i != lowest_bit_set)) |
| 3374 | // MemA[address,4] = bits(32) UNKNOWN; |
| 3375 | WriteBits32UnknownToMemory (address + offset); |
| 3376 | else |
| 3377 | { |
| 3378 | // MemA[address,4] = R[i]; |
| 3379 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 3380 | if (!success) |
| 3381 | return false; |
| 3382 | |
| 3383 | Register data_reg; |
| 3384 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 3385 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
| 3386 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 3387 | return false; |
| 3388 | } |
| 3389 | |
| 3390 | // address = address + 4; |
| 3391 | offset += addr_byte_size; |
| 3392 | } |
| 3393 | } |
| 3394 | |
| 3395 | // if registers<15> == ’1’ then |
| 3396 | // MemA[address,4] = PCStoreValue(); |
| 3397 | if (BitIsSet (registers, 15)) |
| 3398 | { |
| 3399 | Register pc_reg; |
| 3400 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 3401 | context.SetRegisterPlusOffset (pc_reg, 8); |
| 3402 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 3403 | if (!success) |
| 3404 | return false; |
| 3405 | |
| 3406 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 3407 | return false; |
| 3408 | } |
| 3409 | |
| 3410 | // if wback then R[n] = R[n] - 4*BitCount(registers); |
| 3411 | if (wback) |
| 3412 | { |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3413 | offset = (addr_byte_size * BitCount (registers)) * -1; |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 3414 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 3415 | context.SetImmediateSigned (offset); |
| 3416 | addr_t data = address + offset; |
| 3417 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3418 | return false; |
| 3419 | } |
| 3420 | } |
| 3421 | return true; |
| 3422 | } |
| 3423 | |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3424 | // STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address |
| 3425 | // from a base register. The consecutive memory locations end just below this address, and the address of the first of |
| 3426 | // those locations can optionally be written back to the base register. |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3427 | bool |
| 3428 | EmulateInstructionARM::EmulateSTMDB (ARMEncoding encoding) |
| 3429 | { |
| 3430 | #if 0 |
| 3431 | if ConditionPassed() then |
| 3432 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3433 | address = R[n] - 4*BitCount(registers); |
| 3434 | |
| 3435 | for i = 0 to 14 |
| 3436 | if registers<i> == ’1’ then |
| 3437 | if i == n && wback && i != LowestSetBit(registers) then |
| 3438 | MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 3439 | else |
| 3440 | MemA[address,4] = R[i]; |
| 3441 | address = address + 4; |
| 3442 | |
| 3443 | if registers<15> == ’1’ then // Only possible for encoding A1 |
| 3444 | MemA[address,4] = PCStoreValue(); |
| 3445 | |
| 3446 | if wback then R[n] = R[n] - 4*BitCount(registers); |
| 3447 | #endif |
| 3448 | |
| 3449 | |
| 3450 | bool success = false; |
| 3451 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3452 | if (!success) |
| 3453 | return false; |
| 3454 | |
| 3455 | if (ConditionPassed ()) |
| 3456 | { |
| 3457 | uint32_t n; |
| 3458 | uint32_t registers = 0; |
| 3459 | bool wback; |
| 3460 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3461 | |
| 3462 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3463 | switch (encoding) |
| 3464 | { |
| 3465 | case eEncodingT1: |
| 3466 | // if W == ’1’ && Rn == ’1101’ then SEE PUSH; |
| 3467 | if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13)) |
| 3468 | { |
| 3469 | // See PUSH |
| 3470 | } |
| 3471 | // n = UInt(Rn); registers = ’0’:M:’0’:register_list; wback = (W == ’1’); |
| 3472 | n = Bits32 (opcode, 19, 16); |
| 3473 | registers = Bits32 (opcode, 15, 0); |
| 3474 | registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. |
| 3475 | wback = BitIsSet (opcode, 21); |
| 3476 | // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; |
| 3477 | if ((n == 15) || BitCount (registers) < 2) |
| 3478 | return false; |
| 3479 | // if wback && registers<n> == ’1’ then UNPREDICTABLE; |
| 3480 | if (wback && BitIsSet (registers, n)) |
| 3481 | return false; |
| 3482 | break; |
| 3483 | |
| 3484 | case eEncodingA1: |
| 3485 | // if W == ’1’ && Rn == ’1101’ && BitCount(register_list) >= 2 then SEE PUSH; |
| 3486 | if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2) |
| 3487 | { |
| 3488 | // See Push |
| 3489 | } |
| 3490 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 3491 | n = Bits32 (opcode, 19, 16); |
| 3492 | registers = Bits32 (opcode, 15, 0); |
| 3493 | wback = BitIsSet (opcode, 21); |
| 3494 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3495 | if ((n == 15) || BitCount (registers) < 1) |
| 3496 | return false; |
| 3497 | break; |
| 3498 | |
| 3499 | default: |
| 3500 | return false; |
| 3501 | } |
| 3502 | |
| 3503 | // address = R[n] - 4*BitCount(registers); |
| 3504 | |
| 3505 | int32_t offset = 0; |
| 3506 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3507 | if (!success) |
| 3508 | return false; |
| 3509 | |
| 3510 | address = address - (addr_byte_size * BitCount (registers)); |
| 3511 | |
| 3512 | EmulateInstruction::Context context; |
| 3513 | context.type = EmulateInstruction::eContextRegisterStore; |
| 3514 | Register base_reg; |
| 3515 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3516 | |
| 3517 | // for i = 0 to 14 |
| 3518 | for (int i = 0; i < 14; ++i) |
| 3519 | { |
| 3520 | uint32_t lowest_set_bit = 14; |
| 3521 | // if registers<i> == ’1’ then |
| 3522 | if (BitIsSet (registers, i)) |
| 3523 | { |
| 3524 | if (i < lowest_set_bit) |
| 3525 | lowest_set_bit = i; |
| 3526 | // if i == n && wback && i != LowestSetBit(registers) then |
| 3527 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 3528 | // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1 |
| 3529 | WriteBits32UnknownToMemory (address + offset); |
| 3530 | else |
| 3531 | { |
| 3532 | // MemA[address,4] = R[i]; |
| 3533 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 3534 | if (!success) |
| 3535 | return false; |
| 3536 | |
| 3537 | Register data_reg; |
| 3538 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 3539 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
| 3540 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 3541 | return false; |
| 3542 | } |
| 3543 | |
| 3544 | // address = address + 4; |
| 3545 | offset += addr_byte_size; |
| 3546 | } |
| 3547 | } |
| 3548 | |
| 3549 | // if registers<15> == ’1’ then // Only possible for encoding A1 |
| 3550 | // MemA[address,4] = PCStoreValue(); |
| 3551 | if (BitIsSet (registers, 15)) |
| 3552 | { |
| 3553 | Register pc_reg; |
| 3554 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 3555 | context.SetRegisterPlusOffset (pc_reg, 8); |
| 3556 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 3557 | if (!success) |
| 3558 | return false; |
| 3559 | |
| 3560 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 3561 | return false; |
| 3562 | } |
| 3563 | |
| 3564 | // if wback then R[n] = R[n] - 4*BitCount(registers); |
| 3565 | if (wback) |
| 3566 | { |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3567 | offset = (addr_byte_size * BitCount (registers)) * -1; |
| 3568 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 3569 | context.SetImmediateSigned (offset); |
| 3570 | addr_t data = address + offset; |
| 3571 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3572 | return false; |
| 3573 | } |
| 3574 | } |
| 3575 | return true; |
| 3576 | } |
| 3577 | |
| 3578 | // STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address |
| 3579 | // from a base register. The consecutive memory locations start just above this address, and the address of the last |
| 3580 | // of those locations can optionally be written back to the base register. |
| 3581 | bool |
| 3582 | EmulateInstructionARM::EmulateSTMIB (ARMEncoding encoding) |
| 3583 | { |
| 3584 | #if 0 |
| 3585 | if ConditionPassed() then |
| 3586 | EncodingSpecificOperations(); |
| 3587 | address = R[n] + 4; |
| 3588 | |
| 3589 | for i = 0 to 14 |
| 3590 | if registers<i> == ’1’ then |
| 3591 | if i == n && wback && i != LowestSetBit(registers) then |
| 3592 | MemA[address,4] = bits(32) UNKNOWN; |
| 3593 | else |
| 3594 | MemA[address,4] = R[i]; |
| 3595 | address = address + 4; |
| 3596 | |
| 3597 | if registers<15> == ’1’ then |
| 3598 | MemA[address,4] = PCStoreValue(); |
| 3599 | |
| 3600 | if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3601 | #endif |
| 3602 | |
| 3603 | bool success = false; |
| 3604 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3605 | if (!success) |
| 3606 | return false; |
| 3607 | |
| 3608 | if (ConditionPassed()) |
| 3609 | { |
| 3610 | uint32_t n; |
| 3611 | uint32_t registers = 0; |
| 3612 | bool wback; |
| 3613 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3614 | |
| 3615 | // EncodingSpecificOperations(); |
| 3616 | switch (encoding) |
| 3617 | { |
| 3618 | case eEncodingA1: |
| 3619 | // n = UInt(Rn); registers = register_list; wback = (W == ’1’); |
| 3620 | n = Bits32 (opcode, 19, 16); |
| 3621 | registers = Bits32 (opcode, 15, 0); |
| 3622 | wback = BitIsSet (opcode, 21); |
| 3623 | |
| 3624 | // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE; |
| 3625 | if ((n == 15) && (BitCount (registers) < 1)) |
| 3626 | return false; |
| 3627 | break; |
| 3628 | default: |
| 3629 | return false; |
| 3630 | } |
| 3631 | // address = R[n] + 4; |
| 3632 | |
| 3633 | int32_t offset = 0; |
| 3634 | addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3635 | if (!success) |
| 3636 | return false; |
| 3637 | |
| 3638 | address = address + addr_byte_size; |
| 3639 | |
| 3640 | EmulateInstruction::Context context; |
| 3641 | context.type = EmulateInstruction::eContextRegisterStore; |
| 3642 | Register base_reg; |
| 3643 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3644 | |
| 3645 | uint32_t lowest_set_bit = 14; |
| 3646 | // for i = 0 to 14 |
| 3647 | for (int i = 0; i < 14; ++i) |
| 3648 | { |
| 3649 | // if registers<i> == ’1’ then |
| 3650 | if (BitIsSet (registers, i)) |
| 3651 | { |
| 3652 | if (i < lowest_set_bit) |
| 3653 | lowest_set_bit = i; |
| 3654 | // if i == n && wback && i != LowestSetBit(registers) then |
| 3655 | if ((i == n) && wback && (i != lowest_set_bit)) |
| 3656 | // MemA[address,4] = bits(32) UNKNOWN; |
| 3657 | WriteBits32UnknownToMemory (address + offset); |
| 3658 | // else |
| 3659 | else |
| 3660 | { |
| 3661 | // MemA[address,4] = R[i]; |
| 3662 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success); |
| 3663 | if (!success) |
| 3664 | return false; |
| 3665 | |
| 3666 | Register data_reg; |
| 3667 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); |
| 3668 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
| 3669 | if (!WriteMemoryUnsigned (context, address + offset, data, addr_byte_size)) |
| 3670 | return false; |
| 3671 | } |
| 3672 | |
| 3673 | // address = address + 4; |
| 3674 | offset += addr_byte_size; |
| 3675 | } |
| 3676 | } |
| 3677 | |
| 3678 | // if registers<15> == ’1’ then |
| 3679 | // MemA[address,4] = PCStoreValue(); |
| 3680 | if (BitIsSet (registers, 15)) |
| 3681 | { |
| 3682 | Register pc_reg; |
| 3683 | pc_reg.SetRegister (eRegisterKindDWARF, dwarf_pc); |
| 3684 | context.SetRegisterPlusOffset (pc_reg, 8); |
| 3685 | const uint32_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 3686 | if (!success) |
| 3687 | return false; |
| 3688 | |
| 3689 | if (!WriteMemoryUnsigned (context, address + offset, pc + 8, addr_byte_size)) |
| 3690 | return false; |
| 3691 | } |
| 3692 | |
| 3693 | // if wback then R[n] = R[n] + 4*BitCount(registers); |
| 3694 | if (wback) |
| 3695 | { |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3696 | offset = addr_byte_size * BitCount (registers); |
| 3697 | context.type = EmulateInstruction::eContextAdjustBaseRegister; |
| 3698 | context.SetImmediateSigned (offset); |
| 3699 | addr_t data = address + offset; |
| 3700 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) |
| 3701 | return false; |
| 3702 | } |
| 3703 | } |
| 3704 | return true; |
| 3705 | } |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 3706 | |
| 3707 | // STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word |
| 3708 | // from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. |
| 3709 | bool |
| 3710 | EmulateInstructionARM::EmulateSTRThumb (ARMEncoding encoding) |
| 3711 | { |
| 3712 | #if 0 |
| 3713 | if ConditionPassed() then |
| 3714 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3715 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 3716 | address = if index then offset_addr else R[n]; |
| 3717 | if UnalignedSupport() || address<1:0> == ’00’ then |
| 3718 | MemU[address,4] = R[t]; |
| 3719 | else // Can only occur before ARMv7 |
| 3720 | MemU[address,4] = bits(32) UNKNOWN; |
| 3721 | if wback then R[n] = offset_addr; |
| 3722 | #endif |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 3723 | |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 3724 | bool success = false; |
| 3725 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3726 | if (!success) |
| 3727 | return false; |
| 3728 | |
| 3729 | if (ConditionPassed()) |
| 3730 | { |
| 3731 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3732 | |
| 3733 | uint32_t t; |
| 3734 | uint32_t n; |
| 3735 | uint32_t imm32; |
| 3736 | bool index; |
| 3737 | bool add; |
| 3738 | bool wback; |
| 3739 | // EncodingSpecificOperations (); NullCheckIfThumbEE(n); |
| 3740 | switch (encoding) |
| 3741 | { |
| 3742 | case eEncodingT1: |
| 3743 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:’00’, 32); |
| 3744 | t = Bits32 (opcode, 2, 0); |
| 3745 | n = Bits32 (opcode, 5, 3); |
| 3746 | imm32 = Bits32 (opcode, 10, 6) << 2; |
| 3747 | |
| 3748 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3749 | index = true; |
| 3750 | add = false; |
| 3751 | wback = false; |
| 3752 | break; |
| 3753 | |
| 3754 | case eEncodingT2: |
| 3755 | // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:’00’, 32); |
| 3756 | t = Bits32 (opcode, 10, 8); |
| 3757 | n = 13; |
| 3758 | imm32 = Bits32 (opcode, 7, 0) << 2; |
| 3759 | |
| 3760 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3761 | index = true; |
| 3762 | add = true; |
| 3763 | wback = false; |
| 3764 | break; |
| 3765 | |
| 3766 | case eEncodingT3: |
| 3767 | // if Rn == ’1111’ then UNDEFINED; |
| 3768 | if (Bits32 (opcode, 19, 16) == 15) |
| 3769 | return false; |
| 3770 | |
| 3771 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 3772 | t = Bits32 (opcode, 15, 12); |
| 3773 | n = Bits32 (opcode, 19, 16); |
| 3774 | imm32 = Bits32 (opcode, 11, 0); |
| 3775 | |
| 3776 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3777 | index = true; |
| 3778 | add = true; |
| 3779 | wback = false; |
| 3780 | |
| 3781 | // if t == 15 then UNPREDICTABLE; |
| 3782 | if (t == 15) |
| 3783 | return false; |
| 3784 | break; |
| 3785 | |
| 3786 | case eEncodingT4: |
| 3787 | // if P == ’1’ && U == ’1’ && W == ’0’ then SEE STRT; |
| 3788 | // if Rn == ’1101’ && P == ’1’ && U == ’0’ && W == ’1’ && imm8 == ’00000100’ then SEE PUSH; |
| 3789 | // if Rn == ’1111’ || (P == ’0’ && W == ’0’) then UNDEFINED; |
| 3790 | if ((Bits32 (opcode, 19, 16) == 15) |
| 3791 | || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))) |
| 3792 | return false; |
| 3793 | |
| 3794 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 3795 | t = Bits32 (opcode, 15, 12); |
| 3796 | n = Bits32 (opcode, 19, 16); |
| 3797 | imm32 = Bits32 (opcode, 7, 0); |
| 3798 | |
| 3799 | // index = (P == ’1’); add = (U == ’1’); wback = (W == ’1’); |
| 3800 | index = BitIsSet (opcode, 10); |
| 3801 | add = BitIsSet (opcode, 9); |
| 3802 | wback = BitIsSet (opcode, 8); |
| 3803 | |
| 3804 | // if t == 15 || (wback && n == t) then UNPREDICTABLE; |
| 3805 | if ((t == 15) || (wback && (n == t))) |
| 3806 | return false; |
| 3807 | break; |
| 3808 | |
| 3809 | default: |
| 3810 | return false; |
| 3811 | } |
| 3812 | |
| 3813 | addr_t offset_addr; |
| 3814 | addr_t address; |
| 3815 | |
| 3816 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 3817 | uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3818 | if (!success) |
| 3819 | return false; |
| 3820 | |
| 3821 | if (add) |
| 3822 | offset_addr = base_address + imm32; |
| 3823 | else |
| 3824 | offset_addr = base_address - imm32; |
| 3825 | |
| 3826 | // address = if index then offset_addr else R[n]; |
| 3827 | if (index) |
| 3828 | address = offset_addr; |
| 3829 | else |
| 3830 | address = base_address; |
| 3831 | |
| 3832 | EmulateInstruction::Context context; |
| 3833 | context.type = eContextRegisterStore; |
| 3834 | Register base_reg; |
| 3835 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 3836 | |
| 3837 | // if UnalignedSupport() || address<1:0> == ’00’ then |
| 3838 | if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0))) |
| 3839 | { |
| 3840 | // MemU[address,4] = R[t]; |
| 3841 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 3842 | if (!success) |
| 3843 | return false; |
| 3844 | |
| 3845 | Register data_reg; |
| 3846 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 3847 | int32_t offset = address - base_address; |
| 3848 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); |
| 3849 | if (!WriteMemoryUnsigned (context, address, data, addr_byte_size)) |
| 3850 | return false; |
| 3851 | } |
| 3852 | else |
| 3853 | { |
| 3854 | // MemU[address,4] = bits(32) UNKNOWN; |
| 3855 | WriteBits32UnknownToMemory (address); |
| 3856 | } |
| 3857 | |
| 3858 | // if wback then R[n] = offset_addr; |
| 3859 | if (wback) |
| 3860 | { |
| 3861 | context.type = eContextRegisterLoad; |
| 3862 | context.SetAddress (offset_addr); |
| 3863 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 3864 | return false; |
| 3865 | } |
| 3866 | } |
| 3867 | return true; |
| 3868 | } |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 3869 | |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 3870 | // STR (Store Register) calculates an address from a base register value and an offset register value, stores a |
| 3871 | // word from a register to memory. The offset register value can optionally be shifted. |
| 3872 | bool |
| 3873 | EmulateInstructionARM::EmulateSTRRegister (ARMEncoding encoding) |
| 3874 | { |
| 3875 | #if 0 |
| 3876 | if ConditionPassed() then |
| 3877 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 3878 | offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 3879 | offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 3880 | address = if index then offset_addr else R[n]; |
| 3881 | if t == 15 then // Only possible for encoding A1 |
| 3882 | data = PCStoreValue(); |
| 3883 | else |
| 3884 | data = R[t]; |
| 3885 | if UnalignedSupport() || address<1:0> == ’00’ || CurrentInstrSet() == InstrSet_ARM then |
| 3886 | MemU[address,4] = data; |
| 3887 | else // Can only occur before ARMv7 |
| 3888 | MemU[address,4] = bits(32) UNKNOWN; |
| 3889 | if wback then R[n] = offset_addr; |
| 3890 | #endif |
| 3891 | |
| 3892 | bool success = false; |
| 3893 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 3894 | if (!success) |
| 3895 | return false; |
| 3896 | |
| 3897 | if (ConditionPassed()) |
| 3898 | { |
| 3899 | const uint32_t addr_byte_size = GetAddressByteSize(); |
| 3900 | |
| 3901 | uint32_t t; |
| 3902 | uint32_t n; |
| 3903 | uint32_t m; |
| 3904 | ARM_ShifterType shift_t; |
| 3905 | uint32_t shift_n; |
| 3906 | bool index; |
| 3907 | bool add; |
| 3908 | bool wback; |
| 3909 | |
| 3910 | // EncodingSpecificOperations (); NullCheckIfThumbEE(n); |
| 3911 | switch (encoding) |
| 3912 | { |
| 3913 | case eEncodingT1: |
| 3914 | // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE"; |
| 3915 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 3916 | t = Bits32 (opcode, 2, 0); |
| 3917 | n = Bits32 (opcode, 5, 3); |
| 3918 | m = Bits32 (opcode, 8, 6); |
| 3919 | |
| 3920 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3921 | index = true; |
| 3922 | add = true; |
| 3923 | wback = false; |
| 3924 | |
| 3925 | // (shift_t, shift_n) = (SRType_LSL, 0); |
| 3926 | shift_t = SRType_LSL; |
| 3927 | shift_n = 0; |
| 3928 | break; |
| 3929 | |
| 3930 | case eEncodingT2: |
| 3931 | // if Rn == ’1111’ then UNDEFINED; |
| 3932 | if (Bits32 (opcode, 19, 16) == 15) |
| 3933 | return false; |
| 3934 | |
| 3935 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 3936 | t = Bits32 (opcode, 15, 12); |
| 3937 | n = Bits32 (opcode, 19, 16); |
| 3938 | m = Bits32 (opcode, 3, 0); |
| 3939 | |
| 3940 | // index = TRUE; add = TRUE; wback = FALSE; |
| 3941 | index = true; |
| 3942 | add = true; |
| 3943 | wback = false; |
| 3944 | |
| 3945 | // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); |
| 3946 | shift_t = SRType_LSL; |
| 3947 | shift_n = Bits32 (opcode, 5, 4); |
| 3948 | |
| 3949 | // if t == 15 || BadReg(m) then UNPREDICTABLE; |
| 3950 | if ((t == 15) || (BadReg (m))) |
| 3951 | return false; |
| 3952 | break; |
| 3953 | |
| 3954 | case eEncodingA1: |
| 3955 | { |
| 3956 | // if P == ’0’ && W == ’1’ then SEE STRT; |
| 3957 | // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); |
| 3958 | t = Bits32 (opcode, 15, 12); |
| 3959 | n = Bits32 (opcode, 19, 16); |
| 3960 | m = Bits32 (opcode, 3, 0); |
| 3961 | |
| 3962 | // index = (P == ’1’); add = (U == ’1’); wback = (P == ’0’) || (W == ’1’); |
| 3963 | index = BitIsSet (opcode, 24); |
| 3964 | add = BitIsSet (opcode, 23); |
| 3965 | wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); |
| 3966 | |
| 3967 | // (shift_t, shift_n) = DecodeImmShift(type, imm5); |
| 3968 | uint32_t typ = Bits32 (opcode, 6, 5); |
| 3969 | uint32_t imm5 = Bits32 (opcode, 11, 7); |
| 3970 | shift_n = DecodeImmShift(typ, imm5, shift_t); |
| 3971 | |
| 3972 | // if m == 15 then UNPREDICTABLE; |
| 3973 | if (m == 15) |
| 3974 | return false; |
| 3975 | |
| 3976 | // if wback && (n == 15 || n == t) then UNPREDICTABLE; |
| 3977 | if (wback && ((n == 15) || (n == t))) |
| 3978 | return false; |
| 3979 | |
| 3980 | break; |
| 3981 | } |
| 3982 | default: |
| 3983 | return false; |
| 3984 | } |
| 3985 | |
| 3986 | addr_t offset_addr; |
| 3987 | addr_t address; |
| 3988 | int32_t offset = 0; |
| 3989 | |
| 3990 | addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 3991 | if (!success) |
| 3992 | return false; |
| 3993 | |
| 3994 | uint32_t Rm_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); |
| 3995 | if (!success) |
| 3996 | return false; |
| 3997 | |
| 3998 | // offset = Shift(R[m], shift_t, shift_n, APSR.C); |
| 3999 | offset = Shift (Rm_data, shift_t, shift_n, Bit32(m_inst_cpsr, CPSR_C)); |
| 4000 | |
| 4001 | // offset_addr = if add then (R[n] + offset) else (R[n] - offset); |
| 4002 | if (add) |
| 4003 | offset_addr = base_address + offset; |
| 4004 | else |
| 4005 | offset_addr = base_address - offset; |
| 4006 | |
| 4007 | // address = if index then offset_addr else R[n]; |
| 4008 | if (index) |
| 4009 | address = offset_addr; |
| 4010 | else |
| 4011 | address = base_address; |
| 4012 | |
| 4013 | uint32_t data; |
| 4014 | // if t == 15 then // Only possible for encoding A1 |
| 4015 | if (t == 15) |
| 4016 | // data = PCStoreValue(); |
| 4017 | data = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); |
| 4018 | else |
| 4019 | // data = R[t]; |
| 4020 | data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 4021 | |
| 4022 | if (!success) |
| 4023 | return false; |
| 4024 | |
| 4025 | EmulateInstruction::Context context; |
| 4026 | context.type = eContextRegisterStore; |
| 4027 | |
| 4028 | // if UnalignedSupport() || address<1:0> == ’00’ || CurrentInstrSet() == InstrSet_ARM then |
| 4029 | if (UnalignedSupport () |
| 4030 | || (BitIsClear (address, 1) && BitIsClear (address, 0)) |
| 4031 | || CurrentInstrSet() == eModeARM) |
| 4032 | { |
| 4033 | // MemU[address,4] = data; |
| 4034 | |
| 4035 | Register base_reg; |
| 4036 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4037 | |
| 4038 | Register data_reg; |
| 4039 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4040 | |
| 4041 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address); |
| 4042 | if (!WriteMemoryUnsigned (context, address, data, addr_byte_size)) |
| 4043 | return false; |
| 4044 | |
| 4045 | } |
| 4046 | else |
| 4047 | // MemU[address,4] = bits(32) UNKNOWN; |
| 4048 | WriteBits32UnknownToMemory (address); |
| 4049 | |
| 4050 | // if wback then R[n] = offset_addr; |
| 4051 | if (wback) |
| 4052 | { |
| 4053 | context.type = eContextRegisterLoad; |
| 4054 | context.SetAddress (offset_addr); |
| 4055 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 4056 | return false; |
| 4057 | } |
| 4058 | |
| 4059 | } |
| 4060 | return true; |
| 4061 | } |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4062 | |
| 4063 | bool |
| 4064 | EmulateInstructionARM::EmulateSTRBThumb (ARMEncoding encoding) |
| 4065 | { |
| 4066 | #if 0 |
| 4067 | if ConditionPassed() then |
| 4068 | EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4069 | offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 4070 | address = if index then offset_addr else R[n]; |
| 4071 | MemU[address,1] = R[t]<7:0>; |
| 4072 | if wback then R[n] = offset_addr; |
| 4073 | #endif |
| 4074 | |
| 4075 | |
| 4076 | bool success = false; |
| 4077 | const uint32_t opcode = OpcodeAsUnsigned (&success); |
| 4078 | if (!success) |
| 4079 | return false; |
| 4080 | |
| 4081 | if (ConditionPassed ()) |
| 4082 | { |
| 4083 | uint32_t t; |
| 4084 | uint32_t n; |
| 4085 | uint32_t imm32; |
| 4086 | bool index; |
| 4087 | bool add; |
| 4088 | bool wback; |
| 4089 | // EncodingSpecificOperations(); NullCheckIfThumbEE(n); |
| 4090 | switch (encoding) |
| 4091 | { |
| 4092 | case eEncodingT1: |
| 4093 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32); |
| 4094 | t = Bits32 (opcode, 2, 0); |
| 4095 | n = Bits32 (opcode, 5, 3); |
| 4096 | imm32 = Bits32 (opcode, 10, 6); |
| 4097 | |
| 4098 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4099 | index = true; |
| 4100 | add = true; |
| 4101 | wback = false; |
| 4102 | break; |
| 4103 | |
| 4104 | case eEncodingT2: |
| 4105 | // if Rn == ’1111’ then UNDEFINED; |
| 4106 | if (Bits32 (opcode, 19, 16) == 15) |
| 4107 | return false; |
| 4108 | |
| 4109 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); |
| 4110 | t = Bits32 (opcode, 15, 12); |
| 4111 | n = Bits32 (opcode, 19, 16); |
| 4112 | imm32 = Bits32 (opcode, 11, 0); |
| 4113 | |
| 4114 | // index = TRUE; add = TRUE; wback = FALSE; |
| 4115 | index = true; |
| 4116 | add = true; |
| 4117 | wback = false; |
| 4118 | |
| 4119 | // if BadReg(t) then UNPREDICTABLE; |
| 4120 | if (BadReg (t)) |
| 4121 | return false; |
| 4122 | break; |
| 4123 | |
| 4124 | case eEncodingT3: |
| 4125 | // if P == ’1’ && U == ’1’ && W == ’0’ then SEE STRBT; |
| 4126 | // if Rn == ’1111’ || (P == ’0’ && W == ’0’) then UNDEFINED; |
| 4127 | if (Bits32 (opcode, 19, 16) == 15) |
| 4128 | return false; |
| 4129 | |
| 4130 | // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); |
| 4131 | t = Bits32 (opcode, 15, 12); |
| 4132 | n = Bits32 (opcode, 19, 16); |
| 4133 | imm32 = Bits32 (opcode, 7, 0); |
| 4134 | |
| 4135 | // index = (P == ’1’); add = (U == ’1’); wback = (W == ’1’); |
| 4136 | index = BitIsSet (opcode, 10); |
| 4137 | add = BitIsSet (opcode, 9); |
| 4138 | wback = BitIsSet (opcode, 8); |
| 4139 | |
| 4140 | // if BadReg(t) || (wback && n == t) then UNPREDICTABLE |
| 4141 | if ((BadReg (t)) || (wback && (n == t))) |
| 4142 | return false; |
| 4143 | break; |
| 4144 | |
| 4145 | default: |
| 4146 | return false; |
| 4147 | } |
| 4148 | |
| 4149 | addr_t offset_addr; |
| 4150 | addr_t address; |
| 4151 | addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); |
| 4152 | if (!success) |
| 4153 | return false; |
| 4154 | |
| 4155 | // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); |
| 4156 | if (add) |
| 4157 | offset_addr = base_address + imm32; |
| 4158 | else |
| 4159 | offset_addr = base_address - imm32; |
| 4160 | |
| 4161 | // address = if index then offset_addr else R[n]; |
| 4162 | if (index) |
| 4163 | address = offset_addr; |
| 4164 | else |
| 4165 | address = base_address; |
| 4166 | |
| 4167 | // MemU[address,1] = R[t]<7:0>; NOTE: "MemU' means UNALIGNED memory access |
| 4168 | Register base_reg; |
| 4169 | base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); |
| 4170 | |
| 4171 | Register data_reg; |
| 4172 | data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); |
| 4173 | |
| 4174 | EmulateInstruction::Context context; |
| 4175 | context.type = eContextRegisterStore; |
| 4176 | context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address); |
| 4177 | |
| 4178 | uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); |
| 4179 | if (!success) |
| 4180 | return false; |
| 4181 | |
| 4182 | data = Bits32 (data, 7, 0); |
| 4183 | |
| 4184 | if (!WriteMemoryUnsigned (context, address, data, 1)) |
| 4185 | return false; |
| 4186 | |
| 4187 | // if wback then R[n] = offset_addr; |
| 4188 | if (wback) |
| 4189 | { |
| 4190 | context.type = eContextRegisterLoad; |
| 4191 | context.SetAddress (offset_addr); |
| 4192 | if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) |
| 4193 | return false; |
| 4194 | } |
| 4195 | |
| 4196 | } |
| 4197 | |
| 4198 | return true; |
| 4199 | } |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4200 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4201 | EmulateInstructionARM::ARMOpcode* |
| 4202 | EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4203 | { |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4204 | static ARMOpcode |
| 4205 | g_arm_opcodes[] = |
| 4206 | { |
| 4207 | //---------------------------------------------------------------------- |
| 4208 | // Prologue instructions |
| 4209 | //---------------------------------------------------------------------- |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 4210 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4211 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4212 | { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
| 4213 | { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePush, "push <register>" }, |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 4214 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4215 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4216 | { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #<const>" }, |
| 4217 | { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubR7IPImmediate, "sub r7, ip, #<const>"}, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 4218 | // copy the stack pointer to ip |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4219 | { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMovRdSP, "mov ip, sp" }, |
| 4220 | { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add ip, sp, #<const>" }, |
| 4221 | { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubIPSPImmediate, "sub ip, sp, #<const>"}, |
Johnny Chen | 4c0e0bc | 2011-01-25 22:45:28 +0000 | [diff] [blame] | 4222 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4223 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4224 | { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub sp, sp, #<const>"}, |
Johnny Chen | ce1ca77 | 2011-01-25 01:13:00 +0000 | [diff] [blame] | 4225 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4226 | // push one register |
| 4227 | // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4228 | { 0x0fff0000, 0x052d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" }, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 4229 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4230 | // vector push consecutive extension register(s) |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 4231 | { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 4232 | { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 4233 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4234 | //---------------------------------------------------------------------- |
Johnny Chen | 587a0a4 | 2011-02-01 18:35:28 +0000 | [diff] [blame] | 4235 | // Epilogue instructions |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4236 | //---------------------------------------------------------------------- |
Johnny Chen | ef85e91 | 2011-01-31 23:07:40 +0000 | [diff] [blame] | 4237 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4238 | { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
| 4239 | { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulatePop, "pop <register>"}, |
Johnny Chen | 9b8d783 | 2011-02-02 01:13:56 +0000 | [diff] [blame] | 4240 | { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 4241 | { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
| 4242 | |
| 4243 | //---------------------------------------------------------------------- |
| 4244 | // Supervisor Call (previously Software Interrupt) |
| 4245 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 4246 | { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, |
| 4247 | |
| 4248 | //---------------------------------------------------------------------- |
| 4249 | // Branch instructions |
| 4250 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4251 | { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSVC, "b #imm24"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 4252 | // To resolve ambiguity, "blx <label>" should come before "bl <label>". |
| 4253 | { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 4254 | { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 4255 | { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 4256 | // for example, "bx lr" |
| 4257 | { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 4258 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4259 | //---------------------------------------------------------------------- |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 4260 | // Data-processing instructions |
| 4261 | //---------------------------------------------------------------------- |
| 4262 | // move bitwise not |
| 4263 | { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 4264 | // asr (immediate) |
| 4265 | { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 4266 | // asr (register) |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 4267 | { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 4268 | // lsl (immediate) |
| 4269 | { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"}, |
| 4270 | // lsl (register) |
| 4271 | { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"}, |
| 4272 | // lsr (immediate) |
| 4273 | { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"}, |
| 4274 | // lsr (register) |
| 4275 | { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 4276 | // rrx is a special case encoding of ror (immediate) |
| 4277 | { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"}, |
| 4278 | // ror (immediate) |
| 4279 | { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"}, |
| 4280 | // ror (register) |
| 4281 | { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 4282 | |
| 4283 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4284 | // Load instructions |
| 4285 | //---------------------------------------------------------------------- |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 4286 | { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 713c266 | 2011-02-11 17:59:55 +0000 | [diff] [blame] | 4287 | { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | 85aab33 | 2011-02-08 23:56:10 +0000 | [diff] [blame] | 4288 | { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 4289 | { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" }, |
| 4290 | |
| 4291 | //---------------------------------------------------------------------- |
| 4292 | // Store instructions |
| 4293 | //---------------------------------------------------------------------- |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4294 | { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4295 | { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" }, |
Caroline Tice | af55656 | 2011-02-15 18:42:15 +0000 | [diff] [blame] | 4296 | { 0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" }, |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4297 | { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>" }, |
| 4298 | { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}" } |
Caroline Tice | 1511f50 | 2011-02-15 00:19:42 +0000 | [diff] [blame] | 4299 | |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4300 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4301 | }; |
| 4302 | static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode); |
| 4303 | |
| 4304 | for (size_t i=0; i<k_num_arm_opcodes; ++i) |
| 4305 | { |
| 4306 | if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) |
| 4307 | return &g_arm_opcodes[i]; |
| 4308 | } |
| 4309 | return NULL; |
| 4310 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4311 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4312 | |
| 4313 | EmulateInstructionARM::ARMOpcode* |
| 4314 | EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 4315 | { |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 4316 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4317 | static ARMOpcode |
| 4318 | g_thumb_opcodes[] = |
| 4319 | { |
| 4320 | //---------------------------------------------------------------------- |
| 4321 | // Prologue instructions |
| 4322 | //---------------------------------------------------------------------- |
Johnny Chen | bcec3af | 2011-01-27 01:26:19 +0000 | [diff] [blame] | 4323 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4324 | // push register(s) |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4325 | { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePush, "push <registers>" }, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 4326 | { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <registers>" }, |
| 4327 | { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePush, "push.w <register>" }, |
Johnny Chen | 788e055 | 2011-01-27 22:52:23 +0000 | [diff] [blame] | 4328 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4329 | // set r7 to point to a stack offset |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4330 | { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdSPImmediate, "add r7, sp, #imm" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 4331 | // copy the stack pointer to r7 |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4332 | { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdSP, "mov r7, sp" }, |
Johnny Chen | e7cf420 | 2011-02-10 18:13:23 +0000 | [diff] [blame] | 4333 | // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity) |
| 4334 | { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovLowHigh, "mov r0-r7, r8-r15" }, |
Johnny Chen | 60c0d62 | 2011-01-25 23:49:39 +0000 | [diff] [blame] | 4335 | |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 4336 | // PC-relative load into register (see also EmulateAddSPRm) |
| 4337 | { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"}, |
Johnny Chen | 799dfd0 | 2011-01-26 23:14:33 +0000 | [diff] [blame] | 4338 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4339 | // adjust the stack pointer |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4340 | { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPRm, "add sp, <Rm>"}, |
| 4341 | { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSubSPImmdiate, "add sp, sp, #imm"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 4342 | { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "sub.w sp, sp, #<const>"}, |
| 4343 | { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSubSPImmdiate, "subw sp, sp, #imm12"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 4344 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4345 | // vector push consecutive extension register(s) |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 4346 | { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"}, |
| 4347 | { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, |
Johnny Chen | fdd179e | 2011-01-31 20:09:28 +0000 | [diff] [blame] | 4348 | |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4349 | //---------------------------------------------------------------------- |
| 4350 | // Epilogue instructions |
| 4351 | //---------------------------------------------------------------------- |
Johnny Chen | 347320d | 2011-01-24 23:40:59 +0000 | [diff] [blame] | 4352 | |
Johnny Chen | c28a76d | 2011-02-01 18:51:48 +0000 | [diff] [blame] | 4353 | { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateAddSPImmediate, "add sp, #imm"}, |
| 4354 | { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulatePop, "pop <registers>"}, |
Johnny Chen | d6c13f0 | 2011-02-08 20:36:34 +0000 | [diff] [blame] | 4355 | { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <registers>" }, |
| 4356 | { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulatePop, "pop.w <register>" }, |
| 4357 | { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"}, |
| 4358 | { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, |
Johnny Chen | b77be41 | 2011-02-04 00:40:18 +0000 | [diff] [blame] | 4359 | |
| 4360 | //---------------------------------------------------------------------- |
| 4361 | // Supervisor Call (previously Software Interrupt) |
| 4362 | //---------------------------------------------------------------------- |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 4363 | { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, |
| 4364 | |
| 4365 | //---------------------------------------------------------------------- |
| 4366 | // If Then makes up to four following instructions conditional. |
| 4367 | //---------------------------------------------------------------------- |
Johnny Chen | 3b620b3 | 2011-02-07 20:11:47 +0000 | [diff] [blame] | 4368 | { 0xffffff00, 0x0000bf00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, |
| 4369 | |
| 4370 | //---------------------------------------------------------------------- |
| 4371 | // Branch instructions |
| 4372 | //---------------------------------------------------------------------- |
| 4373 | // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". |
| 4374 | { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, |
| 4375 | { 0xffff8000, 0x0000e000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateB, "b #imm11 (outside or last in IT)"}, |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4376 | { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4377 | { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateB, "b.w #imm8 (outside or last in IT)"}, |
Johnny Chen | 383d629 | 2011-02-11 21:23:32 +0000 | [diff] [blame] | 4378 | // J1 == J2 == 1 |
| 4379 | { 0xf800f800, 0xf000f800, ARMV4T_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"}, |
| 4380 | // J1 == J2 == 1 |
| 4381 | { 0xf800e800, 0xf000e800, ARMV5_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"}, |
| 4382 | { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"}, |
Johnny Chen | ab3b351 | 2011-02-12 00:10:51 +0000 | [diff] [blame] | 4383 | // for example, "bx lr" |
| 4384 | { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"}, |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 4385 | // compare and branch |
| 4386 | { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"}, |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4387 | |
| 4388 | //---------------------------------------------------------------------- |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 4389 | // Data-processing instructions |
| 4390 | //---------------------------------------------------------------------- |
| 4391 | // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two. |
| 4392 | { 0xffffff00, 0x00004400, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateAddRdnRm, "add <Rdn>, <Rm>"}, |
Johnny Chen | 338bf54 | 2011-02-10 19:29:03 +0000 | [diff] [blame] | 4393 | // move from high register to high register |
| 4394 | { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "mov<c> <Rd>, <Rm>"}, |
| 4395 | // move from low register to low register |
| 4396 | { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateMovRdRm, "movs <Rd>, <Rm>"}, |
Johnny Chen | 357c30f | 2011-02-14 22:04:25 +0000 | [diff] [blame] | 4397 | // move immediate |
| 4398 | { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMovRdImm, "movs|mov<c> <Rd>, #imm8"}, |
| 4399 | { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMovRdImm, "mov{s}<c>.w <Rd>, #<const>"}, |
Johnny Chen | 28070c3 | 2011-02-12 01:27:26 +0000 | [diff] [blame] | 4400 | // move bitwise not |
| 4401 | { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMvnRdImm, "mvn{s} <Rd>, #<const>"}, |
Johnny Chen | d4dc444 | 2011-02-11 02:02:56 +0000 | [diff] [blame] | 4402 | // compare a register with immediate |
| 4403 | { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnImm, "cmp<c> <Rn>, #imm8"}, |
Johnny Chen | e4a4d30 | 2011-02-11 21:53:58 +0000 | [diff] [blame] | 4404 | // compare Rn with Rm (Rn and Rm both from r0-r7) |
| 4405 | { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
| 4406 | // compare Rn with Rm (Rn and Rm not both from r0-r7) |
| 4407 | { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCmpRnRm, "cmp<c> <Rn>, <Rm>"}, |
Johnny Chen | 82f16aa | 2011-02-15 20:10:55 +0000 | [diff] [blame] | 4408 | // asr (immediate) |
| 4409 | { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"}, |
Johnny Chen | 4d896db | 2011-02-15 20:14:02 +0000 | [diff] [blame] | 4410 | { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"}, |
Johnny Chen | e7f8953 | 2011-02-15 23:22:46 +0000 | [diff] [blame] | 4411 | // asr (register) |
| 4412 | { 0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"}, |
| 4413 | { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 4414 | // lsl (immediate) |
| 4415 | { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"}, |
| 4416 | { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 4417 | // lsl (register) |
| 4418 | { 0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"}, |
| 4419 | { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
| 4420 | // lsr (immediate) |
| 4421 | { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"}, |
| 4422 | { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 4423 | // lsr (register) |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 4424 | { 0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"}, |
Johnny Chen | 2ee35bc | 2011-02-16 19:27:43 +0000 | [diff] [blame] | 4425 | { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | eeab485 | 2011-02-16 22:14:44 +0000 | [diff] [blame] | 4426 | // rrx is a special case encoding of ror (immediate) |
| 4427 | { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"}, |
| 4428 | // ror (immediate) |
| 4429 | { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"}, |
| 4430 | // ror (register) |
| 4431 | { 0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"}, |
| 4432 | { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"}, |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 4433 | |
| 4434 | //---------------------------------------------------------------------- |
Caroline Tice | b9f76c3 | 2011-02-08 22:24:38 +0000 | [diff] [blame] | 4435 | // Load instructions |
| 4436 | //---------------------------------------------------------------------- |
| 4437 | { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" }, |
Caroline Tice | 0b29e24 | 2011-02-08 23:16:02 +0000 | [diff] [blame] | 4438 | { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" }, |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 4439 | { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" }, |
Johnny Chen | c9de910 | 2011-02-11 19:12:30 +0000 | [diff] [blame] | 4440 | { 0xfffff800, 0x00006800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"}, |
| 4441 | // Thumb2 PC-relative load into register |
Caroline Tice | fa17220 | 2011-02-11 22:49:54 +0000 | [diff] [blame] | 4442 | { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"}, |
| 4443 | |
| 4444 | //---------------------------------------------------------------------- |
| 4445 | // Store instructions |
| 4446 | //---------------------------------------------------------------------- |
| 4447 | { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" }, |
Caroline Tice | b6f8d7e | 2011-02-15 18:10:01 +0000 | [diff] [blame] | 4448 | { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" }, |
Caroline Tice | 7fac857 | 2011-02-15 22:53:54 +0000 | [diff] [blame] | 4449 | { 0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" }, |
| 4450 | { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt> [<Rn>{,#<imm>}]" }, |
| 4451 | { 0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt> [SP,#<imm>]" }, |
| 4452 | { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt [<Rn>,#<imm12>]" }, |
Caroline Tice | 3fd63e9 | 2011-02-16 00:33:43 +0000 | [diff] [blame] | 4453 | { 0xfff00800, 0xf8400800, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt> [<Rn>,#+/-<imm8>]" }, |
| 4454 | { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> {<Rn> <Rm>]" }, |
Caroline Tice | 73a29de | 2011-02-16 20:22:22 +0000 | [diff] [blame] | 4455 | { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt> [<Rn> <Rm> {lsl #imm2>}]" }, |
| 4456 | { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> [<Rn> #<imm5>]" }, |
| 4457 | { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt> [<Rn> #<imm12>]" }, |
| 4458 | { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> [<Rn>, #+/-<imm8>]{!}" } |
Greg Clayton | 2b8e8b0 | 2011-02-01 00:49:32 +0000 | [diff] [blame] | 4459 | }; |
| 4460 | |
| 4461 | const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); |
| 4462 | for (size_t i=0; i<k_num_thumb_opcodes; ++i) |
| 4463 | { |
| 4464 | if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) |
| 4465 | return &g_thumb_opcodes[i]; |
| 4466 | } |
| 4467 | return NULL; |
| 4468 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4469 | |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 4470 | bool |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 4471 | EmulateInstructionARM::SetArchitecture (const ArchSpec &arch) |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 4472 | { |
| 4473 | m_arm_isa = 0; |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 4474 | const char *arch_cstr = arch.AsCString (); |
| 4475 | if (arch_cstr) |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 4476 | { |
Greg Clayton | 395fc33 | 2011-02-15 21:59:32 +0000 | [diff] [blame] | 4477 | if (0 == ::strcasecmp(arch_cstr, "armv4t")) m_arm_isa = ARMv4T; |
| 4478 | else if (0 == ::strcasecmp(arch_cstr, "armv4")) m_arm_isa = ARMv4; |
| 4479 | else if (0 == ::strcasecmp(arch_cstr, "armv5tej")) m_arm_isa = ARMv5TEJ; |
| 4480 | else if (0 == ::strcasecmp(arch_cstr, "armv5te")) m_arm_isa = ARMv5TE; |
| 4481 | else if (0 == ::strcasecmp(arch_cstr, "armv5t")) m_arm_isa = ARMv5T; |
| 4482 | else if (0 == ::strcasecmp(arch_cstr, "armv6k")) m_arm_isa = ARMv6K; |
| 4483 | else if (0 == ::strcasecmp(arch_cstr, "armv6")) m_arm_isa = ARMv6; |
| 4484 | else if (0 == ::strcasecmp(arch_cstr, "armv6t2")) m_arm_isa = ARMv6T2; |
| 4485 | else if (0 == ::strcasecmp(arch_cstr, "armv7")) m_arm_isa = ARMv7; |
| 4486 | else if (0 == ::strcasecmp(arch_cstr, "armv8")) m_arm_isa = ARMv8; |
Greg Clayton | 31e2a38 | 2011-01-30 20:03:56 +0000 | [diff] [blame] | 4487 | } |
| 4488 | return m_arm_isa != 0; |
| 4489 | } |
| 4490 | |
| 4491 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4492 | bool |
| 4493 | EmulateInstructionARM::ReadInstruction () |
| 4494 | { |
| 4495 | bool success = false; |
| 4496 | m_inst_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success); |
| 4497 | if (success) |
| 4498 | { |
| 4499 | addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); |
| 4500 | if (success) |
| 4501 | { |
Caroline Tice | 9bfe7f2 | 2011-02-14 23:03:21 +0000 | [diff] [blame] | 4502 | Context read_inst_context; |
| 4503 | read_inst_context.type = eContextReadOpcode; |
| 4504 | read_inst_context.SetNoArgs (); |
| 4505 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4506 | if (m_inst_cpsr & MASK_CPSR_T) |
| 4507 | { |
| 4508 | m_inst_mode = eModeThumb; |
| 4509 | uint32_t thumb_opcode = ReadMemoryUnsigned(read_inst_context, pc, 2, 0, &success); |
| 4510 | |
| 4511 | if (success) |
| 4512 | { |
| 4513 | if ((m_inst.opcode.inst16 & 0xe000) != 0xe000 || ((m_inst.opcode.inst16 & 0x1800u) == 0)) |
| 4514 | { |
| 4515 | m_inst.opcode_type = eOpcode16; |
| 4516 | m_inst.opcode.inst16 = thumb_opcode; |
| 4517 | } |
| 4518 | else |
| 4519 | { |
| 4520 | m_inst.opcode_type = eOpcode32; |
| 4521 | m_inst.opcode.inst32 = (thumb_opcode << 16) | ReadMemoryUnsigned(read_inst_context, pc + 2, 2, 0, &success); |
| 4522 | } |
| 4523 | } |
| 4524 | } |
| 4525 | else |
| 4526 | { |
| 4527 | m_inst_mode = eModeARM; |
| 4528 | m_inst.opcode_type = eOpcode32; |
| 4529 | m_inst.opcode.inst32 = ReadMemoryUnsigned(read_inst_context, pc, 4, 0, &success); |
| 4530 | } |
| 4531 | } |
| 4532 | } |
| 4533 | if (!success) |
| 4534 | { |
| 4535 | m_inst_mode = eModeInvalid; |
| 4536 | m_inst_pc = LLDB_INVALID_ADDRESS; |
| 4537 | } |
| 4538 | return success; |
| 4539 | } |
| 4540 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4541 | uint32_t |
| 4542 | EmulateInstructionARM::ArchVersion () |
| 4543 | { |
| 4544 | return m_arm_isa; |
| 4545 | } |
| 4546 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4547 | bool |
| 4548 | EmulateInstructionARM::ConditionPassed () |
| 4549 | { |
| 4550 | if (m_inst_cpsr == 0) |
| 4551 | return false; |
| 4552 | |
| 4553 | const uint32_t cond = CurrentCond (); |
| 4554 | |
| 4555 | if (cond == UINT32_MAX) |
| 4556 | return false; |
| 4557 | |
| 4558 | bool result = false; |
| 4559 | switch (UnsignedBits(cond, 3, 1)) |
| 4560 | { |
| 4561 | case 0: result = (m_inst_cpsr & MASK_CPSR_Z) != 0; break; |
| 4562 | case 1: result = (m_inst_cpsr & MASK_CPSR_C) != 0; break; |
| 4563 | case 2: result = (m_inst_cpsr & MASK_CPSR_N) != 0; break; |
| 4564 | case 3: result = (m_inst_cpsr & MASK_CPSR_V) != 0; break; |
| 4565 | case 4: result = ((m_inst_cpsr & MASK_CPSR_C) != 0) && ((m_inst_cpsr & MASK_CPSR_Z) == 0); break; |
| 4566 | case 5: |
| 4567 | { |
| 4568 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 4569 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 4570 | result = n == v; |
| 4571 | } |
| 4572 | break; |
| 4573 | case 6: |
| 4574 | { |
| 4575 | bool n = (m_inst_cpsr & MASK_CPSR_N); |
| 4576 | bool v = (m_inst_cpsr & MASK_CPSR_V); |
| 4577 | result = n == v && ((m_inst_cpsr & MASK_CPSR_Z) == 0); |
| 4578 | } |
| 4579 | break; |
| 4580 | case 7: |
| 4581 | result = true; |
| 4582 | break; |
| 4583 | } |
| 4584 | |
| 4585 | if (cond & 1) |
| 4586 | result = !result; |
| 4587 | return result; |
| 4588 | } |
| 4589 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4590 | uint32_t |
| 4591 | EmulateInstructionARM::CurrentCond () |
| 4592 | { |
| 4593 | switch (m_inst_mode) |
| 4594 | { |
| 4595 | default: |
| 4596 | case eModeInvalid: |
| 4597 | break; |
| 4598 | |
| 4599 | case eModeARM: |
| 4600 | return UnsignedBits(m_inst.opcode.inst32, 31, 28); |
| 4601 | |
| 4602 | case eModeThumb: |
| 4603 | // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit |
| 4604 | // 'cond' field of the encoding. |
| 4605 | if (m_inst.opcode_type == eOpcode16 && |
| 4606 | Bits32(m_inst.opcode.inst16, 15, 12) == 0x0d && |
| 4607 | Bits32(m_inst.opcode.inst16, 11, 7) != 0x0f) |
| 4608 | { |
| 4609 | return Bits32(m_inst.opcode.inst16, 11, 7); |
| 4610 | } |
| 4611 | else if (m_inst.opcode_type == eOpcode32 && |
| 4612 | Bits32(m_inst.opcode.inst32, 31, 27) == 0x1e && |
| 4613 | Bits32(m_inst.opcode.inst32, 15, 14) == 0x02 && |
| 4614 | Bits32(m_inst.opcode.inst32, 12, 12) == 0x00 && |
| 4615 | Bits32(m_inst.opcode.inst32, 25, 22) <= 0x0d) |
| 4616 | { |
| 4617 | return Bits32(m_inst.opcode.inst32, 25, 22); |
| 4618 | } |
| 4619 | |
| 4620 | return m_it_session.GetCond(); |
| 4621 | } |
| 4622 | return UINT32_MAX; // Return invalid value |
| 4623 | } |
| 4624 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4625 | bool |
Johnny Chen | 098ae2d | 2011-02-12 00:50:05 +0000 | [diff] [blame] | 4626 | EmulateInstructionARM::InITBlock() |
| 4627 | { |
| 4628 | return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock(); |
| 4629 | } |
| 4630 | |
| 4631 | bool |
| 4632 | EmulateInstructionARM::LastInITBlock() |
| 4633 | { |
| 4634 | return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock(); |
| 4635 | } |
| 4636 | |
| 4637 | bool |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4638 | EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr) |
| 4639 | { |
| 4640 | addr_t target; |
| 4641 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4642 | // Check the current instruction set. |
| 4643 | if (CurrentInstrSet() == eModeARM) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4644 | target = addr & 0xfffffffc; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4645 | else |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4646 | target = addr & 0xfffffffe; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4647 | |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4648 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 4649 | return false; |
| 4650 | |
| 4651 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4652 | } |
| 4653 | |
| 4654 | // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. |
| 4655 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4656 | EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr) |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4657 | { |
| 4658 | addr_t target; |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 4659 | // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, |
| 4660 | // we want to record it and issue a WriteRegister callback so the clients |
| 4661 | // can track the mode changes accordingly. |
| 4662 | bool cpsr_changed = false; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4663 | |
| 4664 | if (BitIsSet(addr, 0)) |
| 4665 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 4666 | if (CurrentInstrSet() != eModeThumb) |
| 4667 | { |
| 4668 | SelectInstrSet(eModeThumb); |
| 4669 | cpsr_changed = true; |
| 4670 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4671 | target = addr & 0xfffffffe; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4672 | context.SetMode (eModeThumb); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4673 | } |
| 4674 | else if (BitIsClear(addr, 1)) |
| 4675 | { |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 4676 | if (CurrentInstrSet() != eModeARM) |
| 4677 | { |
| 4678 | SelectInstrSet(eModeARM); |
| 4679 | cpsr_changed = true; |
| 4680 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4681 | target = addr & 0xfffffffc; |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4682 | context.SetMode (eModeARM); |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4683 | } |
| 4684 | else |
| 4685 | return false; // address<1:0> == '10' => UNPREDICTABLE |
| 4686 | |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 4687 | if (cpsr_changed) |
| 4688 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 4689 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) |
Johnny Chen | 0f309db | 2011-02-09 19:11:32 +0000 | [diff] [blame] | 4690 | return false; |
| 4691 | } |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4692 | if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target)) |
Johnny Chen | 53ebab7 | 2011-02-08 23:21:57 +0000 | [diff] [blame] | 4693 | return false; |
| 4694 | |
| 4695 | return true; |
Johnny Chen | 9ee056b | 2011-02-08 00:06:35 +0000 | [diff] [blame] | 4696 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4697 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4698 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions. |
| 4699 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4700 | EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr) |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4701 | { |
| 4702 | if (ArchVersion() >= ARMv5T) |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4703 | return BXWritePC(context, addr); |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4704 | else |
| 4705 | return BranchWritePC((const Context)context, addr); |
| 4706 | } |
| 4707 | |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 4708 | // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set. |
| 4709 | bool |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4710 | EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr) |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 4711 | { |
| 4712 | if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) |
Johnny Chen | 668b451 | 2011-02-15 21:08:58 +0000 | [diff] [blame] | 4713 | return BXWritePC(context, addr); |
Johnny Chen | 26863dc | 2011-02-09 23:43:29 +0000 | [diff] [blame] | 4714 | else |
| 4715 | return BranchWritePC((const Context)context, addr); |
| 4716 | } |
| 4717 | |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4718 | EmulateInstructionARM::Mode |
| 4719 | EmulateInstructionARM::CurrentInstrSet () |
| 4720 | { |
| 4721 | return m_inst_mode; |
| 4722 | } |
| 4723 | |
| 4724 | // Set the 'T' bit of our CPSR. The m_inst_mode gets updated when the next |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 4725 | // ReadInstruction() is performed. This function has a side effect of updating |
| 4726 | // the m_new_inst_cpsr member variable if necessary. |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4727 | bool |
| 4728 | EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb) |
| 4729 | { |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 4730 | m_new_inst_cpsr = m_inst_cpsr; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4731 | switch (arm_or_thumb) |
| 4732 | { |
| 4733 | default: |
| 4734 | return false; |
| 4735 | eModeARM: |
| 4736 | // Clear the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 4737 | m_new_inst_cpsr &= ~MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4738 | break; |
| 4739 | eModeThumb: |
| 4740 | // Set the T bit. |
Johnny Chen | 558133b | 2011-02-09 23:59:17 +0000 | [diff] [blame] | 4741 | m_new_inst_cpsr |= MASK_CPSR_T; |
Johnny Chen | ee9b1f7 | 2011-02-09 01:00:31 +0000 | [diff] [blame] | 4742 | break; |
| 4743 | } |
| 4744 | return true; |
| 4745 | } |
| 4746 | |
Johnny Chen | ef21b59 | 2011-02-10 01:52:38 +0000 | [diff] [blame] | 4747 | // This function returns TRUE if the processor currently provides support for |
| 4748 | // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7, |
| 4749 | // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6. |
| 4750 | bool |
| 4751 | EmulateInstructionARM::UnalignedSupport() |
| 4752 | { |
| 4753 | return (ArchVersion() >= ARMv7); |
| 4754 | } |
| 4755 | |
Johnny Chen | bf6ad17 | 2011-02-11 01:29:53 +0000 | [diff] [blame] | 4756 | // The main addition and subtraction instructions can produce status information |
| 4757 | // about both unsigned carry and signed overflow conditions. This status |
| 4758 | // information can be used to synthesize multi-word additions and subtractions. |
| 4759 | EmulateInstructionARM::AddWithCarryResult |
| 4760 | EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in) |
| 4761 | { |
| 4762 | uint32_t result; |
| 4763 | uint8_t carry_out; |
| 4764 | uint8_t overflow; |
| 4765 | |
| 4766 | uint64_t unsigned_sum = x + y + carry_in; |
| 4767 | int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in; |
| 4768 | |
| 4769 | result = UnsignedBits(unsigned_sum, 31, 0); |
| 4770 | carry_out = (result == unsigned_sum ? 0 : 1); |
| 4771 | overflow = ((int32_t)result == signed_sum ? 0 : 1); |
| 4772 | |
| 4773 | AddWithCarryResult res = { result, carry_out, overflow }; |
| 4774 | return res; |
| 4775 | } |
| 4776 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4777 | bool |
| 4778 | EmulateInstructionARM::EvaluateInstruction () |
| 4779 | { |
Johnny Chen | c315f86 | 2011-02-05 00:46:10 +0000 | [diff] [blame] | 4780 | // Advance the ITSTATE bits to their values for the next instruction. |
| 4781 | if (m_inst_mode == eModeThumb && m_it_session.InITBlock()) |
| 4782 | m_it_session.ITAdvance(); |
| 4783 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 4784 | return false; |
| 4785 | } |