commit 01b36e6436a1d1d1dacdea777ae1dc7472f2fdd9
author Dale Johannesen <dalej@apple.com> Fri Feb 13 02:30:42 2009 +0000
committer Dale Johannesen <dalej@apple.com> Fri Feb 13 02:30:42 2009 +0000
tree 4101d8efd113d9cc969033f7aae3531d4c1702dd
parent bd9ef18f74a361e0ed630d373677c6fc0ce3cad9

Remove non-DebugLoc versions of BuildMI from Alpha and Cell.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index d2ec7b1..439daae 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -627,6 +627,8 @@
 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                            MachineBasicBlock *FBB,
                            const SmallVectorImpl<MachineOperand> &Cond) const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -636,14 +638,14 @@
   if (FBB == 0) {
     if (Cond.empty()) {
       // Unconditional branch
-      MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
+      MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
       MIB.addMBB(TBB);
 
       DEBUG(cerr << "Inserted one-way uncond branch: ");
       DEBUG((*MIB).dump());
     } else {
       // Conditional branch
-      MachineInstrBuilder  MIB = BuildMI(&MBB, get(Cond[0].getImm()));
+      MachineInstrBuilder  MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
 
       DEBUG(cerr << "Inserted one-way cond branch:   ");
@@ -651,8 +653,8 @@
     }
     return 1;
   } else {
-    MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
-    MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
+    MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
+    MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
 
     // Two-way Conditional Branch.
     MIB.addReg(Cond[1].getReg()).addMBB(TBB);