Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 47c5339..4418f40 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -281,8 +281,8 @@
if (Kind == SDep::Anti)
DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
else {
- unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
- DefSU->getInstr(), Reg);
+ unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
+ DefSU->getInstr());
DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
}
}