PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index b631124..891ae55 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -423,17 +423,21 @@
return false;
}
-void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
+bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const {
unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
MI->addImmOperand(Cond[0].getImmedValue());
- return;
+ return true;
}
MachineOperand *PMO = MI->findFirstPredOperand();
- PMO->setImm(Cond[0].getImmedValue());
+ if (PMO) {
+ PMO->setImm(Cond[0].getImmedValue());
+ return true;
+ }
+ return false;
}