X86 integer register classes naming changes. Make them consistent with FP, vector classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index 7adc1c5..7d40c88 100755
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -360,14 +360,14 @@
// See if a truncate instruction can be turned into a nop.
switch (MI->getOpcode()) {
default: break;
- case X86::TRUNC_R32_R16:
- case X86::TRUNC_R32_R8:
- case X86::TRUNC_R16_R8: {
+ case X86::TRUNC_GR32_GR16:
+ case X86::TRUNC_GR32_GR8:
+ case X86::TRUNC_GR16_GR8: {
const MachineOperand &MO0 = MI->getOperand(0);
const MachineOperand &MO1 = MI->getOperand(1);
unsigned Reg0 = MO0.getReg();
unsigned Reg1 = MO1.getReg();
- if (MI->getOpcode() == X86::TRUNC_R32_R16)
+ if (MI->getOpcode() == X86::TRUNC_GR32_GR16)
Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
else
Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);