llvm-mc/AsmParser: Implement user defined super classes.
- We can now discriminate SUB32ri8 from SUB32ri, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index ea5528a..5a42683 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -137,6 +137,19 @@
bool isImm() const { return Kind == Immediate; }
+ bool isImmSExt8() const {
+ // Accept immediates which fit in 8 bits when sign extended, and
+ // non-absolute immediates.
+ if (!isImm())
+ return false;
+
+ if (!getImm().isAbsolute())
+ return true;
+
+ int64_t Value = getImm().getConstant();
+ return Value == (int64_t) (int8_t) Value;
+ }
+
bool isMem() const { return Kind == Memory; }
bool isReg() const { return Kind == Register; }
@@ -151,6 +164,12 @@
Inst.addOperand(MCOperand::CreateMCValue(getImm()));
}
+ void addImmSExt8Operands(MCInst &Inst, unsigned N) {
+ // FIXME: Support user customization of the render method.
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::CreateMCValue(getImm()));
+ }
+
void addMemOperands(MCInst &Inst, unsigned N) {
assert((N == 4 || N == 5) && "Invalid number of operands!");
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index c21cad9..80f03e8 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -212,9 +212,15 @@
// A couple of more descriptive operand definitions.
// 16-bits but only 8 bits are significant.
-def i16i8imm : Operand<i16>;
+def i16i8imm : Operand<i16> {
+ let ParserMatchClass = "ImmSExt8";
+ let ParserMatchSuperClass = "Imm";
+}
// 32-bits but only 8 bits are significant.
-def i32i8imm : Operand<i32>;
+def i32i8imm : Operand<i32> {
+ let ParserMatchClass = "ImmSExt8";
+ let ParserMatchSuperClass = "Imm";
+}
// Branch targets have OtherVT type and print as pc-relative values.
def brtarget : Operand<OtherVT> {