Turn sdivs into udivs when we can prove the sign bits are clear. This
implements CodeGen/PowerPC/div-2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23659 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 28215ad..12cfe00 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1556,6 +1556,17 @@
return N1;
}
break;
+ case ISD::SDIV: {
+ if (CombinerEnabled) break;
+
+ // If we know the sign bits of both operands are zero, strength reduce to a
+ // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
+ uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
+ if (MaskedValueIsZero(N2, SignBit, TLI) &&
+ MaskedValueIsZero(N1, SignBit, TLI))
+ return getNode(ISD::UDIV, VT, N1, N2);
+ break;
+ }
case ISD::AND:
case ISD::OR: