Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 975d46f..4aad817 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -703,7 +703,6 @@
.Case("fwait", "wait")
.Case("movzx", "movzb") // FIXME: Not correct.
.Case("fildq", "fildll")
- .Case("ud2a", "ud2")
.Default(Name);
// FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
@@ -1176,10 +1175,9 @@
// First, handle aliases that expand to multiple instructions.
// FIXME: This should be replaced with a real .td file alias mechanism.
- if (Op->getToken() == "fstsw" || Op->getToken() == "fstsww" ||
- Op->getToken() == "fstcw" || Op->getToken() == "fstcww" ||
+ if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
Op->getToken() == "finit" || Op->getToken() == "fsave" ||
- Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
+ Op->getToken() == "fstenv") {
MCInst Inst;
Inst.setOpcode(X86::WAIT);
Out.EmitInstruction(Inst);
@@ -1189,11 +1187,8 @@
.Case("finit", "fninit")
.Case("fsave", "fnsave")
.Case("fstcw", "fnstcw")
- .Case("fstcww", "fnstcw")
.Case("fstenv", "fnstenv")
.Case("fstsw", "fnstsw")
- .Case("fstsww", "fnstsw")
- .Case("fclex", "fnclex")
.Default(0);
assert(Repl && "Unknown wait-prefixed instruction");
delete Operands[0];
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index 57634d3..0087e48 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -340,7 +340,7 @@
def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
-def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw{w}\t$dst">;
+def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
@@ -600,12 +600,12 @@
(outs), (ins), "fnstsw %ax", []>, DF;
def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
- (outs), (ins i16mem:$dst), "fnstcw{w}\t$dst",
+ (outs), (ins i16mem:$dst), "fnstcw\t$dst",
[(X86fp_cwd_get16 addr:$dst)]>;
let mayLoad = 1 in
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
- (outs), (ins i16mem:$dst), "fldcw{w}\t$dst", []>;
+ (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
// FPU control instructions
def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td
index 835794d..48b6d6e 100644
--- a/lib/Target/X86/X86InstrSystem.td
+++ b/lib/Target/X86/X86InstrSystem.td
@@ -310,13 +310,13 @@
def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
- "verr{w}\t$seg", []>, TB;
+ "verr\t$seg", []>, TB;
def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
- "verr{w}\t$seg", []>, TB;
+ "verr\t$seg", []>, TB;
def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
- "verw{w}\t$seg", []>, TB;
+ "verw\t$seg", []>, TB;
def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
- "verw{w}\t$seg", []>, TB;
+ "verw\t$seg", []>, TB;
//===----------------------------------------------------------------------===//
// Descriptor-table support instructions