commit 0e31d5cf80b6efb6f7a9ca7778503c575a8038e9
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:19:16 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:19:16 2009 +0000
tree 11bee0cb2814e7be7ea8aa1aa090d2ff3e30739f
parent 2c97ae8826371dc5b4dc119d7576443ebd39b7b2

Allow FP arguments pass / return

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76015 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZISelLowering.cpp

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 364d688..f25c337 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -173,33 +173,42 @@
     if (VA.isRegLoc()) {
       // Arguments passed in registers
       MVT RegVT = VA.getLocVT();
+      TargetRegisterClass *RC;
       switch (RegVT.getSimpleVT()) {
       default:
         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
              << RegVT.getSimpleVT()
              << "\n";
         abort();
-      case MVT::i64:
-        unsigned VReg =
-          RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
-        RegInfo.addLiveIn(VA.getLocReg(), VReg);
-        SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
-
-        // If this is an 8/16/32-bit value, it is really passed promoted to 64
-        // bits. Insert an assert[sz]ext to capture this, then truncate to the
-        // right size.
-        if (VA.getLocInfo() == CCValAssign::SExt)
-          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
-                                 DAG.getValueType(VA.getValVT()));
-        else if (VA.getLocInfo() == CCValAssign::ZExt)
-          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
-                                 DAG.getValueType(VA.getValVT()));
-
-        if (VA.getLocInfo() != CCValAssign::Full)
-          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
-
-        ArgValues.push_back(ArgValue);
+       case MVT::i64:
+        RC = SystemZ::GR64RegisterClass;
+        break;
+       case MVT::f32:
+        RC = SystemZ::FP32RegisterClass;
+        break;
+       case MVT::f64:
+        RC = SystemZ::FP64RegisterClass;
+        break;
       }
+
+      unsigned VReg = RegInfo.createVirtualRegister(RC);
+      RegInfo.addLiveIn(VA.getLocReg(), VReg);
+      SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
+
+      // If this is an 8/16/32-bit value, it is really passed promoted to 64
+      // bits. Insert an assert[sz]ext to capture this, then truncate to the
+      // right size.
+      if (VA.getLocInfo() == CCValAssign::SExt)
+        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
+                               DAG.getValueType(VA.getValVT()));
+      else if (VA.getLocInfo() == CCValAssign::ZExt)
+        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
+                               DAG.getValueType(VA.getValVT()));
+
+      if (VA.getLocInfo() != CCValAssign::Full)
+        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
+
+      ArgValues.push_back(ArgValue);
     } else {
       // Sanity check
       assert(VA.isMemLoc());