CellSPU testcase, extract_elt.ll: extract vector element.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45219 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 7d22187..2ab4841 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2101,7 +2101,7 @@
}
// Need to generate shuffle mask and extract:
- int prefslot_begin, prefslot_end;
+ int prefslot_begin = -1, prefslot_end = -1;
int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8;
switch (VT) {
@@ -2123,6 +2123,9 @@
}
}
+ assert(prefslot_begin != -1 && prefslot_end != -1 &&
+ "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
+
for (int i = 0; i < 16; ++i) {
// zero fill uppper part of preferred slot, don't care about the
// other slots:
@@ -2134,7 +2137,7 @@
? 0x80
: elt_byte + (i - prefslot_begin));
- ShufMask[i] = DAG.getConstant(mask_val, MVT::i16);
+ ShufMask[i] = DAG.getConstant(mask_val, MVT::i8);
} else
ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
}