commit 0fcdd8b2cc2b1bcf0aa64870d5269f9ac6dc76c0
author Hal Finkel <hfinkel@anl.gov> Wed Jun 20 15:43:03 2012 +0000
committer Hal Finkel <hfinkel@anl.gov> Wed Jun 20 15:43:03 2012 +0000
tree 59e03dedcaa6ca8f158a1ac91440dcc484557817
parent d65e463ff9327d168e8389e5c9a9f16a601be8a5

Add support for generating reg+reg (indexed) pre-inc loads on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 48feb98..dc50d86 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1106,13 +1106,8 @@
     return false;
 
   if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
-    if (isa<StoreSDNode>(N)) {
-      AM = ISD::PRE_INC;
-      return true;
-    }
-
-    // FIXME: reg+reg preinc loads
-    return false;
+    AM = ISD::PRE_INC;
+    return true;
   }
 
   // LDU/STU use reg+imm*4, others use reg+imm.