commit 133f079c8cf966d2222c2dda2de56d2cc600497e
author Chris Lattner <sabre@nondot.org> Mon Oct 28 04:45:29 2002 +0000
committer Chris Lattner <sabre@nondot.org> Mon Oct 28 04:45:29 2002 +0000
tree 4c9d473350fd191174f5bfe59cb66b24f699375e
parent 6d6c3f86186333037f2fd3fb001e8b2998c080d9

Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4331 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAlloc/PhyRegAlloc.cpp

diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 4dcd44f..9660e9f 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -539,8 +539,8 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
         {
           MachineOperand& Op = MInst->getOperand(OpNum);
-          if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-              Op.getOperandType() ==  MachineOperand::MO_CCRegister)
+          if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+              Op.getType() ==  MachineOperand::MO_CCRegister)
             {
               const Value *const Val =  Op.getVRegValue();
           
@@ -750,7 +750,7 @@
                                      std::vector<MachineInstr*>& MIBef,
                                      std::vector<MachineInstr*>& MIAft) {
   
-  RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+  RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
   
   int RegU =  getUnusedUniRegAtMI(RC, MInst, LVSetBef);
   
@@ -766,8 +766,8 @@
     int scratchRegType = -1;
     if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
       {
-        int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
-                                                   MInst, MIBef, MIAft);
+        int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+                                             MInst, MIBef, MIAft);
         assert(scratchReg != MRI.getInvalidRegNum());
         
         // We may as well hold the value in the scratch register instead
@@ -893,8 +893,8 @@
     {
       const MachineOperand& Op = MInst->getOperand(OpNum);
       
-      if (Op.getOperandType() == MachineOperand::MO_VirtualRegister || 
-          Op.getOperandType() == MachineOperand::MO_CCRegister)
+      if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
+          MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
           if (MRI.getRegClassIDOfValue(Val) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
@@ -971,9 +971,9 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
 	MachineOperand& Op = MInst->getOperand(OpNum);
 
-	if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-	    Op.getOperandType() ==  MachineOperand::MO_CCRegister /*|| 
-	    Op.getOperandType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
+	if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+	    Op.getType() ==  MachineOperand::MO_CCRegister /*|| 
+	    Op.getType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
 
 	  const Value *const Val = Op.getVRegValue () ;
 	  // ****this code is temporary till NULL Values are fixed
@@ -1005,7 +1005,7 @@
 	  }
 
 	} 
-	else if (Op.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+	else if (Op.getType() ==  MachineOperand::MO_MachineRegister) {
 	  cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
 	}