| commit | 13af222bab6fdc77d8193eb38e78a9cbed1d9d1f | [log] [tgz] |
|---|---|---|
| author | Jim Grosbach <grosbach@apple.com> | Wed Nov 30 18:21:25 2011 +0000 |
| committer | Jim Grosbach <grosbach@apple.com> | Wed Nov 30 18:21:25 2011 +0000 |
| tree | 96cebac821b4d37db7b673d1939f7b47b69ee1bf | |
| parent | 78647434ea861806f0c75ef20afe12f3ff6dbbec [diff] [blame] |
ARM parsing for VLD1 two register all lanes, no writeback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a96b37d..c24335c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -977,6 +977,11 @@ return VectorList.Count == 1; } + bool isVecListTwoDAllLanes() const { + if (Kind != k_VectorListAllLanes) return false; + return VectorList.Count == 2; + } + bool isVectorIndex8() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < 8;